59 lines
2.2 KiB
Plaintext
59 lines
2.2 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 8.2.03i Trace
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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C:\Xilinx\bin\nt\trce.exe -ise C:/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise
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-e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf -ucf
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C:/brad/pdp8/synth/s3board.ucf
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Design file: top.ncd
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Physical constraint file: top.pcf
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Device,speed: xc3s1000,-5 (PRODUCTION 1.39 2006-08-18)
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Report level: error report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock sysclk
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--------------+------------+------------+------------------+--------+
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| Setup to | Hold to | | Clock |
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Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
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--------------+------------+------------+------------------+--------+
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slideswitch<2>| 4.986(R)| -1.884(R)|sysclk_BUFGP | 0.000|
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slideswitch<3>| 5.549(R)| -2.335(R)|sysclk_BUFGP | 0.000|
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--------------+------------+------------+------------------+--------+
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Clock to Setup on destination clock sysclk
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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sysclk | 4.720| | | |
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---------------+---------+---------+---------+---------+
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Analysis completed Fri Apr 23 22:48:33 2010
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 144 MB
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