302 lines
21 KiB
Plaintext
302 lines
21 KiB
Plaintext
Release 8.2.03i Map I.34
|
|
Xilinx Mapping Report File for Design 'top'
|
|
|
|
Design Information
|
|
------------------
|
|
Command Line : C:\Xilinx\bin\nt\map.exe -ise C:/brad/pdp8/xilinx/pdp8/pdp8.ise
|
|
-intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd
|
|
top.ngd top.pcf
|
|
Target Device : xc3s1000
|
|
Target Package : ft256
|
|
Target Speed : -5
|
|
Mapper Version : spartan3 -- $Revision: 1.34.32.1 $
|
|
Mapped Date : Fri Apr 23 22:47:42 2010
|
|
|
|
Design Summary
|
|
--------------
|
|
Number of errors: 0
|
|
Number of warnings: 12
|
|
Logic Utilization:
|
|
Total Number Slice Registers: 493 out of 15,360 3%
|
|
Number used as Flip Flops: 481
|
|
Number used as Latches: 12
|
|
Number of 4 input LUTs: 1,605 out of 15,360 10%
|
|
Logic Distribution:
|
|
Number of occupied Slices: 1,120 out of 7,680 14%
|
|
Number of Slices containing only related logic: 1,120 out of 1,120 100%
|
|
Number of Slices containing unrelated logic: 0 out of 1,120 0%
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
|
Total Number 4 input LUTs: 1,964 out of 15,360 12%
|
|
Number used as logic: 1,605
|
|
Number used as a route-thru: 167
|
|
Number used for 32x1 RAMs: 192
|
|
(Two LUTs used per 32x1 RAM)
|
|
Number of bonded IOBs: 116 out of 173 67%
|
|
IOB Flip Flops: 14
|
|
Number of GCLKs: 3 out of 8 37%
|
|
|
|
Total equivalent gate count for design: 40,343
|
|
Additional JTAG gate count for IOBs: 5,568
|
|
Peak Memory Usage: 173 MB
|
|
|
|
NOTES:
|
|
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
|
Map gives priority to combine logic that is related. Doing so results in
|
|
the best timing performance.
|
|
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
|
related logic packing.
|
|
|
|
Note that once logic distribution reaches the 99% level through related
|
|
logic packing, this does not mean the device is completely utilized.
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
|
unrelated logic packing may adversely affect the overall timing performance
|
|
of your design.
|
|
|
|
Table of Contents
|
|
-----------------
|
|
Section 1 - Errors
|
|
Section 2 - Warnings
|
|
Section 3 - Informational
|
|
Section 4 - Removed Logic Summary
|
|
Section 5 - Removed Logic
|
|
Section 6 - IOB Properties
|
|
Section 7 - RPMs
|
|
Section 8 - Guide Report
|
|
Section 9 - Area Group and Partition Summary
|
|
Section 10 - Modular Design Summary
|
|
Section 11 - Timing Report
|
|
Section 12 - Configuration String Information
|
|
|
|
Section 1 - Errors
|
|
------------------
|
|
|
|
Section 2 - Warnings
|
|
--------------------
|
|
WARNING:LIT:243 - Logical network slideswitch<7>_IBUF has no load.
|
|
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 6
|
|
more times for the following (max. 5 shown):
|
|
slideswitch<6>_IBUF,
|
|
slideswitch<5>_IBUF,
|
|
slideswitch<4>_IBUF,
|
|
button<2>_IBUF,
|
|
button<1>_IBUF
|
|
To see the details of these warning messages, please use the -detail switch.
|
|
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
|
|
symbol "physical_group_clk/clk_BUFG" (output signal=clk) has a mix of clock
|
|
and non-clock loads. The non-clock loads are:
|
|
Pin D of clk
|
|
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
|
|
symbol
|
|
"physical_group_io/tt/baud_rate_generator/rx_baud_clk/io/tt/baud_rate_generat
|
|
or/rx_baud_clk_BUFG" (output signal=io/tt/baud_rate_generator/rx_baud_clk)
|
|
has a mix of clock and non-clock loads. The non-clock loads are:
|
|
Pin D of io/tt/baud_rate_generator/rx_baud_clk
|
|
WARNING:PhysDesignRules:372 - Gated clock. Clock net ram_rd is sourced by a
|
|
combinatorial pin. This is not good design practice. Use the CE pin to
|
|
control the loading of data into the flip-flop.
|
|
WARNING:PhysDesignRules:367 - The signal <slideswitch<4>_IBUF> is incomplete.
|
|
The signal does not drive any load pins in the design.
|
|
WARNING:PhysDesignRules:367 - The signal <slideswitch<5>_IBUF> is incomplete.
|
|
The signal does not drive any load pins in the design.
|
|
WARNING:PhysDesignRules:367 - The signal <slideswitch<6>_IBUF> is incomplete.
|
|
The signal does not drive any load pins in the design.
|
|
WARNING:PhysDesignRules:367 - The signal <slideswitch<7>_IBUF> is incomplete.
|
|
The signal does not drive any load pins in the design.
|
|
WARNING:PhysDesignRules:367 - The signal <button<0>_IBUF> is incomplete. The
|
|
signal does not drive any load pins in the design.
|
|
WARNING:PhysDesignRules:367 - The signal <button<1>_IBUF> is incomplete. The
|
|
signal does not drive any load pins in the design.
|
|
WARNING:PhysDesignRules:367 - The signal <button<2>_IBUF> is incomplete. The
|
|
signal does not drive any load pins in the design.
|
|
|
|
Section 3 - Informational
|
|
-------------------------
|
|
INFO:MapLib:562 - No environment variables are currently set.
|
|
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
|
|
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
|
|
BUFG symbol "clk_BUFG" (output signal=clk),
|
|
BUFG symbol "io/tt/baud_rate_generator/rx_baud_clk_BUFG" (output
|
|
signal=io/tt/baud_rate_generator/rx_baud_clk),
|
|
BUFGP symbol "sysclk_BUFGP" (output signal=sysclk_BUFGP)
|
|
|
|
Section 4 - Removed Logic Summary
|
|
---------------------------------
|
|
2 block(s) optimized away
|
|
|
|
Section 5 - Removed Logic
|
|
-------------------------
|
|
|
|
Optimized Block(s):
|
|
TYPE BLOCK
|
|
GND XST_GND
|
|
VCC XST_VCC
|
|
|
|
To enable printing of redundant blocks removed and signals merged, set the
|
|
detailed map report option and rerun map.
|
|
|
|
Section 6 - IOB Properties
|
|
--------------------------
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
|
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
|
|
| | | | | Strength | Rate | | | Delay |
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
|
| button<0> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| button<1> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| button<2> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| button<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
|
|
| ide_cs<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_cs<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_da<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_da<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_da<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_data_bus<0> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<1> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<2> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<3> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<4> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<5> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<6> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<7> | IOB | BIDIR | LVTTL | 24 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<8> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<9> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<10> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<11> | IOB | BIDIR | LVTTL | 12 | SLOW | INFF1 | | IFD |
|
|
| ide_data_bus<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_data_bus<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_data_bus<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_data_bus<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_dior | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| ide_diow | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
|
|
| led<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| led<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| rs232_rxd | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
|
|
| rs232_txd | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg_an<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg_an<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg_an<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sevenseg_an<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| slideswitch<0> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<1> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<2> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<3> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<4> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<5> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<6> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| slideswitch<7> | IOB | INPUT | LVCMOS25 | | | | | |
|
|
| sram1_ce_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<0> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<1> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<2> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<3> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<4> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<5> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<6> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<7> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<8> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<9> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<10> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<11> | IOB | BIDIR | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<12> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<13> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<14> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_io<15> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_lb_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram1_ub_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram2_ce_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_io<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_lb_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram2_ub_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
|
|
| sram_a<0> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<1> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<2> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<3> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<4> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<5> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<6> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<7> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<8> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<9> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<10> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<11> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<12> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<13> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<14> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<15> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<16> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_a<17> | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_oe_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sram_we_n | IOB | OUTPUT | LVCMOS25 | 12 | FAST | | | |
|
|
| sysclk | IOB | INPUT | LVCMOS25 | | | | | |
|
|
+------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
Section 7 - RPMs
|
|
----------------
|
|
|
|
Section 8 - Guide Report
|
|
------------------------
|
|
Guide not run on this design.
|
|
|
|
Section 9 - Area Group and Partition Summary
|
|
--------------------------------------------
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
Area Group Information
|
|
----------------------
|
|
|
|
No area groups were found in this design.
|
|
|
|
----------------------
|
|
|
|
Section 10 - Modular Design Summary
|
|
-----------------------------------
|
|
Modular Design not used for this design.
|
|
|
|
Section 11 - Timing Report
|
|
--------------------------
|
|
This design was not run using timing mode.
|
|
|
|
Section 12 - Configuration String Details
|
|
-----------------------------------------
|
|
Use the "-detail" map option to print out Configuration Strings
|