525 lines
22 KiB
Plaintext
525 lines
22 KiB
Plaintext
Release 8.2i - xst I.31
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Reading design: fpga.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "fpga.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "fpga"
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Output Format : NGC
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Target Device : xc2s200-5-fg256
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---- Source Options
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Top Module Name : fpga
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : lut
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100
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Add Generic Clock Buffer(BUFG) : 4
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : fpga.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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tristate2logic : Yes
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../v/ps2.v" in library work
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Compiling verilog file "../../v/fpga2.v" in library work
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Module <ps2> compiled
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Module <fpga> compiled
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No errors in compilation
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Analysis of file <"fpga.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <fpga> in library <work>.
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Analyzing hierarchy for module <ps2> in library <work> with parameters.
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PS2_FREQ = "00000000000000000000000000001010"
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KEY_RELEASE = "11110000"
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FREQ = "00000000000000000110000110101000"
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TIMEOUT = "00000000000000000000100111000100"
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <fpga>.
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Module <fpga> is correct for synthesis.
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Analyzing module <ps2> in library <work>.
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FREQ = 32'sb00000000000000000110000110101000
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PS2_FREQ = 32'sb00000000000000000000000000001010
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TIMEOUT = 32'sb00000000000000000000100111000100
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KEY_RELEASE = 8'b11110000
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Module <ps2> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <ps2>.
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Related source file is "../../v/ps2.v".
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Found 14-bit adder for signal <$addsub0000> created at line 93.
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Found 4-bit adder for signal <$addsub0001> created at line 103.
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Found 4-bit register for signal <bitcnt_r>.
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Found 4-bit 4-to-1 multiplexer for signal <bitcnt_x>.
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Found 1-bit register for signal <error_r>.
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Found 1-bit register for signal <keyrel_r>.
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Found 1-bit 4-to-1 multiplexer for signal <keyrel_x>.
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Found 5-bit register for signal <ps2_clk_r>.
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Found 1-bit register for signal <rdy_r>.
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Found 10-bit register for signal <sc_r>.
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Found 14-bit register for signal <timer_r>.
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Summary:
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inferred 36 D-type flip-flop(s).
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inferred 2 Adder/Subtractor(s).
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inferred 5 Multiplexer(s).
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Unit <ps2> synthesized.
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Synthesizing Unit <fpga>.
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Related source file is "../../v/fpga2.v".
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WARNING:Xst:1306 - Output <vga_hsync_n> is never assigned.
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WARNING:Xst:1306 - Output <vga_red0> is never assigned.
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WARNING:Xst:1306 - Output <vga_red1> is never assigned.
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WARNING:Xst:1306 - Output <vga_red2> is never assigned.
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WARNING:Xst:1306 - Output <vga_green0> is never assigned.
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WARNING:Xst:1306 - Output <vga_green1> is never assigned.
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WARNING:Xst:1306 - Output <vga_green2> is never assigned.
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WARNING:Xst:647 - Input <clkb> is never used.
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WARNING:Xst:1306 - Output <vga_blue0> is never assigned.
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WARNING:Xst:1306 - Output <vga_blue1> is never assigned.
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WARNING:Xst:1306 - Output <vga_blue2> is never assigned.
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WARNING:Xst:1306 - Output <vga_vsync_n> is never assigned.
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WARNING:Xst:1780 - Signal <vsync> is never used or assigned.
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WARNING:Xst:646 - Signal <kb_scancode<7>> is assigned but never used.
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WARNING:Xst:646 - Signal <kb_bsy> is assigned but never used.
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WARNING:Xst:1780 - Signal <hsync> is never used or assigned.
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WARNING:Xst:1780 - Signal <pixel> is never used or assigned.
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WARNING:Xst:1780 - Signal <data> is never used or assigned.
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Found finite state machine <FSM_0> for signal <gray_cnt>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 4 |
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| Inputs | 0 |
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| Outputs | 2 |
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| Clock | clka (rising_edge) |
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| Reset | reset_n (negative) |
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| Reset type | asynchronous |
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| Reset State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 1-bit register for signal <rdy>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 D-type flip-flop(s).
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Unit <fpga> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 2
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14-bit adder : 1
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4-bit adder : 1
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# Registers : 8
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1-bit register : 4
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10-bit register : 1
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14-bit register : 1
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4-bit register : 1
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5-bit register : 1
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# Multiplexers : 2
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1-bit 4-to-1 multiplexer : 1
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4-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <gray_cnt> on signal <gray_cnt[1:2]> with gray encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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01 | 01
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11 | 11
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10 | 10
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-------------------
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Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 1
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# Adders/Subtractors : 2
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14-bit adder : 1
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4-bit adder : 1
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# Registers : 39
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Flip-Flops : 39
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# Multiplexers : 2
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1-bit 4-to-1 multiplexer : 1
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4-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <fpga> ...
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Optimizing unit <ps2> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 1.
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Final Macro Processing ...
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Processing Unit <fpga> :
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INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <ps2/ps2_clk_r_1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
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INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <ps2/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
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Unit <fpga> processed.
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 39
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Flip-Flops : 39
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : fpga.ngr
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Top Level Output File Name : fpga
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : NO
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Design Statistics
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# IOs : 24
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Cell Usage :
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# BELS : 85
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# GND : 1
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# INV : 4
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# LUT1 : 13
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# LUT2 : 16
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# LUT3 : 2
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# LUT3_L : 1
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# LUT4 : 14
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# LUT4_D : 3
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# LUT4_L : 2
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# MUXCY : 13
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# MUXF5 : 2
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# VCC : 1
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# XORCY : 13
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# FlipFlops/Latches : 39
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# FDC : 24
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# FDCE : 10
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# FDP : 5
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# Clock Buffers : 2
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# BUFG : 1
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# BUFGP : 1
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# IO Buffers : 11
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# IBUF : 3
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# OBUF : 8
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 2s200fg256-5
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Number of Slices: 34 out of 2352 1%
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Number of Slice Flip Flops: 39 out of 4704 0%
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Number of 4 input LUTs: 55 out of 4704 1%
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Number of IOs: 24
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Number of bonded IOBs: 12 out of 180 6%
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Number of GCLKs: 2 out of 4 50%
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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ps2/rdy_r | NONE(rdy) | 1 |
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clka | BUFGP | 2 |
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gray_cnt_FFd11 | BUFG | 36 |
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-----------------------------------+------------------------+-------+
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INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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Asynchronous Control Signals Information:
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----------------------------------------
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-------------------------------------+------------------------+-------+
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Control Signal | Buffer(FF name) | Load |
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-------------------------------------+------------------------+-------+
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ps2/rst_n_inv(ps2/rst_n_inv1_INV_0:O)| NONE(rdy) | 39 |
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-------------------------------------+------------------------+-------+
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Timing Summary:
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---------------
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Speed Grade: -5
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Minimum period: 10.147ns (Maximum Frequency: 98.551MHz)
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Minimum input arrival time before clock: 2.827ns
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Maximum output required time after clock: 8.329ns
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Maximum combinational path delay: No path found
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'ps2/rdy_r'
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Clock period: 5.188ns (frequency: 192.753MHz)
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Total number of paths / destination ports: 1 / 1
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-------------------------------------------------------------------------
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Delay: 5.188ns (Levels of Logic = 1)
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Source: rdy (FF)
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Destination: rdy (FF)
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Source Clock: ps2/rdy_r rising
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Destination Clock: ps2/rdy_r rising
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Data Path: rdy to rdy
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDC:C->Q 2 1.292 1.340 rdy (rdy)
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INV:I->O 1 0.653 1.150 _not00011_INV_0 (_not0001)
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FDC:D 0.753 rdy
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----------------------------------------
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Total 5.188ns (2.698ns logic, 2.490ns route)
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(52.0% logic, 48.0% route)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'clka'
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Clock period: 9.821ns (frequency: 101.823MHz)
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Total number of paths / destination ports: 2 / 2
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-------------------------------------------------------------------------
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Delay: 9.821ns (Levels of Logic = 2)
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Source: gray_cnt_FFd1 (FF)
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Destination: gray_cnt_FFd2 (FF)
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Source Clock: clka rising
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Destination Clock: clka rising
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Data Path: gray_cnt_FFd1 to gray_cnt_FFd2
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDC:C->Q 1 1.292 1.150 gray_cnt_FFd1 (gray_cnt_FFd11)
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BUFG:I->O 37 0.773 4.050 gray_cnt_FFd1_BUFG (gray_cnt_FFd1)
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INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In)
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FDC:D 0.753 gray_cnt_FFd2
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----------------------------------------
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Total 9.821ns (3.471ns logic, 6.350ns route)
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(35.3% logic, 64.7% route)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'gray_cnt_FFd11'
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Clock period: 10.147ns (frequency: 98.551MHz)
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Total number of paths / destination ports: 389 / 44
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-------------------------------------------------------------------------
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Delay: 10.147ns (Levels of Logic = 4)
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Source: ps2/timer_r_7 (FF)
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Destination: ps2/bitcnt_r_1 (FF)
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Source Clock: gray_cnt_FFd11 rising
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Destination Clock: gray_cnt_FFd11 rising
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Data Path: ps2/timer_r_7 to ps2/bitcnt_r_1
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDC:C->Q 2 1.292 1.340 ps2/timer_r_7 (ps2/timer_r_7)
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LUT4:I0->O 1 0.653 1.150 ps2/_cmp_eq00018 (ps2/_cmp_eq0001_map32)
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LUT4:I0->O 6 0.653 1.850 ps2/_cmp_eq000156 (ps2/_cmp_eq0001)
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LUT4_D:I3->O 1 0.653 1.150 ps2/bitcnt_x<1>111 (ps2/N3)
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LUT4:I1->O 1 0.653 0.000 ps2/bitcnt_x<1>1 (ps2/bitcnt_x<1>)
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FDC:D 0.753 ps2/bitcnt_r_1
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----------------------------------------
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Total 10.147ns (4.657ns logic, 5.490ns route)
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(45.9% logic, 54.1% route)
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=========================================================================
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Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd11'
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Total number of paths / destination ports: 2 / 2
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-------------------------------------------------------------------------
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Offset: 2.827ns (Levels of Logic = 1)
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Source: ps2_clk (PAD)
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Destination: ps2/ps2_clk_r_0 (FF)
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Destination Clock: gray_cnt_FFd11 rising
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Data Path: ps2_clk to ps2/ps2_clk_r_0
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 1 0.924 1.150 ps2_clk_IBUF (ps2_clk_IBUF)
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FDP:D 0.753 ps2/ps2_clk_r_0
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----------------------------------------
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Total 2.827ns (1.677ns logic, 1.150ns route)
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(59.3% logic, 40.7% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'gray_cnt_FFd11'
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Total number of paths / destination ports: 7 / 7
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-------------------------------------------------------------------------
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Offset: 8.329ns (Levels of Logic = 1)
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Source: ps2/sc_r_6 (FF)
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Destination: fpga_din_d0 (PAD)
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Source Clock: gray_cnt_FFd11 rising
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Data Path: ps2/sc_r_6 to fpga_din_d0
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDCE:C->Q 3 1.292 1.480 ps2/sc_r_6 (ps2/sc_r_6)
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OBUF:I->O 5.557 fpga_din_d0_OBUF (fpga_din_d0)
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----------------------------------------
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Total 8.329ns (6.849ns logic, 1.480ns route)
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(82.2% logic, 17.8% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'ps2/rdy_r'
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Total number of paths / destination ports: 1 / 1
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-------------------------------------------------------------------------
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Offset: 8.189ns (Levels of Logic = 1)
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Source: rdy (FF)
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Destination: fpga_d1 (PAD)
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Source Clock: ps2/rdy_r rising
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Data Path: rdy to fpga_d1
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDC:C->Q 2 1.292 1.340 rdy (rdy)
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OBUF:I->O 5.557 fpga_d1_OBUF (fpga_d1)
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----------------------------------------
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Total 8.189ns (6.849ns logic, 1.340ns route)
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(83.6% logic, 16.4% route)
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=========================================================================
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CPU : 7.48 / 7.59 s | Elapsed : 8.00 / 8.00 s
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-->
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Total memory usage is 239200 kilobytes
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|
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 18 ( 0 filtered)
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Number of infos : 3 ( 0 filtered)
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|