165 lines
7.0 KiB
HTML
165 lines
7.0 KiB
HTML
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD COLSPAN='4'><B>PS2 Project Status</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>ps2.ise</TD>
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<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
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<TD>Programming File Generated</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>fpga</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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<TD ALIGN=LEFT>No Errors</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc2s200-5fg256</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>21 Warnings</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
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<TD>ISE 8.2i</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
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<TD>Wed Dec 27 10:45:57 2006</TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>PS2 Partition Summary</B></TD></TR>
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<TR><TD COLSPAN='4'>No partition information was found.</TD></TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='5'><B>Device Utilization Summary</B></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
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<TD ALIGN=RIGHT>37</TD>
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<TD ALIGN=RIGHT>4,704</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
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<TD ALIGN=RIGHT>39</TD>
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<TD ALIGN=RIGHT>4,704</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of occupied Slices</TD>
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<TD ALIGN=RIGHT>39</TD>
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<TD ALIGN=RIGHT>2,352</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD>
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<TD ALIGN=RIGHT>39</TD>
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<TD ALIGN=RIGHT>39</TD>
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<TD ALIGN=RIGHT>100%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>39</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD>
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<TD ALIGN=RIGHT>52</TD>
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<TD ALIGN=RIGHT>4,704</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
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<TD ALIGN=RIGHT>39</TD>
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<TD> </TD>
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<TD> </TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD>
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<TD ALIGN=RIGHT>13</TD>
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<TD> </TD>
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<TD> </TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of bonded <A HREF_DISABLED='fpga_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD>
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<TD ALIGN=RIGHT>11</TD>
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<TD ALIGN=RIGHT>176</TD>
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<TD ALIGN=RIGHT>6%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
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<TD ALIGN=RIGHT>2</TD>
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<TD> </TD>
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<TD> </TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of GCLKs</TD>
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<TD ALIGN=RIGHT>2</TD>
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<TD ALIGN=RIGHT>4</TD>
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<TD ALIGN=RIGHT>50%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of GCLKIOBs</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD ALIGN=RIGHT>4</TD>
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<TD ALIGN=RIGHT>25%</TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD>
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<TD ALIGN=RIGHT>630</TD>
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<TD> </TD>
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<TD> </TD>
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<TD> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Additional JTAG gate count for IOBs</TD>
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<TD ALIGN=RIGHT>576</TD>
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<TD> </TD>
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<TD> </TD>
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<TD> </TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Performance Summary</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
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<TD>0</TD>
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<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
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<TD><A HREF_DISABLED='fpga.pad?&DataKey=PinoutData'>Pinout Report</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD>
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<TD><A HREF_DISABLED='fpga.unroutes'>All Signals Completely Routed</A></TD>
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<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
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<TD><A HREF_DISABLED='fpga.par?&DataKey=ClocksData'>Clock Report</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
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<TD><A HREF_DISABLED='fpga.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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<TD BGCOLOR='#FFFF99'><B> </B></TD>
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<TD> </TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:27 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>18 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>3 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:36 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:44 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:52 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:18:57 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Dec 21 09:19:06 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR>
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<TR ALIGN=LEFT><TD>Xplorer Report</TD><TD> </TD><TD> </TD></TR>
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</TABLE>
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</BODY></HTML> |