105 lines
5.0 KiB
Plaintext
105 lines
5.0 KiB
Plaintext
Release 8.2i - Bitgen I.31
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Loading device for application Rf_Device from file 'v200.nph' in environment
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/opt/Xilinx.
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"fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5
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Opened constraints file fpga.pcf.
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Mon Jan 1 22:22:58 2007
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bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No fpga.ncd
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Summary of Bitgen Options:
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+----------------------+----------------------+
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| Option Name | Current Setting |
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+----------------------+----------------------+
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| Compress | (Not Specified)* |
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+----------------------+----------------------+
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| Readback | (Not Specified)* |
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+----------------------+----------------------+
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| DebugBitstream | No** |
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+----------------------+----------------------+
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| ConfigRate | 4** |
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+----------------------+----------------------+
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| StartupClk | Cclk** |
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+----------------------+----------------------+
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| CclkPin | Pullup** |
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+----------------------+----------------------+
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| DonePin | Pullup** |
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+----------------------+----------------------+
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| M0Pin | Pullup** |
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+----------------------+----------------------+
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| M1Pin | Pullup** |
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+----------------------+----------------------+
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| M2Pin | Pullup** |
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+----------------------+----------------------+
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| ProgPin | Pullup** |
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+----------------------+----------------------+
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| TckPin | Pullup** |
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+----------------------+----------------------+
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| TdiPin | Pullup** |
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+----------------------+----------------------+
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| TdoPin | Pullup |
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+----------------------+----------------------+
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| TmsPin | Pullup** |
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+----------------------+----------------------+
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| UnusedPin | Pulldown** |
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+----------------------+----------------------+
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| GSR_cycle | 6** |
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+----------------------+----------------------+
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| GWE_cycle | 6** |
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+----------------------+----------------------+
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| GTS_cycle | 5** |
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+----------------------+----------------------+
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| LCK_cycle | NoWait** |
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+----------------------+----------------------+
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| DONE_cycle | 4** |
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+----------------------+----------------------+
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| Persist | No* |
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+----------------------+----------------------+
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| DriveDone | No** |
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+----------------------+----------------------+
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| DonePipe | No** |
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+----------------------+----------------------+
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| Security | None** |
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+----------------------+----------------------+
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| UserID | 0xFFFFFFFF** |
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+----------------------+----------------------+
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| Gclkdel0 | 11111** |
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+----------------------+----------------------+
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| Gclkdel1 | 11111** |
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+----------------------+----------------------+
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| Gclkdel2 | 11111** |
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+----------------------+----------------------+
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| Gclkdel3 | 11111** |
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+----------------------+----------------------+
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| ActiveReconfig | No* |
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+----------------------+----------------------+
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| ActivateGclk | No* |
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+----------------------+----------------------+
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| PartialMask0 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialMask1 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialGclk | (Not Specified)* |
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+----------------------+----------------------+
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| PartialLeft | (Not Specified)* |
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+----------------------+----------------------+
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| PartialRight | (Not Specified)* |
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+----------------------+----------------------+
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| IEEE1532 | No* |
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+----------------------+----------------------+
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| Binary | No** |
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+----------------------+----------------------+
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* Default setting.
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** The specified setting matches the default setting.
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Running DRC.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced
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by a combinatorial pin. This is not good design practice. Use the CE pin to
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control the loading of data into the flip-flop.
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DRC detected 0 errors and 1 warnings.
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Creating bit map...
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Saving bit stream in "fpga.bit".
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Bitstream generation is complete.
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