5 lines
248 B
Plaintext
5 lines
248 B
Plaintext
WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced
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by a combinatorial pin. This is not good design practice. Use the CE pin to
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control the loading of data into the flip-flop.
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DRC detected 0 errors and 1 warnings.
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