212 lines
8.3 KiB
Plaintext
212 lines
8.3 KiB
Plaintext
Release 8.2i par I.31
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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wide:: Mon Jan 01 22:22:21 2007
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par -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf
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Constraints file: fpga.pcf.
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Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
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"fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5
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Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
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Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
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the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
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balance between the fastest runtime and best performance, set the effort level to "med".
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Device speed data version: "PRODUCTION 1.27 2006-05-03".
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Device Utilization Summary:
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Number of BLOCKRAMs 7 out of 14 50%
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Number of GCLKs 3 out of 4 75%
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Number of External GCLKIOBs 1 out of 4 25%
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Number of LOCed GCLKIOBs 1 out of 1 100%
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Number of External IOBs 22 out of 176 12%
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Number of LOCed IOBs 22 out of 22 100%
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Number of SLICEs 402 out of 2352 17%
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Overall effort level (-ol): Standard
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard
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Starting Placer
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Phase 1.1
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Phase 1.1 (Checksum:98a557) REAL time: 4 secs
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Phase 2.31
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Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs
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Phase 3.23
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Phase 3.23 (Checksum:1c9c37d) REAL time: 4 secs
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Phase 4.3
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Phase 4.3 (Checksum:26259fc) REAL time: 4 secs
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Phase 5.5
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Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs
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Phase 6.8
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..................................................
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..............
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......................................................
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.......................................
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..........................................
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.................................
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Phase 6.8 (Checksum:bfc6cd) REAL time: 9 secs
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Phase 7.5
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Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs
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Phase 8.18
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Phase 8.18 (Checksum:4c4b3f8) REAL time: 14 secs
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Phase 9.5
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Phase 9.5 (Checksum:55d4a77) REAL time: 14 secs
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Writing design to file fpga.ncd
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Total REAL time to Placer completion: 14 secs
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Total CPU time to Placer completion: 14 secs
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Starting Router
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Phase 1: 3141 unrouted; REAL time: 16 secs
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Phase 2: 3034 unrouted; REAL time: 16 secs
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Phase 3: 910 unrouted; REAL time: 17 secs
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Phase 4: 910 unrouted; (187799) REAL time: 17 secs
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Phase 5: 909 unrouted; (0) REAL time: 18 secs
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Phase 6: 0 unrouted; (0) REAL time: 20 secs
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Phase 7: 0 unrouted; (0) REAL time: 20 secs
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Phase 8: 0 unrouted; (0) REAL time: 20 secs
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Total REAL time to Router completion: 20 secs
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Total CPU time to Router completion: 18 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| gray_cnt_FFd1 | GCLKBUF3| No | 78 | 0.209 | 0.796 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga/crtclk | GCLKBUF0| No | 30 | 0.098 | 0.768 |
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+---------------------+--------------+------+------+------------+-------------+
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| clka_BUFGP | GCLKBUF1| No | 1 | 0.000 | 0.747 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga/crt/ram_wclk | Local| | 14 | 1.258 | 3.885 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga/charload | Local| | 15 | 1.888 | 5.945 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga/vgacore/hblank | Local| | 12 | 0.087 | 3.941 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga/pclk<2> | Local| | 9 | 0.715 | 2.527 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga/crt/_or0000 | Local| | 2 | 0.000 | 0.700 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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The Delay Summary Report
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The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
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The AVERAGE CONNECTION DELAY for this design is: 2.379
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The MAXIMUM PIN DELAY IS: 7.048
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The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 6.411
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Listing Pin Delays by value: (nsec)
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d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 8.00 d >= 8.00
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--------- --------- --------- --------- --------- ---------
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574 826 763 511 459 0
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Timing Score: 0
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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Constraint | Requested | Actual | Logic | Absolute |Number of
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| | | Levels | Slack |errors
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net gra | N/A | 11.183ns | 5 | N/A | N/A
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y_cnt_FFd1 | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net vga | N/A | 8.284ns | 4 | N/A | N/A
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/crtclk | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | N/A | 7.120ns | 1 | N/A | N/A
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a_BUFGP | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net vga | N/A | 10.431ns | 0 | N/A | N/A
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/crt/ram_wclk | | | | |
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net vga | N/A | 9.916ns | 4 | N/A | N/A
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/vgacore/hblank | | | | |
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
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constraint does not cover any paths or that it has no requested value.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 22 secs
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Total CPU time to PAR completion: 20 secs
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Peak Memory Usage: 323 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 1
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Writing design to file fpga.ncd
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PAR done!
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