49 lines
1.6 KiB
Plaintext
49 lines
1.6 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 8.2i Trace
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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trce -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise -e 3 -l 3 -s 5
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-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf
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Design file: fpga.ncd
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Physical constraint file: fpga.pcf
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Device,speed: xc2s200,-5 (PRODUCTION 1.27 2006-05-03)
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Report level: error report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Clock to Setup on destination clock clka
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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clka | 7.120| | | |
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---------------+---------+---------+---------+---------+
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Analysis completed Mon Jan 1 22:22:52 2007
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 203 MB
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