153 lines
5.6 KiB
Plaintext
153 lines
5.6 KiB
Plaintext
Release 8.2i - xst I.31
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s
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Parameter xsthdpdir set to ./xst
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Reading design: fpga.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "fpga.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "fpga"
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Output Format : NGC
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Target Device : xc2s200-5-fg256
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---- Source Options
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Top Module Name : fpga
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : lut
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100
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Add Generic Clock Buffer(BUFG) : 4
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : fpga.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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tristate2logic : Yes
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../v/scancode2.v" in library work
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Compiling verilog include file "../../v/scancode_rom.v"
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Module <scancode_rom> compiled
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Module <scancode_convert> compiled
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Compiling verilog file "../../v/fpga3.v" in library work
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Module <test> compiled
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Module <fpga> compiled
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No errors in compilation
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Analysis of file <"fpga.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <fpga> in library <work>.
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Analyzing hierarchy for module <scancode_convert> in library <work>.
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Analyzing hierarchy for module <scancode_rom> in library <work>.
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <fpga>.
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Module <fpga> is correct for synthesis.
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Analyzing module <scancode_convert> in library <work>.
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ERROR:Xst:850 - "../../v/scancode2.v" line 63: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 69: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 75: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 80: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 87: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 92: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 93: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 101: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 109: Unsupported Event Control Statement.
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ERROR:Xst:850 - "../../v/scancode2.v" line 110: Unsupported Event Control Statement.
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Found 10 error(s). Aborting synthesis.
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-->
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Total memory usage is 216028 kilobytes
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Number of errors : 10 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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