67 lines
1.2 KiB
Verilog
67 lines
1.2 KiB
Verilog
// brg.v
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// baud rate generator for uart
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module brg(clk, reset, tx_baud_clk, rx_baud_clk);
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input clk;
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input reset;
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output tx_baud_clk;
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output rx_baud_clk;
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parameter SYS_CLK = 26'd50000000;
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parameter BAUD = 16'd9600;
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`ifdef sim_time
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parameter RX_CLK_DIV = 13'd5;
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parameter TX_CLK_DIV = 13'd5;
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`else
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parameter RX_CLK_DIV = SYS_CLK / (BAUD * 16 * 2);
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parameter TX_CLK_DIV = SYS_CLK / (BAUD * 2);
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`endif
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reg [12:0] rx_clk_div;
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reg [12:0] tx_clk_div;
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reg tx_baud_clk;
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reg rx_baud_clk;
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always @(posedge clk or posedge reset)
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if (reset)
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begin
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rx_clk_div <= 0;
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rx_baud_clk <= 0;
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end
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else
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if (rx_clk_div == RX_CLK_DIV)
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begin
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rx_clk_div <= 0;
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rx_baud_clk <= ~rx_baud_clk;
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end
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else
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begin
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rx_clk_div <= rx_clk_div + 13'b1;
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rx_baud_clk <= rx_baud_clk;
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end
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always @(posedge clk or posedge reset)
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if (reset)
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begin
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tx_clk_div <= 0;
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tx_baud_clk <= 0;
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end
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else
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if (tx_clk_div == TX_CLK_DIV)
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begin
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tx_clk_div <= 0;
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tx_baud_clk <= ~tx_baud_clk;
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end
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else
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begin
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tx_clk_div <= tx_clk_div + 13'b1;
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tx_baud_clk <= tx_baud_clk;
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end
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endmodule
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