704 lines
13 KiB
Verilog
704 lines
13 KiB
Verilog
// PDP-8
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// Based on descriptions in "Computer Engineering"
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// Nov 2005 Brad Parker brad@heeltoe.com
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// initial work; runs focal a bit
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// Dec 2006
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// cleaned up a little; now runs focal to prompt
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// moved i/o out to pdp8_io.v
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// added IF, DF, user mode
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// Apr 2009
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// major revamp for synthesis, removed latches, added muxes, new top
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//
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// TODO:
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// fully implement extended memory (IF & DF), user mode (KT8/I)
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// add df32/rf08
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// 6000 pws ac <= switches
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//
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//
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// Instruction format:
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//
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// 0 1 2 3 4 5 6 7 8 9 10 11
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// |--op--|
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// 0 and
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// 1 tad
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// 2 isz
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// 3 dca
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// 4 jms
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// 5 jmp
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// 6 iot
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// 7 opr
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// group 1
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// 0
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// |cla|clf| | |
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// | | |cma cml| |
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// |bsw 001 |
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// |ral 010 |
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// |rtl 011 |
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// |rar 100 |
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// |rtr 101 |
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// | |iac
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//
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// group 2
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// 1 0
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// |sma|sza|snl|skp| |
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// |cla|
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// |osr|hlt
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//
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// group 3
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// eae
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// 1 1
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// |cla|
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// |mqa|sca|mql|
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// |isn |
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//
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//
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//
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// cpu states
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//
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// F0 fetch
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// F1 incr pc
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// F2 write
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// F3 dispatch
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//
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// E0 read
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// E1 decode
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// E2 write
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// E3 load
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//
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// or
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//
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// D0 read
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// D1 wait
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// D2 write
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// D3 load
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//
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// H0 halted
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//
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// ------
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//
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// F0 fetch
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// check for interrupt
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//
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// F1 incr pc
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// if opr
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// group 1 processing
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// group 2 processing
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//
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// if iot
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//
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// incr pc or skip (incr pc by 2)
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//
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// F2 write
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// ma <= pc
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//
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// F3 dispatch
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// if opr
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// group1 processing
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//
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// if !opr && !iot
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// possible defer
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//
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//
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// D0
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// mb <= memory
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// D1
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// D2
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// D3
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//
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// E0
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// mb <= memory
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// E1
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// E2 write isz value
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// E3
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//
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//
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// extended memory
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//
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// 62n1 cdf change data field; df <= mb[5:3]
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// 62n2 cif change instruction field; if <= mb[5:3], after next jmp or jms
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// 6214 rdf read df into ac[5:3]
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// 6224 rif read if into ac[5:3]
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// 6234 rib read sf into ac[5:0], which is {if,df}
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// 6244 rmf restore memory field, sf => ib, df
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// (remember that on interrupt, sf <= {if,df})
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//
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module pdp8(clk, reset,
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ram_addr, ram_data_out, ram_data_in, ram_rd, ram_wr,
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io_select, io_data_out, io_data_in,
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io_data_avail, io_interrupt, io_skip,
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switches, iot, state, mb);
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input clk, reset;
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input [11:0] ram_data_in;
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output ram_rd;
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output ram_wr;
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output [11:0] ram_data_out;
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output [14:0] ram_addr;
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output [5:0] io_select;
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input [11:0] io_data_in;
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output [11:0] io_data_out;
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input io_data_avail;
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input io_interrupt;
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input io_skip;
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output iot;
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output [3:0] state;
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output [11:0] mb;
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input [11:0] switches;
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// memory buffer, holds data, instructions
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reg [11:0] mb;
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// generate address of work in memory being accessed
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wire [14:0] ma;
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// accumulator & link
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reg [11:0] ac;
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reg l;
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// MQ
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reg [11:0] mq;
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// program counter
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reg [11:0] pc;
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wire pc_incr, pc_skip;
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// instruction register
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reg [2:0] ir;
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// extended memory - instruction field & data field
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reg [2:0] IF;
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reg [2:0] DF;
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reg [2:0] IB;
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reg [5:0] SF;
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reg ib_pending;
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// user mode
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reg UB;
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reg UF;
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// processor state
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reg [3:0] state;
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wire [3:0] next_state;
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reg run;
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reg interrupt_enable;
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reg interrupt_cycle;
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reg interrupt_inhibit;
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reg interrupt_skip;
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reg interrupt;
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reg user_interrupt;
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wire skip_condition;
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wire fetch; // memory cycle to fetch instruction
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wire deferred;// memory cycle to get address of operand
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wire execute;// memory cycle to getch (store) operand and execute isn
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assign {fetch, deferred, execute} =
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(state[3:2] == 2'b00) ? 3'b100 :
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(state[3:2] == 2'b01) ? 3'b010 :
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(state[3:2] == 2'b10) ? 3'b001 :
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3'b000 ;
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// instruction op decode
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wire i_and,tad,isz,dca,jms,jmp,iot,opr;
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assign {i_and,tad,isz,dca,jms,jmp,iot,opr} =
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(ir == 3'b000) ? 8'b10000000 :
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(ir == 3'b001) ? 8'b01000000 :
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(ir == 3'b010) ? 8'b00100000 :
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(ir == 3'b011) ? 8'b00010000 :
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(ir == 3'b100) ? 8'b00001000 :
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(ir == 3'b101) ? 8'b00000100 :
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(ir == 3'b110) ? 8'b00000010 :
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8'b00000001 ;
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//-------------
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/*
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* note: bit numbering is opposite that used in "Computer Engineering"
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*
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* F1
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* if opr
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* if MB[8] and !MB[0]
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* begin
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* if skip.conditions ^ MB[3]
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* pc <= pc + 2
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* if skip.conditions == MB[3]
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* pc <= pc + 1 next
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* if MB[7]
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* ac <= 0
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*/
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assign skip_condition = (mb[6] && ac[11]) ||
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(mb[5] && (ac == 12'b0)) ||
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(mb[4] && l);
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assign pc_incr =
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(opr & !mb[8]) ||
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(opr && (mb[8] && !mb[0]) && (skip_condition == mb[3])) ||
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iot ||
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(!(opr || iot) && !interrupt_cycle);
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assign pc_skip =
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(opr && (mb[8] && !mb[0]) && (skip_condition ^ mb[3])) ||
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(iot && (io_skip || interrupt_skip));
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// (iot && mb[0] && io_skip);
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// cpu states
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parameter F0 = 4'b0000;
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parameter F1 = 4'b0001;
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parameter F2 = 4'b0010;
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parameter F3 = 4'b0011;
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parameter D0 = 4'b0100;
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parameter D1 = 4'b0101;
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parameter D2 = 4'b0110;
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parameter D3 = 4'b0111;
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parameter E0 = 4'b1000;
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parameter E1 = 4'b1001;
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parameter E2 = 4'b1010;
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parameter E3 = 4'b1011;
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parameter H0 = 4'b1100;
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//
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// cpu state state machine
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//
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// clock next cpu state at rising edge of clock
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//
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always @(posedge clk)
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if (reset)
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state <= 0;
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else
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state <= next_state;
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wire next_is_F0;
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wire next_is_E0;
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assign next_is_F0 = opr | iot | (!mb[8] & jmp);
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assign next_is_E0 = !mb[8] & !jmp;
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assign next_state = state == F0 ? F1 :
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state == F1 && (~iot | (iot & io_data_avail)) ? F2 :
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state == F2 ? F3 :
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state == F3 ? (~run ? H0 :
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next_is_F0 ? F0 :
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next_is_E0 ? E0 :
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D0) :
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state == D0 ? D1 :
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state == D1 ? D2 :
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state == D2 ? D3 :
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state == D3 ? (jmp ? F0 : E0) :
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state == E0 ? E1 :
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state == E1 ? E2 :
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state == E2 ? E3 :
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state == E3 ? F0 :
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state == H0 ? H0 :
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F0;
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//
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// pc
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//
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wire [11:0] pc_mux;
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always @(posedge clk)
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if (reset)
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pc <= 0;
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else
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begin
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if (state == F1) $display("pc_skip %b", pc_skip);
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//if (state == F1 || state == D3 || state == E3)
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//$display(" pc <- %o", pc_mux);
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pc <= pc_mux;
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end
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assign pc_mux = (state == F1 && pc_skip) ? (pc + 12'd2) :
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(state == F1 && pc_incr) ? (pc + 12'd1) :
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(state == F3 && !(opr || iot) && (!mb[8] & jmp)) ? ma :
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(state == D3 && jmp) ? mb :
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(state == E3 && jms) ? ma :
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(state == E3 && isz && mb == 12'b0) ? (pc + 12'd1) :
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pc;
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//
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// ram
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//
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assign ram_rd = (state == F0) ||
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(state == D0) ||
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(state == E0);
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assign ram_wr = (state == D2 && is_index_reg) ||
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(state == E2 && (isz || dca || jms));
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assign ram_addr = ma;
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assign ram_data_out = mb;
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assign io_select = mb[8:3];
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assign io_data_out = ac;
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//
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// ea calculation
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//
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reg [14:0] ea;
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always @(posedge clk)
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if (reset)
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ea <= 0;
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else
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if (state == F1)
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ea <= {DF, mb[7] ? pc[11:7] : 5'b0, mb[6:0]};
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else
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if (state == D3)
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ea <= mb;
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wire is_index_reg;
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assign is_index_reg = ea[11:3] == 8'h01;
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//
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// ma
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//
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assign ma = (state == F0) ? {IF, pc} :
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(state == F2 && (opr || iot)) ? {IF,pc} :
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((state == F3 || state == D0 || state == E0) &&
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(!opr && !iot)) ? ea :
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(state == D2) ? (is_index_reg ? ea : {DF,mb}) :
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(state == E2 ) ? ea :
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(state == E3 && jms) ? {ea[14:12], ea[11:0] + 12'b1} :
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15'b0;
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//
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// registers
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//
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always @(posedge clk)
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if (reset)
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begin
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mb <= 0;
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ac <= 0;
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mq <= 0;
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l <= 0;
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ir <= 0;
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run <= 1;
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interrupt_enable <= 0;
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interrupt_cycle <= 0;
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interrupt_inhibit <= 0;
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interrupt_skip <= 0;
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interrupt <= 0;
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user_interrupt <= 0;
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IF <= 0;
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DF <= 0;
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IB <= 0;
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SF <= 0;
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UF <= 0;
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UB <= 0;
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ib_pending <= 0;
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end
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else
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case (state)
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// FETCH
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F0:
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begin
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interrupt_skip <= 0;
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if (interrupt && interrupt_enable &&
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!interrupt_inhibit && !interrupt_cycle)
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begin
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$display("xxx interrupt, pc %o; %b %b %b",
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pc, interrupt, interrupt_enable, interrupt_cycle);
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interrupt_cycle <= 1;
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interrupt <= 0;
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interrupt_enable <= 0;
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// simulate a jsr to 0
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mb <= 12'o4000;
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ir <= 3'o4;
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SF <= {IF,DF};
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IF <= 3'b000;
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DF <= 3'b000;
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end
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else
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begin
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interrupt_cycle <= 0;
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//?? interrupt_inhibit <= 0;
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//?? ib_pending <= 0;
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//$display("read ram [%o] -> %o", ram_addr, ram_data_in);
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mb <= ram_data_in;
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ir <= ram_data_in[11:9];
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end
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end
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F1:
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begin
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if (opr)
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case ({mb[8],mb[0]})
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2'b0x: // group 1
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begin
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if (mb[7]) ac <= 0;
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if (mb[6]) l <= 0;
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if (mb[5]) ac <= ~ac;
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if (mb[4]) l <= ~l;
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end
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2'b10: // group 2
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begin
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if (mb[7])
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ac <= 0;
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end
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2'b11: // group 3
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begin
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if (mb[7])
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ac <= 0;
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end
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default:
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;
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endcase
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if (iot)
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begin
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case (io_select)
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6'b000000: // ION, IOF
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case (mb[2:0])
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3'b001: interrupt_enable <= 1;
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3'b010: interrupt_enable <= 0;
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3'b011: if (interrupt_enable)
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interrupt_skip <= 1;
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endcase
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6'b010xxx: // CDF..RMF
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begin
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case (mb[2:0])
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3'b001: DF <= mb[5:3]; // CDF
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3'b010: // CIF
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begin
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IB <= mb[5:3];
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ib_pending <= 1;
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interrupt_inhibit <= 1;
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end
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3'b100:
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case (io_select[2:0])
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3'b001: ac <= { 6'b0, DF, 3'b0 }; // RDF
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3'b010: ac <= { 6'b0, IF, 3'b0 }; // RIF
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3'b011: ac <= { 6'b0, SF }; // RIB
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3'b100: begin // RMF
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IB <= SF[5:3];
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DF <= SF[2:0];
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end
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endcase
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endcase
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end
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endcase // case(io_select)
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if (io_data_avail)
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begin
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//$display("io_data clock %o", io_data_in);
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ac <= io_data_in;
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end
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end // if (iot)
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if (io_interrupt)
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interrupt <= 1;
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end // case: F1
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F2:
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begin
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if (opr)
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begin
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// group 3
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if (mb[8] & mb[0])
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case ({mb[6:4]})
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3'b001: mq <= ac;
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3'b100: ac <= ac | mq;
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//3'b101: tmq <= mq;
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3'b100: ac <= mq;
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3'b101: ac <= mq;
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endcase
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end
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end
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F3:
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begin
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if (opr)
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begin
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// group 1
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if (!mb[8])
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begin
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if (mb[0]) // IAC
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{l,ac} <= {l,ac} + 1'b1;
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case (mb[3:1])
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3'b001: // BSW
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{l,ac} <= {l,ac[5:0],ac[11:6]};
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3'b010: // RAL
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{l,ac} <= {ac[11:0],l};
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3'b011: // RTL
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{l,ac} <= {ac[10:0],l,ac[11]};
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3'b100: // RAR
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{l,ac} <= {ac[0],l,ac[11:1]};
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3'b101: // RTR
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{l,ac} <= {ac[1:0],l,ac[11:2]};
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endcase
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end
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if (!UF)
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begin
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// group 2
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if (mb[8] & !mb[0])
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begin
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if (mb[2])
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ac <= ac | switches;
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if (mb[1])
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run <= 0;
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end
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end
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if (UF)
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begin
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// group 2 - user mode (halt & osr)
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if (mb[8] & !mb[0])
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begin
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if (mb[2])
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user_interrupt <= 1;
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if (mb[1])
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user_interrupt <= 1;
|
|
end
|
|
end
|
|
|
|
// group 3
|
|
if (mb[8] & mb[0])
|
|
begin
|
|
if (mb[7:4] == 4'b1101)
|
|
mq <= 0;
|
|
end
|
|
|
|
// ir <= 0;
|
|
// mb <= 0;
|
|
end // if (opr)
|
|
|
|
// if (iot)
|
|
// begin
|
|
// ir <= 0;
|
|
// mb <= 0;
|
|
// end
|
|
|
|
// if (!(opr || iot))
|
|
// begin
|
|
// if (!mb[8] & jmp)
|
|
// begin
|
|
// //pc <= ma;
|
|
// ir <= 0;
|
|
// mb <= 0;
|
|
// end
|
|
//
|
|
// if (mb[8])
|
|
// mb <= 0;
|
|
//
|
|
// if (!mb[8] & !jmp)
|
|
// mb <= 0;
|
|
// end
|
|
end // case: F3
|
|
|
|
|
|
// DEFER
|
|
|
|
D0:
|
|
begin
|
|
$display("read ram [%o] -> %o", ram_addr, ram_data_in);
|
|
mb <= ram_data_in;
|
|
end
|
|
|
|
D1:
|
|
begin
|
|
// auto increment locations
|
|
if (is_index_reg)
|
|
mb <= mb + 1;
|
|
end
|
|
|
|
D2:
|
|
begin
|
|
// write ram
|
|
$display("write ram [%o] <- %o", ram_addr, ram_data_out);
|
|
end
|
|
|
|
D3:
|
|
begin
|
|
// if (jmp)
|
|
// begin
|
|
// //pc <= mb;
|
|
// ir <= 0;
|
|
// mb <= 0;
|
|
// end
|
|
//
|
|
// if (!jmp)
|
|
// begin
|
|
// mb <= 0;
|
|
// end
|
|
end
|
|
|
|
// EXECUTE
|
|
|
|
E0:
|
|
begin
|
|
$display("read ram [%o] -> %o", ram_addr, ram_data_in);
|
|
mb <= ram_data_in;
|
|
end
|
|
|
|
E1:
|
|
begin
|
|
if (i_and)
|
|
begin
|
|
end
|
|
|
|
if (isz)
|
|
mb <= mb + 1;
|
|
else
|
|
if (dca)
|
|
mb <= ac;
|
|
else
|
|
if (jms)
|
|
mb <= pc;
|
|
end
|
|
|
|
E2:
|
|
begin
|
|
// write ram
|
|
$display("write ram [%o] <- %o", ram_addr, ram_data_out);
|
|
end
|
|
|
|
E3:
|
|
begin
|
|
if (i_and)
|
|
ac <= ac & mb;
|
|
else
|
|
if (tad)
|
|
{l,ac} <= {l,ac} + {1'b0,mb};
|
|
else
|
|
if (dca)
|
|
ac <= 0;
|
|
|
|
// pc <- ma
|
|
// ir <= 0;
|
|
end
|
|
endcase // case(state)
|
|
|
|
endmodule
|
|
|