246 lines
5.6 KiB
Verilog
246 lines
5.6 KiB
Verilog
// this is verilator_pdp8.v
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// test bench top end for pdp8.v
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`define debug
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`define sim_time
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`define debug_s3ram
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`define use_sim_ram_model
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`define use_fake_uart
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`define debug_ram
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//`define debug_vcd
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//`define debug_log
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`include "../rtl/pdp8_tt.v"
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`include "../rtl/pdp8_rf.v"
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`include "../rtl/pdp8_kw.v"
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`include "../rtl/pdp8_io.v"
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`include "../rtl/pdp8_ram.v"
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`include "../rtl/pdp8.v"
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`ifdef use_fake_uart
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`include "../verif/fake_uart.v"
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`else
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`include "../rtl/uart.v"
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`endif
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`include "../rtl/brg.v"
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`include "../rtl/ide_disk.v"
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`include "../rtl/ide.v"
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`include "../rtl/ram_256x12.v"
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`include "../rtl/bootrom.v"
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`ifdef use_sim_ram_model
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`include "../rtl/ram_32kx12.v"
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`else
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`include "../verif/ram_s3board.v"
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`endif
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`timescale 1ns / 1ns
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module wrap_ide(clk, ide_data_in, ide_data_out,
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ide_dior, ide_diow, ide_cs, ide_da);
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input clk;
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input [15:0] ide_data_in;
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output [15:0] ide_data_out;
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input ide_dior;
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input ide_diow;
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input [1:0] ide_cs;
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input [2:0] ide_da;
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import "DPI-C" function void dpi_ide(input integer data_in,
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output integer data_out,
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input integer dior,
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input integer diow,
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input integer cs,
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input integer da);
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integer dbi, dbo;
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wire [31:0] dboo;
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assign dbi = {16'b0, ide_data_in};
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assign dboo = dbo;
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assign ide_data_out = dboo[15:0];
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always @(posedge clk)
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begin
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dpi_ide(dbi,
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dbo,
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{31'b0, ide_dior},
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{31'b0, ide_diow},
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{30'b0, ide_cs},
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{29'b0, ide_da});
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`ifdef debug_ide
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if (ide_dior == 0)
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begin
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$display("wrap_ide: read (%b %b) %x %x %x %x",
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ide_dior, ide_diow, dbo, dboo, dboo[15:0], ide_data_out);
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end
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if (ide_diow == 0)
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begin
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$display("wrap_ide: write (%b %b) %x %x %x",
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ide_dior, ide_diow, dbo, dboo, ide_data_out);
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end
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`endif
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end
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endmodule
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module test;
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reg sysclk/*verilator public_flat_rw @(clk)*/;
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wire clk;
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reg reset/*verilator public_flat_rw @(clk) */;
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reg [11:0] switches;
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wire [14:0] initial_pc;
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wire [11:0] pc_out;
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wire [11:0] ac_out;
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wire [11:0] ram_data_in;
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wire ram_rd;
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wire ram_wr;
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wire [11:0] ram_data_out;
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wire [14:0] ram_addr;
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wire [11:0] io_data_in;
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wire [11:0] io_data_out;
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wire [11:0] io_addr;
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wire io_data_avail;
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wire io_interrupt;
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wire io_skip;
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wire io_clear_ac;
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wire [5:0] io_select;
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wire iot;
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wire [3:0] state;
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wire [11:0] mb;
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wire ext_ram_read_req;
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wire ext_ram_write_req;
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wire [14:0] ext_ram_ma;
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wire [11:0] ext_ram_in;
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wire ext_ram_done;
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wire [11:0] ext_ram_out;
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wire [17:0] sram_a;
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wire sram_oe_n;
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wire sram_we_n;
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wire [15:0] sram1_io;
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wire sram1_ce_n;
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wire sram1_ub_n;
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wire sram1_lb_n;
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wire [15:0] sram2_io;
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wire sram2_ce_n;
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wire sram2_ub_n;
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wire sram2_lb_n;
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wire [15:0] ide_data_in;
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wire [15:0] ide_data_out;
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wire ide_dior, ide_diow;
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wire [1:0] ide_cs;
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wire [2:0] ide_da;
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reg rs232_in;
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wire rs232_out;
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// always @(posedge sysclk)
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// clk <= ~clk;
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assign clk = sysclk;
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pdp8 cpu(.clk(clk),
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.reset(reset),
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.initial_pc(initial_pc),
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.pc_out(pc_out),
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.ac_out(ac_out),
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.ram_addr(ram_addr),
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.ram_data_in(ram_data_out),
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.ram_data_out(ram_data_in),
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.ram_rd(ram_rd),
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.ram_wr(ram_wr),
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.io_select(io_select),
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.io_data_in(io_data_in),
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.io_data_out(io_data_out),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.switches(switches),
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.iot(iot),
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.state(state),
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.mb(mb),
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.ext_ram_read_req(ext_ram_read_req),
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.ext_ram_write_req(ext_ram_write_req),
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.ext_ram_done(ext_ram_done),
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.ext_ram_ma(ext_ram_ma),
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.ext_ram_in(ext_ram_out),
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.ext_ram_out(ext_ram_in));
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pdp8_io io(.clk(clk),
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.brgclk(clk),
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.reset(reset),
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.iot(iot),
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.state(state),
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.mb(mb),
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.io_data_in(io_data_out),
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.io_data_out(io_data_in),
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.io_select(io_select),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.io_ram_read_req(ext_ram_read_req),
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.io_ram_write_req(ext_ram_write_req),
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.io_ram_done(ext_ram_done),
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.io_ram_ma(ext_ram_ma),
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.io_ram_in(ext_ram_in),
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.io_ram_out(ext_ram_out),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da),
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.ide_data_in(ide_data_in),
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.ide_data_out(ide_data_out),
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.rs232_in(rs232_in),
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.rs232_out(rs232_out));
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pdp8_ram ram(.clk(clk),
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.reset(reset),
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.addr(ram_addr),
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.data_in(ram_data_in),
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.data_out(ram_data_out),
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.rd(ram_rd),
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.wr(ram_wr),
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.sram_a(sram_a),
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.sram_oe_n(sram_oe_n), .sram_we_n(sram_we_n),
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.sram1_io(sram1_io), .sram1_ce_n(sram1_ce_n),
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.sram1_ub_n(sram1_ub_n), .sram1_lb_n(sram1_lb_n),
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.sram2_io(sram2_io), .sram2_ce_n(sram2_ce_n),
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.sram2_ub_n(sram2_ub_n), .sram2_lb_n(sram2_lb_n));
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`ifndef use_sim_ram_model
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ram_s3board sram(.ram_a(sram_a),
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.ram_oe_n(sram_oe_n),
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.ram_we_n(sram_we_n),
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.ram1_io(sram1_io),
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.ram1_ce_n(sram1_ce_n),
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.ram1_ub_n(sram1_ub_n), .ram1_lb_n(sram1_lb_n),
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.ram2_io(sram2_io),
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.ram2_ce_n(sram2_ce_n),
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.ram2_ub_n(sram2_ub_n), .ram2_lb_n(sram2_lb_n));
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`endif
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wrap_ide wrap_ide(.clk(clk),
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.ide_data_in(ide_data_out),
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.ide_data_out(ide_data_in),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da));
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endmodule
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