github.com/lisper.cpus-pdp8
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brad 8974fd8ff1 synthesis
2010-10-26 11:20:13 +00:00
cpu
basic focal working
2009-05-10 23:51:20 +00:00
images
basic images for focal
2007-01-03 12:30:31 +00:00
pdf
2010-04-02 12:33:22 +00:00
pli
2010-06-07 20:36:11 +00:00
rom
2010-10-23 23:31:38 +00:00
rtl
synthesis
2010-10-26 11:20:13 +00:00
sim
boots tss/8
2010-04-02 12:32:05 +00:00
simhv36-1
tss8 testing
2010-06-02 15:21:04 +00:00
synth
2010-10-26 11:18:34 +00:00
tests
2010-06-05 17:09:48 +00:00
tss8
2010-04-02 12:36:00 +00:00
tss8.2
2010-04-11 10:33:53 +00:00
utils
2010-10-23 23:31:49 +00:00
v
initial
2007-01-02 16:24:48 +00:00
verif
verilator
2010-10-23 23:30:54 +00:00
verilator
2010-10-23 23:29:39 +00:00
xilinx
2010-04-24 10:35:11 +00:00
Description
FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
65 MiB
Languages
Verilog 46.9%
C 39%
Roff 4.1%
C++ 3.4%
Module Management System 1.7%
Other 4.7%