460 lines
9.5 KiB
Verilog
460 lines
9.5 KiB
Verilog
// PDP-8 i/o
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// Based on descriptions in "Computer Engineering"
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// Dev 2006 Brad Parker brad@heeltoe.com
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// Revamp 2009 Brad Parker brad@heeltoe.com
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/*
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iot's touched by focal
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6022 PCF
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6203 CDF CIF 00
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6402 PT08
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6412
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6422
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6432
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6442
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6452
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6462
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6472
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6764 DECTAPE
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6772
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*/
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/*
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RF08
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7750 word count
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7751 current address
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2048 words/track
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660x
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661x
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662x
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664x
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6601 DCMA Generates System Clear Pulse (SCLP) at IOP time 1.
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Clears disk memory eaddress(DMA), Parity Eror Flag (PEF),
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Data Request Late Flag (DRL), and sets logic to
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initial state for read or write. Does not clear
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interrupt enable or extended address register.
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6603 DMAR Generate SCLP at IOP time 1. At IOP time 2, loads DMA
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with AC and clears AC. Read continues for number words
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in WC register (7750)
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6605 DMAW Generate SCLP at IOP time 1. At IOP time 4, loads DMA
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with AC and clears AC. When the disk word address is located
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writing begins, disk address is incremented for each
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word written
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6611 DCIM clears disk interrupt enable and the extended address
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registers at IOP time 1.
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6612 DSAC At IOP time 2, skip if Address Confirmed (ADC) set indicating
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the DMA address and disk word address compare. AC is then
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cleared.
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6615 DIML At IOP time 1, clear interrupt enable and memory address
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extension registers. At IOP time 4, load interrupt enable
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and memory address extension register with AC, clear AC.
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6616 DIMA Clear ??? at IOP time 2. At IOP time 4 load AC with status
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register.
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6621 DFSE skip on error skip if DRL, PER WLS or NXD set
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6622 ??? skip if data completion DCF set
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6623 DISK skip on error or data completion; enabled at IOP 2
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6626 DMAC clear ac at IOP time 2 load AC from DMA at IOP time 4.
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6641 DCXA Clears EMA
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6643 DXAL Clears and loads EMA from AC. At IOP time 1, clear EMA, at
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IOP time 2, load EMA with AC. Clear AC
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6645 DXAC Clears AC and loads EMA into AC
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6646 DMMT Maintenance
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uses 3 cycle data break
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ac 7:0, ac 11:0 => 20 bit {EMA,DMA}
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20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 }
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status
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*/
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// EIE = WLS | DRL | NXD | PER
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/*
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3 cycle data break
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1. An address is read from the device to indicate the location of the
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word count register. This location specifies the number of words in
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the block yet to be transferred. The address is always the same for a
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given device.
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2. The content of the specficified word count register is read from
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memory and incremented by one. To transfer a block of n words, the
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word count is set to -n during the programmed initialization of the
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device. When this register is incremented to 0, a pulse is sent to
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the device to terminate the transfer.
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3. The location after the word count register contains the current
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address register for the device transfer. The content of thise
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register is set to 1 less than the location to be affected by the next
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transfer. To transfer a block beginning at location A, the register is
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originally set to A-1.
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4. The content of the current address register is incremented by 1
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and then used to specify the location affected by the transfer.
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After the transfer of information has been accomplished through the
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data break factility, input data (or new output data) is processed,
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usually through the program interrupt facility. An interrupt is
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requested when the data transfer is completed and the service routine
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will process the information.
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xxx:
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if (databreak_req)
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begin
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databreak_done <= 0;
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next_state <= DB0;
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end
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// read word count
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DB0:
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ma <= wc-address;
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next_state <= DB1;
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// write word count - 1
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DB1:
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mb <= memory_bus - 1;
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ram_we_n <= 0;
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if (mb == 0) databreak_done <= 1;
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next_state <= DB2;
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// finish write
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DB2:
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ram_we_n <= 1;
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next_state <= DB3;
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// read current address
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DB3:
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ma <= ma | 1;
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next_state <= DB4;
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// write current address - 1
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DB4:
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mb <= memory_bus + 1;
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ram_we_n <= 0;
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next_state <= DB5;
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// finish write
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DB5:
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ram_we_n <= 1;
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next_state <= DB6;
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// set up read/write address
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DB6:
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ma <= mb;
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next_state <= DB7;
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// do read or start write
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DB7:
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if (databreak_write)
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begin
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data <= memory_bus;
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next_state <= F0;
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end
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else
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begin
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mb <= data;
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ram_we_n <= 0;
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next_state <= DB8;
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end
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// finish write
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DB8:
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ram_we_n < = 1;
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next_state <= F0;
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*/
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module pdp8_io(clk, reset, iot, state, mb,
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io_data_in, io_data_out, io_select,
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io_data_avail, io_interrupt, io_skip);
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input clk, reset, iot;
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input [11:0] io_data_in;
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input [11:0] mb;
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input [3:0] state;
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input [5:0] io_select;
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output reg [11:0] io_data_out;
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output reg io_data_avail;
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output reg io_interrupt;
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output reg io_skip;
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reg rx_int, tx_int;
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reg [12:0] rx_data, tx_data;
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reg tx_delaying;
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integer tx_delay;
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parameter F0 = 4'b0000;
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parameter F1 = 4'b0001;
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parameter F2 = 4'b0010;
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parameter F3 = 4'b0011;
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parameter D0 = 4'b0100;
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parameter D1 = 4'b0101;
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parameter D2 = 4'b0110;
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parameter D3 = 4'b0111;
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parameter E0 = 4'b1000;
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parameter E1 = 4'b1001;
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parameter E2 = 4'b1010;
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parameter E3 = 4'b1011;
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parameter PCA_bit = 12'o4000; // photocell status
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parameter DRE_bit = 12'o2000; // data req enable
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parameter WLS_bit = 12'o1000; // write lock status
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parameter EIE_bit = 12'o0400; // error int enable
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parameter PIE_bit = 12'o0200; // photocell int enb
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parameter CIE_bit = 12'o0100; // done int enable
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parameter MEX_bit = 12'o0070; // memory extension
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parameter DRL_bit = 12'o0004; // data late error
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parameter NXD_bit = 12'o0002; // non-existent disk
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parameter PER_bit = 12'o0001; // parity error
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wire ADC;
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wire DCF;
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reg [11:0] DMA;
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reg [7:0] EMA;
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reg PEF;
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reg rf08_rw;
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reg rf08_start_io;
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reg CIE, DRE, DRL, EIE, MEX, NXD, PCA, PER, PIE, WLS;
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assign DCF = 1'b0;
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assign ADC = DMA == /*DWA??*/0;
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// combinatorial
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always @(state or
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rx_int or tx_int or
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ADC or DRL or PER or WLS or NXD or DCF)
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begin
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// sampled during f1
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io_skip = 0;
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io_data_out = io_data_in;
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io_data_avail = 1;
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if (state == F1 && iot)
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case (io_select)
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6'o03:
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begin
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if (mb[0])
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io_skip = rx_int;
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if (mb[2])
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io_data_out = rx_data;
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end
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6'o04:
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if (mb[0])
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begin
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io_skip = tx_int;
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$display("xxx io_skip %b", tx_int);
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end
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6'o60:
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case (mb[2:0])
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3'o03: // DMAR
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io_data_out = 0;
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3'o03: // DMAW
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io_data_out = 0;
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endcase
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6'o61:
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case (mb[2:0])
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3'o2: // DSAC
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if (ADC)
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begin
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io_skip = 1;
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io_data_out = 0;
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end
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3'o6: // DIMA
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io_data_out = { PCA, DRE,WLS,EIE, PIE,CIE,MEX, DRL,NXD,PER };
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3'o5: // DIML
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io_data_out = 0;
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endcase
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6'o62:
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case (mb[2:0])
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3'o1: // DFSE
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if (DRL | PER | WLS | NXD)
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io_skip = 1;
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3'o2: // ???
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if (DCF)
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io_skip = 1;
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3'o3: // DISK
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if (DRL | PER | WLS | NXD | DCF)
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io_skip = 1;
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3'o6: // DMAC
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io_data_out = DMA;
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endcase
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6'o64:
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case (mb[2:0])
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3: // DXAL
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io_data_out = 0;
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5: // DXAC
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io_data_out = EMA;
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endcase
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endcase // case(io_select)
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end
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//
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// registers
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//
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always @(posedge clk)
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if (reset)
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begin
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end
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else
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case (state)
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F0:
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begin
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// sampled during f1
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io_data_avail <= 0;
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if (iot)
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case (io_select)
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6'o60: // DCMA
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if (mb[2:0] == 3'b001)
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begin
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DMA <= 0;
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PEF <= 0;
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DRL <= 0;
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end
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6'o61:
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case (mb[2:0])
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3'o1: // DCIM
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begin
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CIE <= 0;
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EMA <= 0;
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end
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3'o2: // DSAC
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begin
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end
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3'o5: // DIML
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begin
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CIE <= io_data_in[8];
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EMA <= io_data_in[7:0];
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end
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endcase // case(mb[2:0])
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endcase
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end
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F1:
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if (iot)
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begin
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$display("iot2 %t, state %b, mb %o, io_select %o",
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$time, state, mb, io_select);
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case (io_select)
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6'o03:
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begin
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if (mb[1])
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rx_int <= 0;
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end
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6'o04:
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begin
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if (mb[0])
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begin
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end
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if (mb[1])
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begin
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tx_int <= 0;
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$display("xxx reset tx_int");
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end
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if (mb[2])
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begin
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tx_data <= io_data_in;
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$display("xxx tx_data %o", io_data_in);
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tx_int <= 1;
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tx_delaying <= 1;
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tx_delay <= 98;
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$display("xxx set tx_int");
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end
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end // case: 6'o04
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6'o60:
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case (mb[2:0])
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3'o03: // DMAR
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begin
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// clear ac
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DMA <= io_data_in;
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rf08_start_io <= 1;
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rf08_rw <= 0;
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end
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3'o03: // DMAW
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begin
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// clear ac
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DMA <= io_data_in;
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rf08_start_io <= 1;
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rf08_rw <= 1;
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end
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endcase // case(mb[2:0])
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6'o64:
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case (mb[2:0])
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1: // DCXA
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EMA <= 0;
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3: // DXAL
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// clear ac
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EMA <= io_data_in;
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endcase
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endcase
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end // if (iot)
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F2:
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begin
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if (io_interrupt)
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$display("iot2 %t, reset io_interrupt", $time);
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// sampled during f0
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io_interrupt <= 0;
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end
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F3:
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begin
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if (tx_delaying)
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begin
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tx_delay <= tx_delay - 1;
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//$display("xxx delay %d", tx_delay);
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if (tx_delay == 0)
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begin
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$display("iot2 %t, xxx set io_interrupt", $time);
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tx_delaying <= 0;
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io_interrupt <= 1;
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end
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end
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end
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endcase // case(state)
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endmodule
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