406 lines
8.3 KiB
Verilog
406 lines
8.3 KiB
Verilog
// test_pdp8.v
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// test bench top end for pdp8.v
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//
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`ifdef __ICARUS__
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`define sim
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`endif
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`ifdef __CVER__
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`define sim
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`endif
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`ifdef sim
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`define debug
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`define sim_time
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`define debug_s3ram
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//`define use_sim_ram_model
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//`define debug_vcd
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//`define debug_log
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`endif
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`ifndef use_rf_pli
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`define use_sim_ram_model 1
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`endif
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`include "../rtl/pdp8_tt.v"
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`include "../rtl/pdp8_rf.v"
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`include "../rtl/pdp8_kw.v"
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`include "../rtl/pdp8_io.v"
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`include "../rtl/pdp8_ram.v"
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`include "../rtl/pdp8.v"
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`ifdef use_fake_uart
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`include "../verif/fake_uart.v"
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`else
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`include "../rtl/uart.v"
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`endif
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`include "../rtl/brg.v"
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`include "../rtl/ide_disk.v"
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`include "../rtl/ide.v"
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`include "../rtl/ram_256x12.v"
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`include "../rtl/bootrom.v"
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`ifdef use_sim_ram_model
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`include "../rtl/ram_32kx12.v"
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`else
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`include "../verif/ram_s3board.v"
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`endif
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`timescale 1ns / 1ns
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module test;
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reg clk, reset;
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reg [11:0] switches;
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wire [14:0] initial_pc;
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wire [11:0] pc_out;
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wire [11:0] ac_out;
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wire [11:0] ram_data_in;
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wire ram_rd;
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wire ram_wr;
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wire [11:0] ram_data_out;
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wire [14:0] ram_addr;
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wire [11:0] io_data_in;
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wire [11:0] io_data_out;
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wire [11:0] io_addr;
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wire io_data_avail;
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wire io_interrupt;
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wire io_skip;
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wire [5:0] io_select;
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wire iot;
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wire [3:0] state;
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wire [11:0] mb;
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wire ext_ram_read_req;
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wire ext_ram_write_req;
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wire [14:0] ext_ram_ma;
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wire [11:0] ext_ram_in;
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wire ext_ram_done;
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wire [11:0] ext_ram_out;
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wire [17:0] sram_a;
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wire sram_oe_n;
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wire sram_we_n;
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wire [15:0] sram1_io;
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wire sram1_ce_n;
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wire sram1_ub_n;
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wire sram1_lb_n;
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wire [15:0] sram2_io;
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wire sram2_ce_n;
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wire sram2_ub_n;
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wire sram2_lb_n;
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wire [15:0] ide_data_bus;
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wire ide_dior, ide_diow;
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wire [1:0] ide_cs;
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wire [2:0] ide_da;
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reg rs232_in;
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wire rs232_out;
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pdp8 cpu(.clk(clk),
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.reset(reset),
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.initial_pc(initial_pc),
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.pc_out(pc_out),
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.ac_out(ac_out),
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.ram_addr(ram_addr),
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.ram_data_in(ram_data_out),
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.ram_data_out(ram_data_in),
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.ram_rd(ram_rd),
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.ram_wr(ram_wr),
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.io_select(io_select),
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.io_data_in(io_data_in),
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.io_data_out(io_data_out),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.switches(switches),
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.iot(iot),
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.state(state),
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.mb(mb),
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.ext_ram_read_req(ext_ram_read_req),
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.ext_ram_write_req(ext_ram_write_req),
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.ext_ram_done(ext_ram_done),
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.ext_ram_ma(ext_ram_ma),
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.ext_ram_in(ext_ram_out),
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.ext_ram_out(ext_ram_in));
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pdp8_io io(.clk(clk),
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.brgclk(clk),
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.reset(reset),
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.iot(iot),
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.state(state),
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.mb(mb),
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.io_data_in(io_data_out),
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.io_data_out(io_data_in),
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.io_select(io_select),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.io_ram_read_req(ext_ram_read_req),
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.io_ram_write_req(ext_ram_write_req),
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.io_ram_done(ext_ram_done),
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.io_ram_ma(ext_ram_ma),
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.io_ram_in(ext_ram_in),
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.io_ram_out(ext_ram_out),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da),
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.ide_data_bus(ide_data_bus),
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.rs232_in(rs232_in),
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.rs232_out(rs232_out));
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`ifndef use_rf_pli
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pdp8_ram ram(.clk(clk),
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.reset(reset),
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.addr(ram_addr),
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.data_in(ram_data_in),
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.data_out(ram_data_out),
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.rd(ram_rd),
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.wr(ram_wr),
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.sram_a(sram_a),
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.sram_oe_n(sram_oe_n), .sram_we_n(sram_we_n),
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.sram1_io(sram1_io), .sram1_ce_n(sram1_ce_n),
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.sram1_ub_n(sram1_ub_n), .sram1_lb_n(sram1_lb_n),
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.sram2_io(sram2_io), .sram2_ce_n(sram2_ce_n),
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.sram2_ub_n(sram2_ub_n), .sram2_lb_n(sram2_lb_n));
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`endif
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`ifndef use_sim_ram_model
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ram_s3board sram(.ram_a(sram_a),
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.ram_oe_n(sram_oe_n),
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.ram_we_n(sram_we_n),
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.ram1_io(sram1_io),
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.ram1_ce_n(sram1_ce_n),
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.ram1_ub_n(sram1_ub_n), .ram1_lb_n(sram1_lb_n),
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.ram2_io(sram2_io),
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.ram2_ce_n(sram2_ce_n),
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.ram2_ub_n(sram2_ub_n), .ram2_lb_n(sram2_lb_n));
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`endif
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reg [14:0] starting_pc;
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reg [1023:0] arg;
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integer n;
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assign initial_pc = starting_pc;
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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`ifdef debug_log
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`else
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`ifdef __CVER__
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$nolog;
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`endif
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`endif
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`ifdef debug_vcd
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$dumpfile("test_pdp8.vcd");
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$dumpvars(0, test);
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`endif
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end
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initial
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begin
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clk = 0;
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reset = 0;
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switches = 0;
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rs232_in = 1;
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max_cycles = 0;
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max_cycles = 100;
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starting_pc = 15'o00200;
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show_pc = 0;
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show_state = 0;
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if (0) show_pc = 1;
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if (0) show_state = 1;
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`ifdef __ICARUS__
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n = $value$plusargs("showpc=%d", arg);
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if (n > 0)
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show_pc = 1;
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n = $value$plusargs("showstate=%d", arg);
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if (n > 0)
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show_state = 1;
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n = $value$plusargs("pc=%o", arg);
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if (n > 0)
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begin
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starting_pc = arg;
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$display("arg pc %o", starting_pc);
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end
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n = $value$plusargs("switches=%o", arg);
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if (n > 0)
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begin
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switches = arg;
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$display("arg swiches %o", switches);
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end
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n = $value$plusargs("cycles=%d", arg);
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if (n > 0)
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begin
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max_cycles = arg;
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$display("arg cycles %d", max_cycles);
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end
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`endif
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`ifdef __CVER__
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n = $scan$plusargs("showpc", arg);
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if (n > 0)
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show_pc = 1;
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n = $scan$plusargs("showstate", arg);
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if (n > 0)
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show_state = 1;
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n = $scan$plusargs("pc=", arg);
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if (n > 0)
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begin
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n = $sscanf(arg, "%o", starting_pc);
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$display("arg %s pc %o", arg, starting_pc);
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end
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n = $scan$plusargs("switches=", arg);
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if (n > 0)
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begin
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n = $sscanf(arg, "%o", switches);
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$display("arg %s switches %o", arg, switches);
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end
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n = $scan$plusargs("cycles=", arg);
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if (n > 0)
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begin
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n = $sscanf(arg, "%d", max_cycles);
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$display("arg %s cycles %d", arg, max_cycles);
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end
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`endif
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#1 begin
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reset = 1;
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end
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#60 begin
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reset = 0;
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end
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end
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always
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begin
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#10 clk = 0;
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#10 clk = 1;
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end
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//----
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integer cycle;
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integer max_cycles;
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integer sample;
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integer show_pc;
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integer show_one_pc;
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integer show_state;
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initial
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begin
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cycle = 0;
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sample = 0;
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end
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always @(posedge cpu.clk)
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begin
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if (cpu.state == 4'b0000)
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begin
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sample = sample + 1;
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if (sample >= 5000/*50000*/)
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begin
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sample = 0;
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show_one_pc = 1;
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end
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if (show_pc)
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show_one_pc = 1;
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cycle = cycle + 1;
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if (max_cycles > 0 && cycle >= max_cycles)
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$finish;
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if (show_one_pc)
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#1 $display("pc %o ir %o l%b ac %o ion %o (IF%o DF%o UF%o SF%o IB%o UB%o)",
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cpu.pc, cpu.mb,
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cpu.l, cpu.ac, cpu.interrupt_enable,
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cpu.IF, cpu.DF, cpu.UF, cpu.SF, cpu.IB, cpu.UB);
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`ifdef xxx
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if (show_one_pc)
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#1 $pli_disassemble(cpu.pc, cpu.mb);
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`endif
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show_one_pc = 0;
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end
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if (cpu.state == 4'b1100)
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begin
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$display("HALTED @ %o", cpu.pc);
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$display("cpu.io_interrupt %b io.io_interrupt %b tt.io_interrupt %b",
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cpu.io_interrupt,
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io.io_interrupt, io.tt.io_interrupt);
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$display("pc %o ir %o", cpu.pc, cpu.mb);
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$finish;
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end
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if (show_state)
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begin
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#2 case (state)
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4'b0000: $display("F0");
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4'b0001: $display("F1");
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4'b0010: $display("F2");
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4'b0011: $display("F3");
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4'b0100: $display("D0");
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4'b0101: $display("D1");
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4'b0110: $display("D2");
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4'b0111: $display("D3");
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4'b1000: $display("E0");
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4'b1001: $display("E1");
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4'b1010: $display("E2 %b%b%b%b%b r%bw%b",
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cpu.i_and, cpu.tad, cpu.isz,
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cpu.dca, cpu.jms,
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cpu.ram_rd, cpu.ram_wr);
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4'b1011: $display("E3");
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endcase // case(state)
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end
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end
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`ifndef use_rf_pli
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always @(posedge clk)
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begin
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$pli_ide(ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
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end
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`endif
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`ifdef use_rf_pli
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always @(reset /*or ram_addr or ram_data_in*/ or ram_rd or ram_wr)
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begin
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$pli_ram(reset, ram_addr, ram_data_in, ram_data_out, ram_rd, ram_wr);
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end
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`endif
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endmodule
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