128 lines
2.4 KiB
Verilog
128 lines
2.4 KiB
Verilog
// run.v
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// testing top end for pdp8.v
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//
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`include "pdp8.v"
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`include "pdp8_io.v"
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`include "pdp8_ram.v"
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`timescale 1ns / 1ns
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module test;
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reg clk, reset;
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reg [11:0] switches;
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wire [11:0] ram_data_in;
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wire ram_rd;
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wire ram_wr;
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wire [11:0] ram_data_out;
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wire [14:0] ram_addr;
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wire [11:0] io_data_in;
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wire [11:0] io_data_out;
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wire [11:0] io_addr;
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wire io_data_avail;
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wire io_interrupt;
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wire io_skip;
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wire [5:0] io_select;
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wire iot;
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wire [3:0] state;
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wire [11:0] mb;
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pdp8 cpu(.clk(clk),
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.reset(reset),
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.ram_addr(ram_addr),
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.ram_data_in(ram_data_out),
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.ram_data_out(ram_data_in),
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.ram_rd(ram_rd),
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.ram_wr(ram_wr),
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.state(state),
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.io_select(io_select),
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.io_data_in(io_data_in),
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.io_data_out(io_data_out),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.iot(iot),
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.mb(mb),
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.switches(switches));
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pdp8_io io(.clk(clk),
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.reset(reset),
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.iot(iot),
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.state(state),
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.mb(mb),
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.io_data_in(io_data_out),
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.io_data_out(io_data_in),
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.io_select(io_select),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip));
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pdp8_ram ram(.clk(clk),
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.reset(reset),
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.addr(ram_addr),
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.data_in(ram_data_in),
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.data_out(ram_data_out),
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.rd(ram_rd),
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.wr(ram_wr));
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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$dumpfile("pdp8.vcd");
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$dumpvars(0, test.cpu);
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end
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initial
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begin
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clk = 0;
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reset = 0;
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#1 begin
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reset = 1;
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end
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#50 begin
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reset = 0;
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end
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#3000000 $finish;
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end
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always
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begin
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#10 clk = 0;
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#10 clk = 1;
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end
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//----
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integer cycle;
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initial
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cycle = 0;
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always @(posedge cpu.clk)
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if (cpu.state == 4'b0000)
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begin
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cycle = cycle + 1;
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// #1 $display("#%d, r%b s%d, pc %o ir%o ma %o mb %o j%b l%b ac %o, i%b/%b",
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// cycle, cpu.run, cpu.state, cpu.pc,
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// cpu.ir, cpu.ma, cpu.mb, cpu.jmp, cpu.l, cpu.ac,
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// cpu.interrupt_enable, cpu.interrupt);
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//#1 $display(" io_data_in %o, io_data_out %o",
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//io_data_in, io_data_out);
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#1 $display("pc %o ir %o l %b ac %o ion %o",
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cpu.pc, cpu.mb, cpu.l, cpu.ac, cpu.interrupt_enable);
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if (state == 4'b1100)
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$finish;
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end
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endmodule
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