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lisper.cpus-pdp8/xilinx/vga/fpga_summary.html
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD COLSPAN='4'><B>VGA Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>vga.ise</TD>
<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>fpga</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD ALIGN=LEFT>No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2s200-5fg256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>29 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 8.2i</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
<TD>Mon Jan 1 22:23:05 2007</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>VGA Partition Summary</B></TD></TR>
<TR><TD COLSPAN='4'>No partition information was found.</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='5'><B>Device Utilization Summary</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number Slice Registers</B></TD>
<TD ALIGN=RIGHT>174</TD>
<TD ALIGN=RIGHT>4,704</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>173</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>688</TD>
<TD ALIGN=RIGHT>4,704</TD>
<TD ALIGN=RIGHT>14%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of occupied Slices</TD>
<TD ALIGN=RIGHT>402</TD>
<TD ALIGN=RIGHT>2,352</TD>
<TD ALIGN=RIGHT>17%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>402</TD>
<TD ALIGN=RIGHT>402</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>402</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>716</TD>
<TD ALIGN=RIGHT>4,704</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>688</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD>
<TD ALIGN=RIGHT>28</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of bonded <A HREF_DISABLED='fpga_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>22</TD>
<TD ALIGN=RIGHT>176</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Block RAMs</TD>
<TD ALIGN=RIGHT>7</TD>
<TD ALIGN=RIGHT>14</TD>
<TD ALIGN=RIGHT>50%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of GCLKs</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>75%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of GCLKIOBs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>25%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD>
<TD ALIGN=RIGHT>120,964</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Additional JTAG gate count for IOBs</TD>
<TD ALIGN=RIGHT>1,104</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Performance Summary</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD><A HREF_DISABLED='fpga.pad?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD>
<TD><A HREF_DISABLED='fpga.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD><A HREF_DISABLED='fpga.par?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD><A HREF_DISABLED='fpga.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Jan 1 22:21:50 2007</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>21 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>6 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Jan 1 22:22:03 2007</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/ngdbuild.xmsgs'>7 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Jan 1 22:22:16 2007</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>7 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Jan 1 22:22:44 2007</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Mon Jan 1 22:22:52 2007</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='fpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon Jan 1 22:23:05 2007</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>1 Warning</A></TD><TD ALIGN=LEFT>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD>Xplorer Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
</TABLE>
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