968 lines
45 KiB
Plaintext
968 lines
45 KiB
Plaintext
Release 8.2i - xst I.31
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Reading design: fpga.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "fpga.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "fpga"
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Output Format : NGC
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Target Device : xc2s200-5-fg256
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---- Source Options
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Top Module Name : fpga
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : lut
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100
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Add Generic Clock Buffer(BUFG) : 4
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : fpga.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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tristate2logic : Yes
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../v/vga.v" in library work
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Compiling verilog include file "../../v/vgacore.v"
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Compiling verilog include file "../../v/crt.v"
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Module <vgacore> compiled
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Compiling verilog include file "../../v/video_ram.v"
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Module <crt> compiled
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Compiling verilog include file "../../v/char_rom.v"
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Module <video_ram> compiled
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Compiling verilog include file "../../v/ps2.v"
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Module <char_rom> compiled
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Compiling verilog include file "../../v/scancode.v"
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Compiling verilog include file "../../v/scancode_rom.v"
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Module <ps2> compiled
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Module <scancode_rom> compiled
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Module <scancode_convert> compiled
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Compiling verilog file "../../v/fpga.v" in library work
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Module <vga> compiled
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Module <fpga> compiled
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No errors in compilation
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Analysis of file <"fpga.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <fpga> in library <work>.
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Analyzing hierarchy for module <vga> in library <work>.
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Analyzing hierarchy for module <char_rom> in library <work>.
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Analyzing hierarchy for module <video_ram> in library <work>.
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Analyzing hierarchy for module <vgacore> in library <work> with parameters.
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V_SIZE = "00000000000000000000000111100000"
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H_SIZE = "00000000000000000000001010000000"
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Analyzing hierarchy for module <ps2> in library <work> with parameters.
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PS2_FREQ = "00000000000000000000000000001010"
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KEY_RELEASE = "11110000"
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FREQ = "00000000000000000110000110101000"
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TIMEOUT = "00000000000000000000100111000100"
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Analyzing hierarchy for module <scancode_convert> in library <work> with parameters.
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C_INIT = "000"
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C_HOLD = "101"
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C_RELEASE = "100"
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C_KEYRELEASE = "011"
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C_KEYPRESS = "010"
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C_IDLE = "001"
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Analyzing hierarchy for module <crt> in library <work> with parameters.
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T_RESET = "0000"
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T_WRITE = "0101"
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T_SCROLL = "1000"
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T_CLEARALL = "0001"
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LINES = "011001"
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COLS = "1010000"
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T_CLEARLAST_DONE = "1100"
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T_CLEARLAST = "1001"
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T_CLEARALL_NEXT = "0010"
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T_IDLE = "0011"
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T_CLEARLAST_WRITE = "1010"
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T_CLEARLAST_NEXT = "1011"
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T_PREWRITE = "0100"
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T_POSTWRITE = "0110"
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T_NEWLINE = "0111"
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Analyzing hierarchy for module <scancode_rom> in library <work>.
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <fpga>.
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Module <fpga> is correct for synthesis.
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Analyzing module <vga> in library <work>.
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Module <vga> is correct for synthesis.
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Analyzing module <char_rom> in library <work>.
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Module <char_rom> is correct for synthesis.
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Analyzing module <video_ram> in library <work>.
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Module <video_ram> is correct for synthesis.
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Analyzing module <vgacore> in library <work>.
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H_SIZE = 32'sb00000000000000000000001010000000
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V_SIZE = 32'sb00000000000000000000000111100000
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Module <vgacore> is correct for synthesis.
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Analyzing module <ps2> in library <work>.
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FREQ = 32'sb00000000000000000110000110101000
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PS2_FREQ = 32'sb00000000000000000000000000001010
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TIMEOUT = 32'sb00000000000000000000100111000100
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KEY_RELEASE = 8'b11110000
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Module <ps2> is correct for synthesis.
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Analyzing module <scancode_convert> in library <work>.
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C_INIT = 3'b000
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C_IDLE = 3'b001
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C_KEYPRESS = 3'b010
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C_KEYRELEASE = 3'b011
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C_RELEASE = 3'b100
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C_HOLD = 3'b101
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"../../v/scancode.v" line 151: Found Full Case directive in module <scancode_convert>.
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Module <scancode_convert> is correct for synthesis.
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Analyzing module <scancode_rom> in library <work>.
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Module <scancode_rom> is correct for synthesis.
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Analyzing module <crt> in library <work>.
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T_RESET = 4'b0000
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T_CLEARALL = 4'b0001
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T_CLEARALL_NEXT = 4'b0010
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T_IDLE = 4'b0011
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T_PREWRITE = 4'b0100
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T_WRITE = 4'b0101
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T_POSTWRITE = 4'b0110
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T_NEWLINE = 4'b0111
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T_SCROLL = 4'b1000
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T_CLEARLAST = 4'b1001
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T_CLEARLAST_WRITE = 4'b1010
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T_CLEARLAST_NEXT = 4'b1011
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T_CLEARLAST_DONE = 4'b1100
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COLS = 7'b1010000
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LINES = 6'b011001
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"../../v/crt.v" line 220: Found Full Case directive in module <crt>.
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Module <crt> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <char_rom>.
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Related source file is "../../v/char_rom.v".
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Found 1024x8-bit ROM for signal <data>.
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Summary:
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inferred 1 ROM(s).
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Unit <char_rom> synthesized.
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Synthesizing Unit <video_ram>.
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Related source file is "../../v/video_ram.v".
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Found 2049x8-bit dual-port block RAM for signal <ram>.
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-----------------------------------------------------------------------
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| ram_style | Auto | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 2049-word x 8-bit | |
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| mode | write-first | |
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| clkA | connected to signal <clk_w> | rise |
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| weA | connected to signal <we_n> | low |
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| addrA | connected to signal <ram_addr_w> | |
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| diA | connected to signal <data_in> | |
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-----------------------------------------------------------------------
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| Port B |
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| aspect ratio | 2049-word x 8-bit | |
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| clkB | connected to signal <clk_r> | rise |
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| addrB | connected to signal <addr> | |
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| doB | connected to signal <data_out> | |
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-----------------------------------------------------------------------
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Found 12-bit register for signal <ram_addr_w>.
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Summary:
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inferred 1 RAM(s).
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inferred 12 D-type flip-flop(s).
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Unit <video_ram> synthesized.
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Synthesizing Unit <vgacore>.
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Related source file is "../../v/vgacore.v".
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Found 1-bit register for signal <vsync>.
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Found 1-bit register for signal <hblank>.
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Found 1-bit register for signal <enable>.
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Found 1-bit register for signal <hsync>.
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Found 10-bit comparator greatequal for signal <$cmp_ge0000> created at line 131.
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Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 145.
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Found 11-bit comparator greatequal for signal <$cmp_ge0002> created at line 109.
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Found 10-bit comparator greatequal for signal <$cmp_ge0003> created at line 123.
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Found 11-bit comparator less for signal <$cmp_lt0000> created at line 137.
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Found 10-bit comparator less for signal <$cmp_lt0001> created at line 131.
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Found 11-bit comparator less for signal <$cmp_lt0002> created at line 79.
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Found 10-bit comparator less for signal <$cmp_lt0003> created at line 95.
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Found 11-bit comparator less for signal <$cmp_lt0004> created at line 109.
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Found 10-bit comparator less for signal <$cmp_lt0005> created at line 123.
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Found 11-bit up counter for signal <hcnt>.
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Found 10-bit up counter for signal <vcnt>.
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Summary:
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inferred 2 Counter(s).
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inferred 4 D-type flip-flop(s).
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inferred 10 Comparator(s).
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Unit <vgacore> synthesized.
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Synthesizing Unit <ps2>.
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Related source file is "../../v/ps2.v".
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WARNING:Xst:646 - Signal <keyrel_r> is assigned but never used.
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WARNING:Xst:653 - Signal <keyrel_x> is used but never assigned. Tied to value 0.
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Found 14-bit adder for signal <$addsub0000> created at line 93.
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Found 4-bit adder for signal <$addsub0001> created at line 103.
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Found 4-bit register for signal <bitcnt_r>.
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Found 4-bit 4-to-1 multiplexer for signal <bitcnt_x>.
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Found 1-bit register for signal <error_r>.
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Found 5-bit register for signal <ps2_clk_r>.
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Found 1-bit register for signal <rdy_r>.
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Found 10-bit register for signal <sc_r>.
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Found 14-bit register for signal <timer_r>.
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Summary:
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inferred 35 D-type flip-flop(s).
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inferred 2 Adder/Subtractor(s).
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inferred 4 Multiplexer(s).
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Unit <ps2> synthesized.
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Synthesizing Unit <crt>.
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Related source file is "../../v/crt.v".
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WARNING:Xst:646 - Signal <printable> is assigned but never used.
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WARNING:Xst:646 - Signal <clr_offset> is assigned but never used.
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Found finite state machine <FSM_0> for signal <state>.
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-----------------------------------------------------------------------
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| States | 13 |
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| Transitions | 24 |
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| Inputs | 8 |
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| Outputs | 13 |
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| Clock | clock (rising_edge) |
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| Reset | reset_n (negative) |
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| Reset type | asynchronous |
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| Reset State | 0000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 4x1-bit ROM for signal <set_newline>.
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WARNING:Xst:737 - Found 1-bit latch for signal <ram_wclk>.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 1-bit register for signal <done>.
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Found 8-bit register for signal <ram_data>.
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Found 12-bit adder for signal <ram_addr>.
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Found 12-bit adder for signal <$addsub0000>.
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Found 12-bit adder for signal <$addsub0001> created at line 102.
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Found 8-bit adder for signal <$addsub0002>.
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Found 7-bit up counter for signal <cursor_h>.
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Found 6-bit up counter for signal <cursor_v>.
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Found 1-bit register for signal <newline>.
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Found 12-bit register for signal <offset>.
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Found 3-bit up counter for signal <write_delay>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 ROM(s).
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inferred 3 Counter(s).
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inferred 22 D-type flip-flop(s).
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inferred 4 Adder/Subtractor(s).
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Unit <crt> synthesized.
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Synthesizing Unit <scancode_rom>.
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Related source file is "../../v/scancode_rom.v".
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Unit <scancode_rom> synthesized.
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Synthesizing Unit <scancode_convert>.
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Related source file is "../../v/scancode.v".
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Found finite state machine <FSM_1> for signal <state>.
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-----------------------------------------------------------------------
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| States | 6 |
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| Transitions | 14 |
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| Inputs | 8 |
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| Outputs | 5 |
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| Clock | clock (rising_edge) |
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| Reset | reset_n (negative) |
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| Reset type | asynchronous |
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| Reset State | 000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 4x1-bit ROM for signal <key_up_clear>.
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Found 1-bit register for signal <strobe_out>.
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Found 8-bit register for signal <ascii>.
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Found 1-bit register for signal <key_up>.
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Found 8-bit subtractor for signal <$addsub0000> created at line 135.
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Found 1-bit register for signal <capslock>.
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Found 1-bit register for signal <ctrl>.
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Found 3-bit up counter for signal <hold_count>.
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Found 1-bit register for signal <release_prefix>.
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Found 7-bit register for signal <sc>.
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Found 1-bit register for signal <shift>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 ROM(s).
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inferred 1 Counter(s).
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inferred 21 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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Unit <scancode_convert> synthesized.
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Synthesizing Unit <vga>.
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Related source file is "../../v/vga.v".
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WARNING:Xst:646 - Signal <rom_addr_char<7>> is assigned but never used.
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WARNING:Xst:646 - Signal <resetVGA> is assigned but never used.
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WARNING:Xst:646 - Signal <done> is assigned but never used.
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WARNING:Xst:646 - Signal <kb_bsy> is assigned but never used.
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WARNING:Xst:646 - Signal <hloc<2:0>> is assigned but never used.
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WARNING:Xst:646 - Signal <vloc<9>> is assigned but never used.
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Found 7-bit comparator equal for signal <$cmp_eq0001> created at line 159.
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Found 6-bit comparator equal for signal <$cmp_eq0002> created at line 159.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0002>.
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Found 1-bit register for signal <charload>.
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Found 8-bit register for signal <crt_data>.
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Found 1-bit register for signal <crtclk>.
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Found 1-bit register for signal <insert_crt_data>.
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Found 3-bit up counter for signal <pclk>.
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Found 8-bit register for signal <pixel_hold>.
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Found 9-bit register for signal <pixelData>.
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Found 12-bit adder for signal <ram_addr_video>.
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Found 8-bit register for signal <rom_addr_char>.
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Found 12-bit adder for signal <vpos_times_80>.
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Summary:
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inferred 1 Counter(s).
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inferred 36 D-type flip-flop(s).
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inferred 2 Adder/Subtractor(s).
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inferred 2 Comparator(s).
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inferred 8 Multiplexer(s).
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Unit <vga> synthesized.
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Synthesizing Unit <fpga>.
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Related source file is "../../v/fpga.v".
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Found finite state machine <FSM_2> for signal <gray_cnt>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 4 |
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| Inputs | 0 |
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| Outputs | 2 |
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| Clock | clka (rising_edge) |
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| Reset | reset_n (negative) |
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| Reset type | asynchronous |
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| Reset State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Summary:
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inferred 1 Finite State Machine(s).
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Unit <fpga> synthesized.
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INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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2049x8-bit dual-port block RAM : 1
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# ROMs : 3
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1024x8-bit ROM : 1
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4x1-bit ROM : 2
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# Adders/Subtractors : 9
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12-bit adder : 5
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14-bit adder : 1
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4-bit adder : 1
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8-bit adder : 1
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8-bit subtractor : 1
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# Counters : 7
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10-bit up counter : 1
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11-bit up counter : 1
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3-bit up counter : 3
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6-bit up counter : 1
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7-bit up counter : 1
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# Registers : 30
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1-bit register : 17
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10-bit register : 1
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12-bit register : 2
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14-bit register : 1
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4-bit register : 1
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5-bit register : 1
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7-bit register : 1
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8-bit register : 5
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9-bit register : 1
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# Latches : 1
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1-bit latch : 1
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# Comparators : 12
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10-bit comparator greatequal : 2
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10-bit comparator less : 3
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11-bit comparator greatequal : 2
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11-bit comparator less : 3
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6-bit comparator equal : 1
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7-bit comparator equal : 1
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# Multiplexers : 2
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4-bit 4-to-1 multiplexer : 1
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8-bit 4-to-1 multiplexer : 1
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=========================================================================
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|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Analyzing FSM <FSM_2> for best encoding.
|
|
Optimizing FSM <gray_cnt> on signal <gray_cnt[1:2]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
11 | 11
|
|
10 | 10
|
|
-------------------
|
|
Analyzing FSM <FSM_1> for best encoding.
|
|
Optimizing FSM <vga/scancode_convert/state> on signal <state[1:6]> with one-hot encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
000 | 000001
|
|
001 | 000010
|
|
010 | 010000
|
|
011 | 001000
|
|
100 | 000100
|
|
101 | 100000
|
|
-------------------
|
|
Analyzing FSM <FSM_0> for best encoding.
|
|
Optimizing FSM <vga/crt/state> on signal <state[1:13]> with one-hot encoding.
|
|
------------------------
|
|
State | Encoding
|
|
------------------------
|
|
0000 | 0000000000001
|
|
0001 | 0000000000010
|
|
0010 | 0000000000100
|
|
0011 | 0000000001000
|
|
0100 | 0000000010000
|
|
0101 | 0000000100000
|
|
0110 | 0000001000000
|
|
0111 | 0000010000000
|
|
1000 | 0000100000000
|
|
1001 | 0001000000000
|
|
1010 | 0010000000000
|
|
1011 | 0100000000000
|
|
1100 | 1000000000000
|
|
------------------------
|
|
Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
|
|
WARNING:Xst:1291 - FF/Latch <rom_addr_char_7> is unconnected in block <vga>.
|
|
INFO:Xst:2261 - The FF/Latch <pixelData_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <pixelData_1> <pixelData_2> <pixelData_3> <pixelData_4> <pixelData_5> <pixelData_6> <pixelData_7> <pixelData_8>
|
|
WARNING:Xst:1291 - FF/Latch <enable> is unconnected in block <vgacore>.
|
|
WARNING:Xst:1291 - FF/Latch <done> is unconnected in block <crt>.
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# FSMs : 3
|
|
# RAMs : 1
|
|
2049x8-bit dual-port block RAM : 1
|
|
# ROMs : 3
|
|
1024x8-bit ROM : 1
|
|
4x1-bit ROM : 2
|
|
# Adders/Subtractors : 8
|
|
12-bit adder : 4
|
|
14-bit adder : 1
|
|
4-bit adder : 1
|
|
8-bit adder : 1
|
|
8-bit subtractor : 1
|
|
# Counters : 7
|
|
10-bit up counter : 1
|
|
11-bit up counter : 1
|
|
3-bit up counter : 3
|
|
6-bit up counter : 1
|
|
7-bit up counter : 1
|
|
# Registers : 130
|
|
Flip-Flops : 130
|
|
# Latches : 1
|
|
1-bit latch : 1
|
|
# Comparators : 12
|
|
10-bit comparator greatequal : 2
|
|
10-bit comparator less : 3
|
|
11-bit comparator greatequal : 2
|
|
11-bit comparator less : 3
|
|
6-bit comparator equal : 1
|
|
7-bit comparator equal : 1
|
|
# Multiplexers : 9
|
|
1-bit 4-to-1 multiplexer : 8
|
|
4-bit 4-to-1 multiplexer : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
WARNING:Xst:1988 - Unit <vgacore>: instances <Mcompar__cmp_lt0000>, <Mcompar__cmp_ge0001> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_6> are dual, second instance is removed
|
|
WARNING:Xst:1291 - FF/Latch <inst_Mram_mem71> is unconnected in block <vga>.
|
|
|
|
Optimizing unit <fpga> ...
|
|
|
|
Optimizing unit <crt> ...
|
|
|
|
Optimizing unit <vgacore> ...
|
|
|
|
Optimizing unit <scancode_rom> ...
|
|
|
|
Optimizing unit <ps2> ...
|
|
|
|
Optimizing unit <vga> ...
|
|
|
|
Optimizing unit <scancode_convert> ...
|
|
|
|
Mapping all equations...
|
|
WARNING:Xst:1291 - FF/Latch <vga/crt_data_7> is unconnected in block <fpga>.
|
|
WARNING:Xst:1291 - FF/Latch <vga/crt/ram_data_7> is unconnected in block <fpga>.
|
|
WARNING:Xst:1291 - FF/Latch <vga/crt/done> is unconnected in block <fpga>.
|
|
WARNING:Xst:1291 - FF/Latch <vga/vgacore/enable> is unconnected in block <fpga>.
|
|
WARNING:Xst:1291 - FF/Latch <vga/scancode_convert/ascii_7> is unconnected in block <fpga>.
|
|
Building and optimizing final netlist ...
|
|
Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 17.
|
|
FlipFlop vga/rom_addr_char_0 has been replicated 1 time(s)
|
|
FlipFlop vga/rom_addr_char_1 has been replicated 1 time(s)
|
|
FlipFlop vga/scancode_convert/sc_0 has been replicated 1 time(s)
|
|
FlipFlop vga/scancode_convert/sc_1 has been replicated 1 time(s)
|
|
FlipFlop vga/vgacore/vcnt_0 has been replicated 1 time(s)
|
|
FlipFlop vga/vgacore/vcnt_1 has been replicated 1 time(s)
|
|
FlipFlop vga/vgacore/vcnt_2 has been replicated 1 time(s)
|
|
|
|
Final Macro Processing ...
|
|
|
|
Processing Unit <fpga> :
|
|
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <vga/ps2/ps2_clk_r_1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <vga/ps2/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
Unit <fpga> processed.
|
|
|
|
=========================================================================
|
|
Final Register Report
|
|
|
|
Macro Statistics
|
|
# Registers : 175
|
|
Flip-Flops : 175
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : fpga.ngr
|
|
Top Level Output File Name : fpga
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : NO
|
|
|
|
Design Statistics
|
|
# IOs : 23
|
|
|
|
Cell Usage :
|
|
# BELS : 978
|
|
# GND : 1
|
|
# INV : 15
|
|
# LUT1 : 27
|
|
# LUT2 : 71
|
|
# LUT2_D : 1
|
|
# LUT2_L : 1
|
|
# LUT3 : 186
|
|
# LUT3_D : 3
|
|
# LUT3_L : 6
|
|
# LUT4 : 376
|
|
# LUT4_D : 9
|
|
# LUT4_L : 30
|
|
# MULT_AND : 10
|
|
# MUXCY : 60
|
|
# MUXF5 : 100
|
|
# MUXF6 : 26
|
|
# VCC : 1
|
|
# XORCY : 55
|
|
# FlipFlops/Latches : 176
|
|
# FD : 29
|
|
# FDC : 67
|
|
# FDC_1 : 14
|
|
# FDCE : 38
|
|
# FDE : 16
|
|
# FDP : 10
|
|
# FDR : 1
|
|
# LD : 1
|
|
# RAMS : 7
|
|
# RAMB4_S1_S1 : 7
|
|
# Clock Buffers : 3
|
|
# BUFG : 2
|
|
# BUFGP : 1
|
|
# IO Buffers : 22
|
|
# IBUF : 3
|
|
# OBUF : 19
|
|
=========================================================================
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 2s200fg256-5
|
|
|
|
Number of Slices: 387 out of 2352 16%
|
|
Number of Slice Flip Flops: 176 out of 4704 3%
|
|
Number of 4 input LUTs: 725 out of 4704 15%
|
|
Number of IOs: 23
|
|
Number of bonded IOBs: 23 out of 180 12%
|
|
Number of BRAMs: 7 out of 14 50%
|
|
Number of GCLKs: 3 out of 4 75%
|
|
|
|
|
|
=========================================================================
|
|
TIMING REPORT
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
-----------------------------------+---------------------------------+-------+
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
-----------------------------------+---------------------------------+-------+
|
|
clka | BUFGP | 2 |
|
|
gray_cnt_FFd11 | BUFG | 102 |
|
|
vga/pclk_2 | NONE(vga/rom_addr_char_2) | 9 |
|
|
vga/crt/ram_wclk | NONE(vga/video_ram/ram_addr_w_9)| 19 |
|
|
vga/charload | NONE(vga/inst_Mram_mem31) | 7 |
|
|
vga/crtclk1 | BUFG | 37 |
|
|
vga/crt/_or0000(vga/crt/_or00001:O)| NONE(*)(vga/crt/ram_wclk) | 1 |
|
|
vga/vgacore/hblank | NONE(vga/vgacore/vcnt_4) | 13 |
|
|
-----------------------------------+---------------------------------+-------+
|
|
(*) This 1 clock signal(s) are generated by combinatorial logic,
|
|
and XST is not able to identify which are the primary clock signals.
|
|
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
|
|
|
Asynchronous Control Signals Information:
|
|
----------------------------------------
|
|
------------------------------------------------------+------------------------+-------+
|
|
Control Signal | Buffer(FF name) | Load |
|
|
------------------------------------------------------+------------------------+-------+
|
|
gray_cnt_Rst_inv(gray_cnt_Rst_inv1_INV_0:O) | NONE(gray_cnt_FFd1) | 65 |
|
|
gray_cnt_Rst_inv1_INV_0_1(gray_cnt_Rst_inv1_INV_0_1:O)| NONE(vga/vgacore/hsync)| 64 |
|
|
------------------------------------------------------+------------------------+-------+
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -5
|
|
|
|
Minimum period: 13.678ns (Maximum Frequency: 73.110MHz)
|
|
Minimum input arrival time before clock: 2.827ns
|
|
Maximum output required time after clock: 18.188ns
|
|
Maximum combinational path delay: No path found
|
|
|
|
Timing Detail:
|
|
--------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'clka'
|
|
Clock period: 13.121ns (frequency: 76.214MHz)
|
|
Total number of paths / destination ports: 2 / 2
|
|
-------------------------------------------------------------------------
|
|
Delay: 13.121ns (Levels of Logic = 2)
|
|
Source: gray_cnt_FFd1 (FF)
|
|
Destination: gray_cnt_FFd2 (FF)
|
|
Source Clock: clka rising
|
|
Destination Clock: clka rising
|
|
|
|
Data Path: gray_cnt_FFd1 to gray_cnt_FFd2
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDC:C->Q 1 1.292 1.150 gray_cnt_FFd1 (gray_cnt_FFd11)
|
|
BUFG:I->O 103 0.773 7.350 gray_cnt_FFd1_BUFG (gray_cnt_FFd1)
|
|
INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In)
|
|
FDC:D 0.753 gray_cnt_FFd2
|
|
----------------------------------------
|
|
Total 13.121ns (3.471ns logic, 9.650ns route)
|
|
(26.5% logic, 73.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'gray_cnt_FFd11'
|
|
Clock period: 13.025ns (frequency: 76.775MHz)
|
|
Total number of paths / destination ports: 2095 / 138
|
|
-------------------------------------------------------------------------
|
|
Delay: 13.025ns (Levels of Logic = 6)
|
|
Source: vga/scancode_convert/ctrl (FF)
|
|
Destination: vga/scancode_convert/ascii_4 (FF)
|
|
Source Clock: gray_cnt_FFd11 rising
|
|
Destination Clock: gray_cnt_FFd11 rising
|
|
|
|
Data Path: vga/scancode_convert/ctrl to vga/scancode_convert/ascii_4
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 5 1.292 1.740 vga/scancode_convert/ctrl (vga/scancode_convert/ctrl)
|
|
LUT3:I0->O 20 0.653 3.200 vga/scancode_convert/raise1 (vga/scancode_convert/raise)
|
|
LUT3:I1->O 1 0.653 1.150 vga/scancode_convert/scancode_rom/data<3>81 (vga/scancode_convert/scancode_rom/N43)
|
|
LUT4_L:I1->LO 1 0.653 0.100 vga/scancode_convert/scancode_rom/data<4>145 (vga/scancode_convert/scancode_rom/data<4>1_map1650)
|
|
LUT4:I2->O 1 0.653 1.150 vga/scancode_convert/scancode_rom/data<4>182 (vga/scancode_convert/scancode_rom/data<4>1_map1654)
|
|
LUT4:I1->O 1 0.653 0.000 vga/scancode_convert/scancode_rom/data<4>1673_F (N3329)
|
|
MUXF5:I0->O 1 0.375 0.000 vga/scancode_convert/scancode_rom/data<4>1673 (vga/scancode_convert/rom_data<4>)
|
|
FDE:D 0.753 vga/scancode_convert/ascii_4
|
|
----------------------------------------
|
|
Total 13.025ns (5.685ns logic, 7.340ns route)
|
|
(43.6% logic, 56.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'vga/crt/ram_wclk'
|
|
Clock period: 4.587ns (frequency: 218.007MHz)
|
|
Total number of paths / destination ports: 84 / 84
|
|
-------------------------------------------------------------------------
|
|
Delay: 4.587ns (Levels of Logic = 0)
|
|
Source: vga/video_ram/ram_addr_w_11 (FF)
|
|
Destination: vga/inst_Mram_mem8 (RAM)
|
|
Source Clock: vga/crt/ram_wclk rising
|
|
Destination Clock: vga/crt/ram_wclk rising
|
|
|
|
Data Path: vga/video_ram/ram_addr_w_11 to vga/inst_Mram_mem8
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 7 1.292 1.950 vga/video_ram/ram_addr_w_11 (vga/video_ram/ram_addr_w_11)
|
|
RAMB4_S1_S1:ADDRA11 1.345 vga/inst_Mram_mem61
|
|
----------------------------------------
|
|
Total 4.587ns (2.637ns logic, 1.950ns route)
|
|
(57.5% logic, 42.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'vga/crtclk1'
|
|
Clock period: 11.607ns (frequency: 86.155MHz)
|
|
Total number of paths / destination ports: 703 / 50
|
|
-------------------------------------------------------------------------
|
|
Delay: 11.607ns (Levels of Logic = 4)
|
|
Source: vga/crt/cursor_h_0 (FF)
|
|
Destination: vga/crt/cursor_h_0 (FF)
|
|
Source Clock: vga/crtclk1 rising
|
|
Destination Clock: vga/crtclk1 rising
|
|
|
|
Data Path: vga/crt/cursor_h_0 to vga/crt/cursor_h_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 10 1.292 2.200 vga/crt/cursor_h_0 (vga/crt/cursor_h_0)
|
|
LUT4_L:I1->LO 1 0.653 0.100 vga/crt/eol_SW1 (N3311)
|
|
LUT4:I0->O 16 0.653 2.800 vga/crt/eol (vga/crt/eol)
|
|
LUT4_D:I3->O 6 0.653 1.850 vga/crt/_and000019 (vga/crt/_and0000_map1131)
|
|
LUT4:I1->O 1 0.653 0.000 vga/crt/cursor_h_Eqn_51 (vga/crt/cursor_h_Eqn_5)
|
|
FDCE:D 0.753 vga/crt/cursor_h_5
|
|
----------------------------------------
|
|
Total 11.607ns (4.657ns logic, 6.950ns route)
|
|
(40.1% logic, 59.9% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'vga/vgacore/hblank'
|
|
Clock period: 13.678ns (frequency: 73.110MHz)
|
|
Total number of paths / destination ports: 566 / 13
|
|
-------------------------------------------------------------------------
|
|
Delay: 13.678ns (Levels of Logic = 13)
|
|
Source: vga/vgacore/vcnt_1 (FF)
|
|
Destination: vga/vgacore/vcnt_9 (FF)
|
|
Source Clock: vga/vgacore/hblank falling
|
|
Destination Clock: vga/vgacore/hblank falling
|
|
|
|
Data Path: vga/vgacore/vcnt_1 to vga/vgacore/vcnt_9
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDC_1:C->Q 87 1.292 6.550 vga/vgacore/vcnt_1 (vga/vgacore/vcnt_1)
|
|
LUT4_D:I1->LO 1 0.653 0.100 vga/vgacore/vcnt_Eqn_911 (N3480)
|
|
LUT4:I1->O 2 0.653 1.340 vga/vgacore/vcnt_Eqn_bis_021 (vga/vgacore/vcnt_Eqn_bis_0)
|
|
LUT2:I1->O 2 0.653 0.000 vga/vgacore/Mcount_vcnt_lut<0> (vga/vgacore/Result<0>1)
|
|
MUXCY:S->O 1 0.784 0.000 vga/vgacore/Mcount_vcnt_cy<0> (vga/vgacore/Mcount_vcnt_cy<0>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<1> (vga/vgacore/Mcount_vcnt_cy<1>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<2> (vga/vgacore/Mcount_vcnt_cy<2>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<3> (vga/vgacore/Mcount_vcnt_cy<3>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<4> (vga/vgacore/Mcount_vcnt_cy<4>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<5> (vga/vgacore/Mcount_vcnt_cy<5>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<6> (vga/vgacore/Mcount_vcnt_cy<6>)
|
|
MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<7> (vga/vgacore/Mcount_vcnt_cy<7>)
|
|
MUXCY:CI->O 0 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<8> (vga/vgacore/Mcount_vcnt_cy<8>)
|
|
XORCY:CI->O 1 0.500 0.000 vga/vgacore/Mcount_vcnt_xor<9> (vga/vgacore/Result<9>1)
|
|
FDC_1:D 0.753 vga/vgacore/vcnt_9
|
|
----------------------------------------
|
|
Total 13.678ns (5.688ns logic, 7.990ns route)
|
|
(41.6% logic, 58.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd11'
|
|
Total number of paths / destination ports: 2 / 2
|
|
-------------------------------------------------------------------------
|
|
Offset: 2.827ns (Levels of Logic = 1)
|
|
Source: ps2_clk (PAD)
|
|
Destination: vga/ps2/ps2_clk_r_0 (FF)
|
|
Destination Clock: gray_cnt_FFd11 rising
|
|
|
|
Data Path: ps2_clk to vga/ps2/ps2_clk_r_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 1 0.924 1.150 ps2_clk_IBUF (ps2_clk_IBUF)
|
|
FDP:D 0.753 vga/ps2/ps2_clk_r_0
|
|
----------------------------------------
|
|
Total 2.827ns (1.677ns logic, 1.150ns route)
|
|
(59.3% logic, 40.7% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'gray_cnt_FFd11'
|
|
Total number of paths / destination ports: 28 / 19
|
|
-------------------------------------------------------------------------
|
|
Offset: 12.522ns (Levels of Logic = 2)
|
|
Source: vga/vgacore/hblank (FF)
|
|
Destination: vga_red0 (PAD)
|
|
Source Clock: gray_cnt_FFd11 rising
|
|
|
|
Data Path: vga/vgacore/hblank to vga_red0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDC:C->Q 17 1.292 2.900 vga/vgacore/hblank (vga/vgacore/hblank)
|
|
LUT3:I2->O 9 0.653 2.120 vga/pixel<8>27 (pixel<8>)
|
|
OBUF:I->O 5.557 vga_red1_OBUF (vga_red1)
|
|
----------------------------------------
|
|
Total 12.522ns (7.502ns logic, 5.020ns route)
|
|
(59.9% logic, 40.1% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'vga/vgacore/hblank'
|
|
Total number of paths / destination ports: 108 / 9
|
|
-------------------------------------------------------------------------
|
|
Offset: 18.188ns (Levels of Logic = 4)
|
|
Source: vga/vgacore/vcnt_2_1 (FF)
|
|
Destination: vga_red0 (PAD)
|
|
Source Clock: vga/vgacore/hblank falling
|
|
|
|
Data Path: vga/vgacore/vcnt_2_1 to vga_red0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDC_1:C->Q 84 1.292 6.400 vga/vgacore/vcnt_2_1 (vga/vgacore/vcnt_2_1)
|
|
LUT3:I1->O 1 0.653 0.000 vga/pixel<8>191 (N3439)
|
|
MUXF5:I1->O 1 0.363 1.150 vga/pixel<8>19_f5 (vga/pixel<8>_map785)
|
|
LUT3:I0->O 9 0.653 2.120 vga/pixel<8>27 (pixel<8>)
|
|
OBUF:I->O 5.557 vga_red1_OBUF (vga_red1)
|
|
----------------------------------------
|
|
Total 18.188ns (8.518ns logic, 9.670ns route)
|
|
(46.8% logic, 53.2% route)
|
|
|
|
=========================================================================
|
|
CPU : 30.25 / 30.36 s | Elapsed : 31.00 / 33.00 s
|
|
|
|
-->
|
|
|
|
|
|
Total memory usage is 262956 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 21 ( 0 filtered)
|
|
Number of infos : 6 ( 0 filtered)
|
|
|