1666 lines
75 KiB
Plaintext
1666 lines
75 KiB
Plaintext
Release 8.2.03i - xst I.34
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s
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--> Reading design: top.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "top.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "top"
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Output Format : NGC
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Target Device : xc3s1000-5-ft256
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---- Source Options
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Top Module Name : top
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : top.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../rtl/ide.v" in library work
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Compiling verilog file "../../rtl/uart.v" in library work
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Module <ide> compiled
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Compiling verilog file "../../rtl/ram_256x12.v" in library work
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Module <uart> compiled
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Compiling verilog file "../../rtl/ide_disk.v" in library work
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Module <ram_256x12> compiled
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Compiling verilog file "../../rtl/brg.v" in library work
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Module <ide_disk> compiled
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Compiling verilog file "../../rtl/sevensegdecode.v" in library work
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Module <brg> compiled
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Compiling verilog file "../../rtl/pdp8_tt.v" in library work
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Module <sevensegdecode> compiled
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Compiling verilog file "../../rtl/pdp8_rf.v" in library work
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Module <pdp8_tt> compiled
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Compiling verilog file "../../rtl/pdp8_kw.v" in library work
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Module <pdp8_rf> compiled
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Compiling verilog file "../../rtl/bootrom.v" in library work
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Module <pdp8_kw> compiled
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Compiling verilog file "../../rtl/pdp8_ram.v" in library work
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Module <bootrom> compiled
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Compiling verilog file "../../rtl/pdp8_io.v" in library work
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Module <pdp8_ram> compiled
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Compiling verilog file "../../rtl/pdp8.v" in library work
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Module <pdp8_io> compiled
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Compiling verilog file "../../rtl/display.v" in library work
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Module <pdp8> compiled
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Compiling verilog file "../../rtl/debounce.v" in library work
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Module <display> compiled
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Compiling verilog file "../../rtl/top.v" in library work
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Module <debounce> compiled
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Module <top> compiled
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No errors in compilation
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Analysis of file <"top.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <top> in library <work>.
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Analyzing hierarchy for module <debounce> in library <work>.
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Analyzing hierarchy for module <display> in library <work>.
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Analyzing hierarchy for module <pdp8> in library <work> with parameters.
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D0 = "0100"
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D1 = "0101"
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D2 = "0110"
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D3 = "0111"
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E0 = "1000"
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E1 = "1001"
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E2 = "1010"
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E3 = "1011"
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F0 = "0000"
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F1 = "0001"
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F2 = "0010"
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F3 = "0011"
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H0 = "1100"
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Analyzing hierarchy for module <pdp8_io> in library <work>.
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Analyzing hierarchy for module <pdp8_ram> in library <work>.
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Analyzing hierarchy for module <sevensegdecode> in library <work>.
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Analyzing hierarchy for module <pdp8_kw> in library <work> with parameters.
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F2 = "0010"
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F3 = "0011"
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F1 = "0001"
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F0 = "0000"
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Analyzing hierarchy for module <pdp8_tt> in library <work> with parameters.
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F3 = "0011"
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F2 = "0010"
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F1 = "0001"
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F0 = "0000"
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Analyzing hierarchy for module <pdp8_rf> in library <work> with parameters.
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CA_ADDR = "000111111101001"
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CIE_bit = "000001000000"
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DB_begin_xfer_write = "0111"
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DB_check_xfer_read = "0100"
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DB_check_xfer_write = "1000"
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DB_done_xfer = "1001"
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DB_done_xfer1 = "1010"
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DB_done_xfer2 = "1011"
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DB_done_xfer3 = "1100"
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DB_idle = "0000"
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DB_next_xfer_incr = "0110"
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DB_next_xfer_read = "0101"
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DB_read_new_page = "1101"
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DB_start_xfer1 = "0001"
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DB_start_xfer2 = "0010"
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DB_start_xfer3 = "0011"
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DB_write_old_page = "1110"
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DRE_bit = "010000000000"
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DRL_bit = "000000000100"
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EIE_bit = "000100000000"
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F0 = "0000"
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F1 = "0001"
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F2 = "0010"
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F3 = "0011"
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MEX_bit = "000000111000"
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NXD_bit = "000000000010"
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PCA_bit = "100000000000"
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PER_bit = "000000000001"
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PIE_bit = "000010000000"
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WC_ADDR = "000111111101000"
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WLS_bit = "001000000000"
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Analyzing hierarchy for module <bootrom> in library <work>.
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Analyzing hierarchy for module <brg> in library <work> with parameters.
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TX_CLK_DIV = "00000000000000000000101000101100"
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SYS_CLK = "10111110101111000010000000"
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RX_CLK_DIV = "00000000000000000000000010100010"
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BAUD = "0010010110000000"
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Analyzing hierarchy for module <uart> in library <work>.
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Analyzing hierarchy for module <ram_256x12> in library <work>.
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Analyzing hierarchy for module <ide_disk> in library <work> with parameters.
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ATA_ALTER = "01110"
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ATA_CMD_READ = "0000000000100000"
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ATA_CMD_WRITE = "0000000000110000"
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ATA_COMMAND = "10111"
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ATA_CYLHIGH = "10101"
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ATA_CYLLOW = "10100"
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ATA_DATA = "10000"
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ATA_DEVCTRL = "01110"
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ATA_DRVHEAD = "10110"
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ATA_ERROR = "10001"
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ATA_FEATURE = "10001"
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ATA_SECCNT = "10010"
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ATA_SECNUM = "10011"
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ATA_STATUS = "10111"
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IDE_STATUS_BSY = "00000000000000000000000000000111"
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IDE_STATUS_CORR = "00000000000000000000000000000010"
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IDE_STATUS_DRDY = "00000000000000000000000000000110"
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IDE_STATUS_DRQ = "00000000000000000000000000000011"
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IDE_STATUS_DSC = "00000000000000000000000000000100"
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IDE_STATUS_DWF = "00000000000000000000000000000101"
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IDE_STATUS_ERR = "00000000000000000000000000000000"
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IDE_STATUS_IDX = "00000000000000000000000000000001"
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init0 = "00001"
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init1 = "00010"
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init10 = "01011"
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init11 = "01100"
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init2 = "00011"
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init3 = "00100"
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init4 = "00101"
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init5 = "00110"
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init6 = "00111"
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init7 = "01000"
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init8 = "01001"
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init9 = "01010"
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last0 = "10001"
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last1 = "10010"
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last2 = "10011"
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last3 = "10100"
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read0 = "01101"
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read1 = "01110"
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ready = "00000"
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wait0 = "10101"
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wait1 = "10110"
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write0 = "01111"
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write1 = "10000"
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Analyzing hierarchy for module <ide> in library <work> with parameters.
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s4 = "101"
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s3 = "100"
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s2 = "011"
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s1 = "010"
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s0 = "001"
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idle = "000"
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <top>.
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Module <top> is correct for synthesis.
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Analyzing module <debounce> in library <work>.
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Module <debounce> is correct for synthesis.
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Analyzing module <display> in library <work>.
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Module <display> is correct for synthesis.
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Analyzing module <sevensegdecode> in library <work>.
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Module <sevensegdecode> is correct for synthesis.
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Analyzing module <pdp8> in library <work>.
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F0 = 4'b0000
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F1 = 4'b0001
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F2 = 4'b0010
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F3 = 4'b0011
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D0 = 4'b0100
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D1 = 4'b0101
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D2 = 4'b0110
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D3 = 4'b0111
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E0 = 4'b1000
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E1 = 4'b1001
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E2 = 4'b1010
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E3 = 4'b1011
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H0 = 4'b1100
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Module <pdp8> is correct for synthesis.
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Analyzing module <pdp8_io> in library <work>.
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Module <pdp8_io> is correct for synthesis.
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Analyzing module <pdp8_kw> in library <work>.
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F0 = 4'b0000
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F1 = 4'b0001
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F2 = 4'b0010
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F3 = 4'b0011
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Module <pdp8_kw> is correct for synthesis.
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Analyzing module <pdp8_tt> in library <work>.
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F0 = 4'b0000
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F1 = 4'b0001
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F2 = 4'b0010
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F3 = 4'b0011
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Module <pdp8_tt> is correct for synthesis.
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Analyzing module <brg> in library <work>.
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SYS_CLK = 26'b10111110101111000010000000
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BAUD = 16'b0010010110000000
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RX_CLK_DIV = 32'b00000000000000000000000010100010
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TX_CLK_DIV = 32'b00000000000000000000101000101100
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Module <brg> is correct for synthesis.
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Analyzing module <uart> in library <work>.
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Module <uart> is correct for synthesis.
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Analyzing module <pdp8_rf> in library <work>.
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F0 = 4'b0000
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F1 = 4'b0001
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F2 = 4'b0010
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F3 = 4'b0011
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PCA_bit = 12'b100000000000
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DRE_bit = 12'b010000000000
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WLS_bit = 12'b001000000000
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EIE_bit = 12'b000100000000
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PIE_bit = 12'b000010000000
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CIE_bit = 12'b000001000000
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MEX_bit = 12'b000000111000
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DRL_bit = 12'b000000000100
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NXD_bit = 12'b000000000010
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PER_bit = 12'b000000000001
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WC_ADDR = 15'b000111111101000
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CA_ADDR = 15'b000111111101001
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DB_idle = 4'b0000
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DB_start_xfer1 = 4'b0001
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DB_start_xfer2 = 4'b0010
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DB_start_xfer3 = 4'b0011
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DB_check_xfer_read = 4'b0100
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DB_next_xfer_read = 4'b0101
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DB_next_xfer_incr = 4'b0110
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DB_begin_xfer_write = 4'b0111
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DB_check_xfer_write = 4'b1000
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DB_done_xfer = 4'b1001
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DB_done_xfer1 = 4'b1010
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DB_done_xfer2 = 4'b1011
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DB_done_xfer3 = 4'b1100
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DB_read_new_page = 4'b1101
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DB_write_old_page = 4'b1110
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Module <pdp8_rf> is correct for synthesis.
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Analyzing module <ram_256x12> in library <work>.
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Module <ram_256x12> is correct for synthesis.
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Analyzing module <ide_disk> in library <work>.
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ready = 5'b00000
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init0 = 5'b00001
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init1 = 5'b00010
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init2 = 5'b00011
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init3 = 5'b00100
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init4 = 5'b00101
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init5 = 5'b00110
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init6 = 5'b00111
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init7 = 5'b01000
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init8 = 5'b01001
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init9 = 5'b01010
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init10 = 5'b01011
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init11 = 5'b01100
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read0 = 5'b01101
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read1 = 5'b01110
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write0 = 5'b01111
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write1 = 5'b10000
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last0 = 5'b10001
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last1 = 5'b10010
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last2 = 5'b10011
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last3 = 5'b10100
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wait0 = 5'b10101
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wait1 = 5'b10110
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ATA_ALTER = 5'b01110
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ATA_DEVCTRL = 5'b01110
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ATA_DATA = 5'b10000
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ATA_ERROR = 5'b10001
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ATA_FEATURE = 5'b10001
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ATA_SECCNT = 5'b10010
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ATA_SECNUM = 5'b10011
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ATA_CYLLOW = 5'b10100
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ATA_CYLHIGH = 5'b10101
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ATA_DRVHEAD = 5'b10110
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ATA_STATUS = 5'b10111
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ATA_COMMAND = 5'b10111
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IDE_STATUS_BSY = 32'sb00000000000000000000000000000111
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IDE_STATUS_DRDY = 32'sb00000000000000000000000000000110
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IDE_STATUS_DWF = 32'sb00000000000000000000000000000101
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IDE_STATUS_DSC = 32'sb00000000000000000000000000000100
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IDE_STATUS_DRQ = 32'sb00000000000000000000000000000011
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IDE_STATUS_CORR = 32'sb00000000000000000000000000000010
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IDE_STATUS_IDX = 32'sb00000000000000000000000000000001
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IDE_STATUS_ERR = 32'sb00000000000000000000000000000000
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ATA_CMD_READ = 16'b0000000000100000
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ATA_CMD_WRITE = 16'b0000000000110000
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Module <ide_disk> is correct for synthesis.
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Analyzing module <ide> in library <work>.
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idle = 3'b000
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s0 = 3'b001
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s1 = 3'b010
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s2 = 3'b011
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s3 = 3'b100
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s4 = 3'b101
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Module <ide> is correct for synthesis.
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Analyzing module <pdp8_ram> in library <work>.
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Module <pdp8_ram> is correct for synthesis.
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Analyzing module <bootrom> in library <work>.
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Module <bootrom> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:1304 - Contents of register <is_write> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic.
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INFO:Xst:1304 - Contents of register <PEF> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic.
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INFO:Xst:1304 - Contents of register <NXD> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic.
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INFO:Xst:1304 - Contents of register <WLS> in unit <pdp8_rf> never changes during circuit operation. The register is replaced by logic.
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Synthesizing Unit <debounce>.
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Related source file is "../../rtl/debounce.v".
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Found 15-bit up counter for signal <clkdiv>.
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Found 10-bit register for signal <hold>.
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Found 1-bit register for signal <onetime>.
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Found 1-bit register for signal <slowclk>.
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Summary:
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inferred 1 Counter(s).
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inferred 12 D-type flip-flop(s).
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Unit <debounce> synthesized.
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Synthesizing Unit <pdp8>.
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Related source file is "../../rtl/pdp8.v".
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WARNING:Xst:646 - Signal <fetch> is assigned but never used.
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WARNING:Xst:646 - Signal <execute> is assigned but never used.
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WARNING:Xst:646 - Signal <deferred> is assigned but never used.
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Found 8x8-bit ROM for signal <$AUX_16>.
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Found 4x1-bit ROM for signal <$mux0005>.
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Found 4-bit register for signal <state>.
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Found 12-bit register for signal <mb>.
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Found 12-bit adder for signal <$add0000> created at line 482.
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Found 12-bit adder carry out for signal <$addsub0000> created at line 425.
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Found 12-bit adder carry out for signal <$addsub0001> created at line 425.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0022>.
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Found 12-bit adder for signal <$share0000> created at line 565.
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Found 1-bit xor2 for signal <$xor0059> created at line 348.
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Found 12-bit register for signal <ac>.
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Found 3-bit register for signal <DF>.
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Found 15-bit register for signal <ea>.
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Found 3-bit register for signal <IB>.
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Found 1-bit register for signal <IB_pending>.
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Found 3-bit register for signal <IF>.
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Found 1-bit register for signal <interrupt>.
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Found 1-bit register for signal <interrupt_cycle>.
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Found 1-bit register for signal <interrupt_enable>.
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Found 1-bit register for signal <interrupt_inhibit_clear>.
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Found 2-bit register for signal <interrupt_inhibit_delay>.
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Found 1-bit register for signal <interrupt_inhibit_ib>.
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Found 1-bit register for signal <interrupt_inhibit_ion>.
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Found 1-bit register for signal <interrupt_inhibit_ub>.
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Found 1-bit register for signal <interrupt_skip>.
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Found 3-bit register for signal <ir>.
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Found 1-bit register for signal <ir_i_flag>.
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Found 1-bit register for signal <ir_z_flag>.
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Found 1-bit register for signal <l>.
|
|
Found 12-bit register for signal <mq>.
|
|
Found 4-bit 4-to-1 multiplexer for signal <next_state>.
|
|
Found 12-bit register for signal <pc>.
|
|
Found 1-bit register for signal <run>.
|
|
Found 7-bit register for signal <SF>.
|
|
Found 1-bit register for signal <UB>.
|
|
Found 1-bit register for signal <UB_pending>.
|
|
Found 1-bit register for signal <UF>.
|
|
Found 1-bit register for signal <UI>.
|
|
Summary:
|
|
inferred 2 ROM(s).
|
|
inferred 93 D-type flip-flop(s).
|
|
inferred 6 Adder/Subtractor(s).
|
|
inferred 7 Multiplexer(s).
|
|
Unit <pdp8> synthesized.
|
|
|
|
|
|
Synthesizing Unit <sevensegdecode>.
|
|
Related source file is "../../rtl/sevensegdecode.v".
|
|
Found 16x7-bit ROM for signal <ss_out>.
|
|
Summary:
|
|
inferred 1 ROM(s).
|
|
Unit <sevensegdecode> synthesized.
|
|
|
|
|
|
Synthesizing Unit <pdp8_kw>.
|
|
Related source file is "../../rtl/pdp8_kw.v".
|
|
WARNING:Xst:647 - Input <mb<11:3>> is never used.
|
|
Found 4x1-bit ROM for signal <io_selected>.
|
|
Found 1-bit register for signal <kw_clk_en>.
|
|
Found 12-bit up counter for signal <kw_ctr>.
|
|
Found 1-bit register for signal <kw_flag>.
|
|
Found 1-bit register for signal <kw_int_en>.
|
|
Found 1-bit register for signal <kw_src_clk>.
|
|
Found 2-bit up counter for signal <kw_src_ctr>.
|
|
Summary:
|
|
inferred 1 ROM(s).
|
|
inferred 2 Counter(s).
|
|
inferred 4 D-type flip-flop(s).
|
|
Unit <pdp8_kw> synthesized.
|
|
|
|
|
|
Synthesizing Unit <brg>.
|
|
Related source file is "../../rtl/brg.v".
|
|
Found 1-bit register for signal <tx_baud_clk>.
|
|
Found 1-bit register for signal <rx_baud_clk>.
|
|
Found 13-bit up counter for signal <rx_clk_div>.
|
|
Found 13-bit up counter for signal <tx_clk_div>.
|
|
Summary:
|
|
inferred 2 Counter(s).
|
|
inferred 2 D-type flip-flop(s).
|
|
Unit <brg> synthesized.
|
|
|
|
|
|
Synthesizing Unit <uart>.
|
|
Related source file is "../../rtl/uart.v".
|
|
WARNING:Xst:647 - Input <clk> is never used.
|
|
WARNING:Xst:646 - Signal <tx_over_run> is assigned but never used.
|
|
WARNING:Xst:646 - Signal <rx_frame_err> is assigned but never used.
|
|
WARNING:Xst:646 - Signal <rx_over_run> is assigned but never used.
|
|
Found finite state machine <FSM_0> for signal <rx_uld>.
|
|
-----------------------------------------------------------------------
|
|
| States | 3 |
|
|
| Transitions | 5 |
|
|
| Inputs | 1 |
|
|
| Outputs | 2 |
|
|
| Clock | rx_clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | 00 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found finite state machine <FSM_1> for signal <tx_ld>.
|
|
-----------------------------------------------------------------------
|
|
| States | 3 |
|
|
| Transitions | 5 |
|
|
| Inputs | 1 |
|
|
| Outputs | 2 |
|
|
| Clock | tx_clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | 00 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 8-bit register for signal <rx_data>.
|
|
Found 1-bit register for signal <tx_empty>.
|
|
Found 1-bit register for signal <tx_out>.
|
|
Found 1-bit register for signal <rx_empty>.
|
|
Found 4-bit adder for signal <$addsub0000> created at line 161.
|
|
Found 4-bit comparator greatequal for signal <$cmp_ge0000> created at line 164.
|
|
Found 4-bit comparator lessequal for signal <$cmp_le0000> created at line 164.
|
|
Found 1-bit register for signal <rx_busy>.
|
|
Found 4-bit register for signal <rx_cnt>.
|
|
Found 1-bit register for signal <rx_d1>.
|
|
Found 1-bit register for signal <rx_d2>.
|
|
Found 8-bit register for signal <rx_reg>.
|
|
Found 4-bit up counter for signal <rx_sample_cnt>.
|
|
Found 4-bit up counter for signal <tx_cnt>.
|
|
Found 8-bit register for signal <tx_reg>.
|
|
Summary:
|
|
inferred 2 Finite State Machine(s).
|
|
inferred 2 Counter(s).
|
|
inferred 34 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
inferred 2 Comparator(s).
|
|
Unit <uart> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ram_256x12>.
|
|
Related source file is "../../rtl/ram_256x12.v".
|
|
WARNING:Xst:647 - Input <reset> is never used.
|
|
Found 256x12-bit single-port distributed RAM for signal <ram>.
|
|
-----------------------------------------------------------------------
|
|
| ram_style | Auto | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 256-word x 12-bit | |
|
|
| clkA | connected to signal <clk> | rise |
|
|
| weA | connected to internal node | high |
|
|
| addrA | connected to signal <a> | |
|
|
| diA | connected to signal <din> | |
|
|
| doA | connected to signal <dout> | |
|
|
-----------------------------------------------------------------------
|
|
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
Unit <ram_256x12> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ide>.
|
|
Related source file is "../../rtl/ide.v".
|
|
Found finite state machine <FSM_2> for signal <ata_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 6 |
|
|
| Transitions | 8 |
|
|
| Inputs | 2 |
|
|
| Outputs | 5 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 000 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 16-bit register for signal <ata_out>.
|
|
Found 16-bit tristate buffer for signal <ide_data_bus>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 16 D-type flip-flop(s).
|
|
inferred 16 Tristate(s).
|
|
Unit <ide> synthesized.
|
|
|
|
|
|
Synthesizing Unit <bootrom>.
|
|
Related source file is "../../rtl/bootrom.v".
|
|
WARNING:Xst:737 - Found 12-bit latch for signal <data>.
|
|
Found 15-bit comparator greatequal for signal <$cmp_ge0000> created at line 31.
|
|
Found 15-bit comparator lessequal for signal <$cmp_le0000> created at line 31.
|
|
Found 3-bit down counter for signal <delay>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 2 Comparator(s).
|
|
Unit <bootrom> synthesized.
|
|
|
|
|
|
Synthesizing Unit <display>.
|
|
Related source file is "../../rtl/display.v".
|
|
WARNING:Xst:647 - Input <reset> is never used.
|
|
Found 1-of-4 decoder for signal <sevenseg_an>.
|
|
Found 1-bit register for signal <aclk>.
|
|
Found 2-bit up counter for signal <anode>.
|
|
Found 3-bit 4-to-1 multiplexer for signal <digit>.
|
|
Found 11-bit up counter for signal <divider>.
|
|
Summary:
|
|
inferred 2 Counter(s).
|
|
inferred 1 D-type flip-flop(s).
|
|
inferred 4 Multiplexer(s).
|
|
inferred 1 Decoder(s).
|
|
Unit <display> synthesized.
|
|
|
|
|
|
Synthesizing Unit <pdp8_ram>.
|
|
Related source file is "../../rtl/pdp8_ram.v".
|
|
Found 16-bit tristate buffer for signal <$mux0000>.
|
|
Summary:
|
|
inferred 16 Tristate(s).
|
|
Unit <pdp8_ram> synthesized.
|
|
|
|
|
|
Synthesizing Unit <pdp8_tt>.
|
|
Related source file is "../../rtl/pdp8_tt.v".
|
|
WARNING:Xst:647 - Input <mb<11:3>> is never used.
|
|
WARNING:Xst:646 - Signal <tto_empty> is assigned but never used.
|
|
Found finite state machine <FSM_3> for signal <tto_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 10 |
|
|
| Inputs | 3 |
|
|
| Outputs | 5 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 00 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found finite state machine <FSM_4> for signal <tti_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 10 |
|
|
| Inputs | 3 |
|
|
| Outputs | 4 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 00 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit 4-to-1 multiplexer for signal <io_skip>.
|
|
Found 1-bit register for signal <rx_int>.
|
|
Found 8-bit register for signal <tx_data>.
|
|
Found 1-bit register for signal <tx_int>.
|
|
Summary:
|
|
inferred 2 Finite State Machine(s).
|
|
inferred 10 D-type flip-flop(s).
|
|
inferred 1 Multiplexer(s).
|
|
Unit <pdp8_tt> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ide_disk>.
|
|
Related source file is "../../rtl/ide_disk.v".
|
|
WARNING:Xst:1305 - Output <ide_error> is never assigned. Tied to value 0.
|
|
WARNING:Xst:646 - Signal <ata_out<15:12>> is assigned but never used.
|
|
WARNING:Xst:646 - Signal <err> is assigned but never used.
|
|
Found finite state machine <FSM_5> for signal <ide_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 23 |
|
|
| Transitions | 49 |
|
|
| Inputs | 8 |
|
|
| Outputs | 21 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 00000 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit register for signal <done>.
|
|
Found 8-bit up counter for signal <offset>.
|
|
Found 8-bit up counter for signal <wc>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 2 Counter(s).
|
|
inferred 1 D-type flip-flop(s).
|
|
Unit <ide_disk> synthesized.
|
|
|
|
|
|
Synthesizing Unit <pdp8_rf>.
|
|
Related source file is "../../rtl/pdp8_rf.v".
|
|
WARNING:Xst:647 - Input <mb<11:3>> is never used.
|
|
WARNING:Xst:646 - Signal <ide_error> is assigned but never used.
|
|
WARNING:Xst:646 - Signal <PEF> is assigned but never used.
|
|
WARNING:Xst:646 - Signal <buffer_rd> is assigned but never used.
|
|
WARNING:Xst:646 - Signal <active> is assigned but never used.
|
|
Found finite state machine <FSM_6> for signal <db_state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 15 |
|
|
| Transitions | 34 |
|
|
| Inputs | 8 |
|
|
| Outputs | 11 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | reset (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | 0000 |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 4x2-bit ROM for signal <$rom0000>.
|
|
Found 4x1-bit ROM for signal <set_db_done>.
|
|
Found 4x1-bit ROM for signal <load_buffer_hold>.
|
|
Found 4x1-bit ROM for signal <set_buffer_dirty>.
|
|
Found 4x1-bit ROM for signal <$mux0029> created at line 622.
|
|
Found 1-bit 4-to-1 multiplexer for signal <io_clear_ac>.
|
|
Found 12-bit 4-to-1 multiplexer for signal <io_data_out>.
|
|
Found 1-bit 4-to-1 multiplexer for signal <io_skip>.
|
|
Found 12-bit adder for signal <$add0001> created at line 977.
|
|
Found 12-bit adder for signal <$add0002> created at line 959.
|
|
Found 12-bit adder for signal <$addsub0000> created at line 978.
|
|
Found 1-bit 4-to-1 multiplexer for signal <$mux0026>.
|
|
Found 1-bit 4-to-1 multiplexer for signal <$mux0027>.
|
|
Found 1-bit register for signal <buffer_dirty>.
|
|
Found 12-bit register for signal <buffer_disk_addr>.
|
|
Found 12-bit register for signal <buffer_hold>.
|
|
Found 12-bit comparator equal for signal <buffer_matches_DMA>.
|
|
Found 1-bit register for signal <CIE>.
|
|
Found 1-bit register for signal <db_done>.
|
|
Found 1-bit register for signal <DCF>.
|
|
Found 20-bit up counter for signal <disk_addr>.
|
|
Found 12-bit register for signal <DMA>.
|
|
Found 15-bit register for signal <dma_addr>.
|
|
Found 12-bit register for signal <dma_wc>.
|
|
Found 1-bit register for signal <EIE>.
|
|
Found 8-bit register for signal <EMA>.
|
|
Found 1-bit register for signal <is_read>.
|
|
Found 3-bit register for signal <MEX>.
|
|
Found 8-bit comparator less for signal <PCA>.
|
|
Found 8-bit up counter for signal <photocell_counter>.
|
|
Found 1-bit register for signal <PIE>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 5 ROM(s).
|
|
inferred 2 Counter(s).
|
|
inferred 81 D-type flip-flop(s).
|
|
inferred 3 Adder/Subtractor(s).
|
|
inferred 2 Comparator(s).
|
|
inferred 16 Multiplexer(s).
|
|
Unit <pdp8_rf> synthesized.
|
|
|
|
|
|
Synthesizing Unit <pdp8_io>.
|
|
Related source file is "../../rtl/pdp8_io.v".
|
|
Found 1-bit 4-to-1 multiplexer for signal <io_clear_ac>.
|
|
Found 12-bit 4-to-1 multiplexer for signal <io_data_out>.
|
|
Found 1-bit 4-to-1 multiplexer for signal <io_data_avail>.
|
|
Summary:
|
|
inferred 14 Multiplexer(s).
|
|
Unit <pdp8_io> synthesized.
|
|
|
|
|
|
Synthesizing Unit <top>.
|
|
Related source file is "../../rtl/top.v".
|
|
WARNING:Xst:647 - Input <slideswitch<7:4>> is never used.
|
|
WARNING:Xst:647 - Input <button<2:0>> is never used.
|
|
WARNING:Xst:653 - Signal <switches> is used but never assigned. Tied to value 000000000000.
|
|
Found 16x25-bit ROM for signal <clkmax>.
|
|
Found 25-bit comparator equal for signal <$cmp_eq0000> created at line 77.
|
|
Found 1-bit register for signal <clk>.
|
|
Found 25-bit up counter for signal <clkdiv>.
|
|
Summary:
|
|
inferred 1 ROM(s).
|
|
inferred 1 Counter(s).
|
|
inferred 1 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
Unit <top> synthesized.
|
|
|
|
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 1
|
|
256x12-bit single-port distributed RAM : 1
|
|
# ROMs : 10
|
|
16x25-bit ROM : 1
|
|
16x7-bit ROM : 1
|
|
4x1-bit ROM : 6
|
|
4x2-bit ROM : 1
|
|
8x8-bit ROM : 1
|
|
# Adders/Subtractors : 10
|
|
12-bit adder : 5
|
|
12-bit adder carry out : 2
|
|
13-bit adder : 2
|
|
4-bit adder : 1
|
|
# Counters : 15
|
|
11-bit up counter : 1
|
|
12-bit up counter : 1
|
|
13-bit up counter : 2
|
|
15-bit up counter : 1
|
|
2-bit up counter : 2
|
|
20-bit up counter : 1
|
|
25-bit up counter : 1
|
|
3-bit down counter : 1
|
|
4-bit up counter : 2
|
|
8-bit up counter : 3
|
|
# Registers : 91
|
|
1-bit register : 68
|
|
10-bit register : 1
|
|
12-bit register : 8
|
|
15-bit register : 1
|
|
16-bit register : 1
|
|
3-bit register : 5
|
|
4-bit register : 2
|
|
7-bit register : 1
|
|
8-bit register : 4
|
|
# Latches : 1
|
|
12-bit latch : 1
|
|
# Comparators : 7
|
|
12-bit comparator equal : 1
|
|
15-bit comparator greatequal : 1
|
|
15-bit comparator lessequal : 1
|
|
25-bit comparator equal : 1
|
|
4-bit comparator greatequal : 1
|
|
4-bit comparator lessequal : 1
|
|
8-bit comparator less : 1
|
|
# Multiplexers : 13
|
|
1-bit 4-to-1 multiplexer : 8
|
|
12-bit 4-to-1 multiplexer : 2
|
|
3-bit 4-to-1 multiplexer : 2
|
|
4-bit 4-to-1 multiplexer : 1
|
|
# Decoders : 1
|
|
1-of-4 decoder : 1
|
|
# Tristates : 2
|
|
16-bit tristate buffer : 2
|
|
# Xors : 1
|
|
1-bit xor2 : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Analyzing FSM <FSM_6> for best encoding.
|
|
Optimizing FSM <io/tf/db_state> on signal <db_state[1:15]> with one-hot encoding.
|
|
--------------------------
|
|
State | Encoding
|
|
--------------------------
|
|
0000 | 000000000000001
|
|
0001 | 000000000000010
|
|
0010 | 000000000000100
|
|
0011 | 000000000001000
|
|
0100 | 000000000010000
|
|
0101 | 000000001000000
|
|
0110 | 000010000000000
|
|
0111 | 000000000100000
|
|
1000 | 000100000000000
|
|
1001 | 000001000000000
|
|
1010 | 001000000000000
|
|
1011 | 010000000000000
|
|
1100 | 100000000000000
|
|
1101 | 000000100000000
|
|
1110 | 000000010000000
|
|
--------------------------
|
|
Analyzing FSM <FSM_5> for best encoding.
|
|
Optimizing FSM <io/tf/disk/ide_state> on signal <ide_state[1:23]> with one-hot encoding.
|
|
----------------------------------
|
|
State | Encoding
|
|
----------------------------------
|
|
00000 | 00000000000000000000001
|
|
00001 | 00000000000000000000010
|
|
00010 | 00000000000000000000100
|
|
00011 | 00000000000000000010000
|
|
00100 | 00000000000000000100000
|
|
00101 | 00000000000000001000000
|
|
00110 | 00000000000000010000000
|
|
00111 | 00000000000000100000000
|
|
01000 | 00000000000001000000000
|
|
01001 | 00000000000010000000000
|
|
01010 | 00000000000100000000000
|
|
01011 | 00000000010000000000000
|
|
01100 | 00000000100000000000000
|
|
01101 | 00000010000000000000000
|
|
01110 | 00000100000000000000000
|
|
01111 | 00000001000000000000000
|
|
10000 | 00010000000000000000000
|
|
10001 | 00001000000000000000000
|
|
10010 | 00100000000000000000000
|
|
10011 | 01000000000000000000000
|
|
10100 | 10000000000000000000000
|
|
10101 | 00000000000000000001000
|
|
10110 | 00000000001000000000000
|
|
----------------------------------
|
|
Analyzing FSM <FSM_4> for best encoding.
|
|
Optimizing FSM <io/tt/tti_state> on signal <tti_state[1:2]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
10 | 11
|
|
11 | 10
|
|
-------------------
|
|
Analyzing FSM <FSM_3> for best encoding.
|
|
Optimizing FSM <io/tt/tto_state> on signal <tto_state[1:2]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
10 | 11
|
|
11 | 10
|
|
-------------------
|
|
Analyzing FSM <FSM_2> for best encoding.
|
|
Optimizing FSM <io/tf/disk/ide1/ata_state> on signal <ata_state[1:3]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
000 | 000
|
|
001 | 001
|
|
010 | 011
|
|
011 | 010
|
|
100 | 110
|
|
101 | 111
|
|
-------------------
|
|
Analyzing FSM <FSM_1> for best encoding.
|
|
Optimizing FSM <io/tt/tt_uart/tx_ld> on signal <tx_ld[1:2]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
10 | 11
|
|
-------------------
|
|
Analyzing FSM <FSM_0> for best encoding.
|
|
Optimizing FSM <io/tt/tt_uart/rx_uld> on signal <rx_uld[1:2]> with gray encoding.
|
|
-------------------
|
|
State | Encoding
|
|
-------------------
|
|
00 | 00
|
|
01 | 01
|
|
10 | 11
|
|
-------------------
|
|
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
|
|
INFO:Xst:1651 - Address input of ROM <Mrom__AUX_16> is tied to register <ir>.
|
|
INFO:Xst:2502 - HDL ADVISOR - Asynchronous or synchronous initialization of this register prevents it from being combined with the ROM for implementation as read-only block RAM.
|
|
INFO:Xst:1647 - Data output of ROM <Mrom__mux0005> is tied to register <interrupt_inhibit_clear>.
|
|
INFO:Xst:2506 - In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
|
|
WARNING:Xst:1426 - The value init of the FF/Latch onetime hinder the constant cleaning in the block debounce.
|
|
You should achieve better results by setting this init to 1.
|
|
WARNING:Xst:1291 - FF/Latch <ata_out_12> is unconnected in block <ide1>.
|
|
WARNING:Xst:1291 - FF/Latch <ata_out_13> is unconnected in block <ide1>.
|
|
WARNING:Xst:1291 - FF/Latch <ata_out_14> is unconnected in block <ide1>.
|
|
WARNING:Xst:1291 - FF/Latch <ata_out_15> is unconnected in block <ide1>.
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# FSMs : 7
|
|
# RAMs : 1
|
|
256x12-bit single-port distributed RAM : 1
|
|
# ROMs : 10
|
|
16x25-bit ROM : 1
|
|
16x7-bit ROM : 1
|
|
4x1-bit ROM : 6
|
|
4x2-bit ROM : 1
|
|
8x8-bit ROM : 1
|
|
# Adders/Subtractors : 10
|
|
12-bit adder : 5
|
|
12-bit adder carry out : 2
|
|
13-bit adder : 2
|
|
4-bit adder : 1
|
|
# Counters : 15
|
|
11-bit up counter : 1
|
|
12-bit up counter : 1
|
|
13-bit up counter : 2
|
|
15-bit up counter : 1
|
|
2-bit up counter : 2
|
|
20-bit up counter : 1
|
|
25-bit up counter : 1
|
|
3-bit down counter : 1
|
|
4-bit up counter : 2
|
|
8-bit up counter : 3
|
|
# Registers : 316
|
|
Flip-Flops : 316
|
|
# Latches : 1
|
|
12-bit latch : 1
|
|
# Comparators : 7
|
|
12-bit comparator equal : 1
|
|
15-bit comparator greatequal : 1
|
|
15-bit comparator lessequal : 1
|
|
25-bit comparator equal : 1
|
|
4-bit comparator greatequal : 1
|
|
4-bit comparator lessequal : 1
|
|
8-bit comparator less : 1
|
|
# Multiplexers : 13
|
|
1-bit 4-to-1 multiplexer : 8
|
|
12-bit 4-to-1 multiplexer : 2
|
|
3-bit 4-to-1 multiplexer : 2
|
|
4-bit 4-to-1 multiplexer : 1
|
|
# Decoders : 1
|
|
1-of-4 decoder : 1
|
|
# Xors : 1
|
|
1-bit xor2 : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
INFO:Xst:2146 - In block <ide_disk>, Counter <offset> <wc> are equivalent, XST will keep only <offset>.
|
|
WARNING:Xst:1291 - FF/Latch <io/tf/disk/ide1/ata_out_12> is unconnected in block <top>.
|
|
WARNING:Xst:1291 - FF/Latch <io/tf/disk/ide1/ata_out_13> is unconnected in block <top>.
|
|
WARNING:Xst:1291 - FF/Latch <io/tf/disk/ide1/ata_out_14> is unconnected in block <top>.
|
|
WARNING:Xst:1291 - FF/Latch <io/tf/disk/ide1/ata_out_15> is unconnected in block <top>.
|
|
|
|
Optimizing unit <top> ...
|
|
|
|
Optimizing unit <pdp8> ...
|
|
|
|
Optimizing unit <pdp8_tt> ...
|
|
|
|
Optimizing unit <bootrom> ...
|
|
|
|
Optimizing unit <uart> ...
|
|
|
|
Optimizing unit <pdp8_kw> ...
|
|
|
|
Mapping all equations...
|
|
Building and optimizing final netlist ...
|
|
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 13.
|
|
FlipFlop cpu/ir_0 has been replicated 1 time(s)
|
|
FlipFlop cpu/ir_1 has been replicated 2 time(s)
|
|
FlipFlop cpu/ir_2 has been replicated 2 time(s)
|
|
FlipFlop cpu/mb_1 has been replicated 2 time(s)
|
|
FlipFlop cpu/mb_2 has been replicated 2 time(s)
|
|
FlipFlop cpu/mb_3 has been replicated 1 time(s)
|
|
FlipFlop cpu/mb_4 has been replicated 1 time(s)
|
|
FlipFlop cpu/mb_5 has been replicated 2 time(s)
|
|
FlipFlop cpu/mb_6 has been replicated 1 time(s)
|
|
FlipFlop cpu/mb_7 has been replicated 1 time(s)
|
|
FlipFlop cpu/mb_8 has been replicated 1 time(s)
|
|
FlipFlop cpu/state_0 has been replicated 4 time(s)
|
|
FlipFlop cpu/state_1 has been replicated 4 time(s)
|
|
FlipFlop cpu/state_2 has been replicated 4 time(s)
|
|
FlipFlop cpu/state_3 has been replicated 4 time(s)
|
|
FlipFlop io/tf/db_state_FFd10 has been replicated 3 time(s)
|
|
FlipFlop io/tf/db_state_FFd13 has been replicated 1 time(s)
|
|
FlipFlop io/tf/db_state_FFd14 has been replicated 2 time(s)
|
|
FlipFlop io/tf/db_state_FFd9 has been replicated 3 time(s)
|
|
FlipFlop io/tf/disk/ide_state_FFd6 has been replicated 1 time(s)
|
|
FlipFlop io/tf/disk/ide_state_FFd8 has been replicated 1 time(s)
|
|
|
|
Final Macro Processing ...
|
|
|
|
Processing Unit <top> :
|
|
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <io/tt/tt_uart/rx_d2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
|
|
Unit <top> processed.
|
|
|
|
=========================================================================
|
|
Final Register Report
|
|
|
|
Macro Statistics
|
|
# Registers : 495
|
|
Flip-Flops : 495
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : top.ngr
|
|
Top Level Output File Name : top
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : NO
|
|
|
|
Design Statistics
|
|
# IOs : 116
|
|
|
|
Cell Usage :
|
|
# BELS : 2365
|
|
# GND : 1
|
|
# INV : 26
|
|
# LUT1 : 165
|
|
# LUT2 : 133
|
|
# LUT2_D : 25
|
|
# LUT2_L : 2
|
|
# LUT3 : 249
|
|
# LUT3_D : 29
|
|
# LUT3_L : 25
|
|
# LUT4 : 987
|
|
# LUT4_D : 37
|
|
# LUT4_L : 104
|
|
# MULT_AND : 19
|
|
# MUXCY : 225
|
|
# MUXF5 : 119
|
|
# MUXF6 : 12
|
|
# VCC : 1
|
|
# XORCY : 206
|
|
# FlipFlops/Latches : 507
|
|
# FD : 38
|
|
# FDC : 30
|
|
# FDCE : 51
|
|
# FDE : 9
|
|
# FDP : 2
|
|
# FDPE : 3
|
|
# FDR : 118
|
|
# FDRE : 104
|
|
# FDRS : 112
|
|
# FDRSE : 4
|
|
# FDS : 7
|
|
# FDSE : 17
|
|
# LD : 12
|
|
# RAMS : 96
|
|
# RAM32X1S : 96
|
|
# Clock Buffers : 3
|
|
# BUFG : 2
|
|
# BUFGP : 1
|
|
# IO Buffers : 108
|
|
# IBUF : 6
|
|
# IOBUF : 24
|
|
# OBUF : 70
|
|
# OBUFT : 8
|
|
=========================================================================
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 3s1000ft256-5
|
|
|
|
Number of Slices: 1038 out of 7680 13%
|
|
Number of Slice Flip Flops: 507 out of 15360 3%
|
|
Number of 4 input LUTs: 1974 out of 15360 12%
|
|
Number used as logic: 1782
|
|
Number used as RAMs: 192
|
|
Number of IOs: 116
|
|
Number of bonded IOBs: 109 out of 173 63%
|
|
Number of GCLKs: 3 out of 8 37%
|
|
|
|
|
|
=========================================================================
|
|
TIMING REPORT
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
--------------------------------------+-----------------------------+-------+
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
--------------------------------------+-----------------------------+-------+
|
|
sysclk | BUFGP | 82 |
|
|
reset_sw/slowclk | NONE(reset_sw/hold_8) | 11 |
|
|
show_pc/aclk | NONE(show_pc/anode_0) | 2 |
|
|
clk1 | BUFG | 438 |
|
|
ram_rd(cpu/ram_rd:O) | NONE(*)(ram/rom/data_7) | 12 |
|
|
io/tt/baud_rate_generator/rx_baud_clk1| BUFG | 30 |
|
|
io/tt/baud_rate_generator/tx_baud_clk | NONE(io/tt/tt_uart/tx_cnt_2)| 16 |
|
|
io/kw/kw_src_clk | NONE(io/kw/kw_ctr_6) | 12 |
|
|
--------------------------------------+-----------------------------+-------+
|
|
(*) This 1 clock signal(s) are generated by combinatorial logic,
|
|
and XST is not able to identify which are the primary clock signals.
|
|
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
|
|
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
|
|
|
Asynchronous Control Signals Information:
|
|
----------------------------------------
|
|
-----------------------------------+---------------------------------------------+-------+
|
|
Control Signal | Buffer(FF name) | Load |
|
|
-----------------------------------+---------------------------------------------+-------+
|
|
reset(reset_sw/out28:O) | NONE(io/tt/baud_rate_generator/rx_clk_div_1)| 86 |
|
|
-----------------------------------+---------------------------------------------+-------+
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -5
|
|
|
|
Minimum period: 13.504ns (Maximum Frequency: 74.051MHz)
|
|
Minimum input arrival time before clock: 8.209ns
|
|
Maximum output required time after clock: 16.039ns
|
|
Maximum combinational path delay: No path found
|
|
|
|
Timing Detail:
|
|
--------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'sysclk'
|
|
Clock period: 6.557ns (frequency: 152.519MHz)
|
|
Total number of paths / destination ports: 1737 / 112
|
|
-------------------------------------------------------------------------
|
|
Delay: 6.557ns (Levels of Logic = 2)
|
|
Source: clk (FF)
|
|
Destination: clk (FF)
|
|
Source Clock: sysclk rising
|
|
Destination Clock: sysclk rising
|
|
|
|
Data Path: clk to clk
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDE:C->Q 1 0.626 0.681 clk (clk1)
|
|
BUFG:I->O 439 0.357 3.557 clk_BUFG (clk)
|
|
INV:I->O 1 0.479 0.681 _not00011_INV_0 (_not0001)
|
|
FDE:D 0.176 clk
|
|
----------------------------------------
|
|
Total 6.557ns (1.638ns logic, 4.919ns route)
|
|
(25.0% logic, 75.0% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'reset_sw/slowclk'
|
|
Clock period: 1.547ns (frequency: 646.224MHz)
|
|
Total number of paths / destination ports: 9 / 9
|
|
-------------------------------------------------------------------------
|
|
Delay: 1.547ns (Levels of Logic = 0)
|
|
Source: reset_sw/hold_0 (FF)
|
|
Destination: reset_sw/hold_1 (FF)
|
|
Source Clock: reset_sw/slowclk rising
|
|
Destination Clock: reset_sw/slowclk rising
|
|
|
|
Data Path: reset_sw/hold_0 to reset_sw/hold_1
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD:C->Q 2 0.626 0.745 reset_sw/hold_0 (reset_sw/hold_0)
|
|
FD:D 0.176 reset_sw/hold_1
|
|
----------------------------------------
|
|
Total 1.547ns (0.802ns logic, 0.745ns route)
|
|
(51.8% logic, 48.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'show_pc/aclk'
|
|
Clock period: 2.585ns (frequency: 386.855MHz)
|
|
Total number of paths / destination ports: 3 / 2
|
|
-------------------------------------------------------------------------
|
|
Delay: 2.585ns (Levels of Logic = 1)
|
|
Source: show_pc/anode_0 (FF)
|
|
Destination: show_pc/anode_1 (FF)
|
|
Source Clock: show_pc/aclk rising
|
|
Destination Clock: show_pc/aclk rising
|
|
|
|
Data Path: show_pc/anode_0 to show_pc/anode_1
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDR:C->Q 14 0.626 1.304 show_pc/anode_0 (show_pc/anode_0)
|
|
LUT2:I0->O 1 0.479 0.000 show_pc/anode_Madd__add0000_Mxor_Result<1>_Result1 (show_pc/anode__add0000<1>)
|
|
FD:D 0.176 show_pc/anode_1
|
|
----------------------------------------
|
|
Total 2.585ns (1.281ns logic, 1.304ns route)
|
|
(49.6% logic, 50.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'clk1'
|
|
Clock period: 13.504ns (frequency: 74.051MHz)
|
|
Total number of paths / destination ports: 210459 / 1244
|
|
-------------------------------------------------------------------------
|
|
Delay: 13.504ns (Levels of Logic = 20)
|
|
Source: cpu/ea_8 (FF)
|
|
Destination: io/tf/dma_wc_11 (FF)
|
|
Source Clock: clk1 rising
|
|
Destination Clock: clk1 rising
|
|
|
|
Data Path: cpu/ea_8 to io/tf/dma_wc_11
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDRS:C->Q 4 0.626 1.074 cpu/ea_8 (cpu/ea_8)
|
|
LUT4:I0->O 2 0.479 0.768 cpu/is_index_reg31 (cpu/is_index_reg_map3416)
|
|
LUT4:I3->O 18 0.479 1.227 cpu/is_index_reg33 (cpu/is_index_reg)
|
|
LUT4:I3->O 1 0.479 0.740 cpu/ram_addr<14>12_SW0 (N7265)
|
|
LUT4:I2->O 4 0.479 0.802 cpu/ram_addr<14>21 (ram_addr<14>)
|
|
LUT4:I3->O 1 0.479 0.740 cpu/ram_addr<10>_SW4 (N7424)
|
|
LUT4:I2->O 12 0.479 0.973 ram/rom/_and0001110 (ram/rom/_and00011_map3671)
|
|
LUT4:I3->O 3 0.479 0.000 io/tf/Madd__add0002_lut<0> (io/tf/N222)
|
|
MUXCY:S->O 1 0.435 0.000 io/tf/Madd__add0002_cy<0> (io/tf/Madd__add0002_cy<0>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<1> (io/tf/Madd__add0002_cy<1>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<2> (io/tf/Madd__add0002_cy<2>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<3> (io/tf/Madd__add0002_cy<3>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<4> (io/tf/Madd__add0002_cy<4>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<5> (io/tf/Madd__add0002_cy<5>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<6> (io/tf/Madd__add0002_cy<6>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<7> (io/tf/Madd__add0002_cy<7>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<8> (io/tf/Madd__add0002_cy<8>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<9> (io/tf/Madd__add0002_cy<9>)
|
|
MUXCY:CI->O 0 0.056 0.000 io/tf/Madd__add0002_cy<10> (io/tf/Madd__add0002_cy<10>)
|
|
XORCY:CI->O 2 0.786 0.768 io/tf/Madd__add0002_xor<11> (io/tf/_add0002<11>)
|
|
LUT4:I3->O 1 0.479 0.000 io/tf/_mux0008<11>641 (N7129)
|
|
FDRS:D 0.176 io/tf/dma_wc_11
|
|
----------------------------------------
|
|
Total 13.504ns (6.410ns logic, 7.094ns route)
|
|
(47.5% logic, 52.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'ram_rd'
|
|
Clock period: 3.610ns (frequency: 276.985MHz)
|
|
Total number of paths / destination ports: 14 / 12
|
|
-------------------------------------------------------------------------
|
|
Delay: 3.610ns (Levels of Logic = 2)
|
|
Source: ram/rom/data_3 (LATCH)
|
|
Destination: ram/rom/data_3 (LATCH)
|
|
Source Clock: ram_rd falling
|
|
Destination Clock: ram_rd falling
|
|
|
|
Data Path: ram/rom/data_3 to ram/rom/data_3
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
LD:G->Q 4 0.551 1.074 ram/rom/data_3 (ram/rom/data_3)
|
|
LUT4:I0->O 1 0.479 0.851 ram/rom/_mux0000<8>123 (ram/rom/_mux0000<8>_map1169)
|
|
LUT2:I1->O 1 0.479 0.000 ram/rom/_mux0000<8>124 (ram/rom/_mux0000<8>)
|
|
LD:D 0.176 ram/rom/data_3
|
|
----------------------------------------
|
|
Total 3.610ns (1.685ns logic, 1.925ns route)
|
|
(46.7% logic, 53.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'io/tt/baud_rate_generator/rx_baud_clk1'
|
|
Clock period: 6.319ns (frequency: 158.254MHz)
|
|
Total number of paths / destination ports: 248 / 55
|
|
-------------------------------------------------------------------------
|
|
Delay: 6.319ns (Levels of Logic = 3)
|
|
Source: io/tt/tt_uart/rx_cnt_2 (FF)
|
|
Destination: io/tt/tt_uart/rx_busy (FF)
|
|
Source Clock: io/tt/baud_rate_generator/rx_baud_clk1 rising
|
|
Destination Clock: io/tt/baud_rate_generator/rx_baud_clk1 rising
|
|
|
|
Data Path: io/tt/tt_uart/rx_cnt_2 to io/tt/tt_uart/rx_busy
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 12 0.626 1.245 io/tt/tt_uart/rx_cnt_2 (io/tt/tt_uart/rx_cnt_2)
|
|
LUT4:I0->O 3 0.479 1.066 io/tt/tt_uart/_cmp_eq00031 (io/tt/tt_uart/_cmp_eq0003)
|
|
LUT4:I0->O 1 0.479 0.740 io/tt/tt_uart/_not0028_SW0 (N1359)
|
|
LUT4:I2->O 1 0.479 0.681 io/tt/tt_uart/_not0028 (io/tt/tt_uart/_not0028)
|
|
FDCE:CE 0.524 io/tt/tt_uart/rx_busy
|
|
----------------------------------------
|
|
Total 6.319ns (2.587ns logic, 3.732ns route)
|
|
(40.9% logic, 59.1% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'io/tt/baud_rate_generator/tx_baud_clk'
|
|
Clock period: 4.443ns (frequency: 225.081MHz)
|
|
Total number of paths / destination ports: 84 / 22
|
|
-------------------------------------------------------------------------
|
|
Delay: 4.443ns (Levels of Logic = 4)
|
|
Source: io/tt/tt_uart/tx_cnt_2 (FF)
|
|
Destination: io/tt/tt_uart/tx_out (FF)
|
|
Source Clock: io/tt/baud_rate_generator/tx_baud_clk rising
|
|
Destination Clock: io/tt/baud_rate_generator/tx_baud_clk rising
|
|
|
|
Data Path: io/tt/tt_uart/tx_cnt_2 to io/tt/tt_uart/tx_out
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 9 0.626 1.250 io/tt/tt_uart/tx_cnt_2 (io/tt/tt_uart/tx_cnt_2)
|
|
LUT4:I0->O 1 0.479 0.000 io/tt/tt_uart/_mux0006129_G (N7693)
|
|
MUXF5:I1->O 2 0.314 0.804 io/tt/tt_uart/_mux0006129 (io/tt/tt_uart/_mux0006_map1445)
|
|
LUT4:I2->O 1 0.479 0.000 io/tt/tt_uart/_mux0006161_F (N7696)
|
|
MUXF5:I0->O 1 0.314 0.000 io/tt/tt_uart/_mux0006161 (io/tt/tt_uart/_mux0006)
|
|
FDPE:D 0.176 io/tt/tt_uart/tx_out
|
|
----------------------------------------
|
|
Total 4.443ns (2.388ns logic, 2.055ns route)
|
|
(53.7% logic, 46.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'io/kw/kw_src_clk'
|
|
Clock period: 4.042ns (frequency: 247.405MHz)
|
|
Total number of paths / destination ports: 78 / 12
|
|
-------------------------------------------------------------------------
|
|
Delay: 4.042ns (Levels of Logic = 12)
|
|
Source: io/kw/kw_ctr_1 (FF)
|
|
Destination: io/kw/kw_ctr_11 (FF)
|
|
Source Clock: io/kw/kw_src_clk rising
|
|
Destination Clock: io/kw/kw_src_clk rising
|
|
|
|
Data Path: io/kw/kw_ctr_1 to io/kw/kw_ctr_11
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDCE:C->Q 2 0.626 1.040 io/kw/kw_ctr_1 (io/kw/kw_ctr_1)
|
|
LUT1:I0->O 1 0.479 0.000 io/kw/kw_ctr_1_rt (io/kw/kw_ctr_1_rt)
|
|
MUXCY:S->O 1 0.435 0.000 io/kw/Mcount_kw_ctr_cy<1> (io/kw/Mcount_kw_ctr_cy<1>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<2> (io/kw/Mcount_kw_ctr_cy<2>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<3> (io/kw/Mcount_kw_ctr_cy<3>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<4> (io/kw/Mcount_kw_ctr_cy<4>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<5> (io/kw/Mcount_kw_ctr_cy<5>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<6> (io/kw/Mcount_kw_ctr_cy<6>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<7> (io/kw/Mcount_kw_ctr_cy<7>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<8> (io/kw/Mcount_kw_ctr_cy<8>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/kw/Mcount_kw_ctr_cy<9> (io/kw/Mcount_kw_ctr_cy<9>)
|
|
MUXCY:CI->O 0 0.056 0.000 io/kw/Mcount_kw_ctr_cy<10> (io/kw/Mcount_kw_ctr_cy<10>)
|
|
XORCY:CI->O 1 0.786 0.000 io/kw/Mcount_kw_ctr_xor<11> (io/kw/Result<11>)
|
|
FDCE:D 0.176 io/kw/kw_ctr_11
|
|
----------------------------------------
|
|
Total 4.042ns (3.002ns logic, 1.040ns route)
|
|
(74.3% logic, 25.7% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk'
|
|
Total number of paths / destination ports: 1690 / 26
|
|
-------------------------------------------------------------------------
|
|
Offset: 7.558ns (Levels of Logic = 15)
|
|
Source: slideswitch<2> (PAD)
|
|
Destination: clkdiv_0 (FF)
|
|
Destination Clock: sysclk rising
|
|
|
|
Data Path: slideswitch<2> to clkdiv_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 10 0.715 1.259 slideswitch_2_IBUF (slideswitch_2_IBUF)
|
|
LUT3:I0->O 5 0.479 0.953 Mrom_clkmax3 (N4)
|
|
LUT3:I1->O 1 0.479 0.000 Mcompar__cmp_eq0000_lut<1>1 (N36)
|
|
MUXCY:S->O 1 0.435 0.000 Mcompar__cmp_eq0000_cy<1> (Mcompar__cmp_eq0000_cy<1>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<2> (Mcompar__cmp_eq0000_cy<2>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<3> (Mcompar__cmp_eq0000_cy<3>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<4> (Mcompar__cmp_eq0000_cy<4>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<5> (Mcompar__cmp_eq0000_cy<5>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<6> (Mcompar__cmp_eq0000_cy<6>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<7> (Mcompar__cmp_eq0000_cy<7>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<8> (Mcompar__cmp_eq0000_cy<8>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<9> (Mcompar__cmp_eq0000_cy<9>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<10> (Mcompar__cmp_eq0000_cy<10>)
|
|
MUXCY:CI->O 1 0.056 0.000 Mcompar__cmp_eq0000_cy<11> (Mcompar__cmp_eq0000_cy<11>)
|
|
MUXCY:CI->O 26 0.246 1.546 Mcompar__cmp_eq0000_cy<12> (Mcompar__cmp_eq0000_cy<12>)
|
|
FDR:R 0.892 clkdiv_0
|
|
----------------------------------------
|
|
Total 7.558ns (3.801ns logic, 3.758ns route)
|
|
(50.3% logic, 49.7% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'reset_sw/slowclk'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 1.572ns (Levels of Logic = 1)
|
|
Source: button<3> (PAD)
|
|
Destination: reset_sw/hold_0 (FF)
|
|
Destination Clock: reset_sw/slowclk rising
|
|
|
|
Data Path: button<3> to reset_sw/hold_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 1 0.715 0.681 button_3_IBUF (button_3_IBUF)
|
|
FD:D 0.176 reset_sw/hold_0
|
|
----------------------------------------
|
|
Total 1.572ns (0.891ns logic, 0.681ns route)
|
|
(56.7% logic, 43.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1'
|
|
Total number of paths / destination ports: 549 / 81
|
|
-------------------------------------------------------------------------
|
|
Offset: 8.209ns (Levels of Logic = 18)
|
|
Source: sram1_io<0> (PAD)
|
|
Destination: io/tf/dma_wc_11 (FF)
|
|
Destination Clock: clk1 rising
|
|
|
|
Data Path: sram1_io<0> to io/tf/dma_wc_11
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IOBUF:IO->O 5 0.715 0.953 sram1_io_0_IOBUF (N7074)
|
|
LUT3:I1->O 1 0.479 0.851 ram/data_out<0>1_SW0 (N7293)
|
|
LUT4:I1->O 1 0.479 0.000 ram/rom/_and0001123_SW2_F (N7458)
|
|
MUXF5:I0->O 1 0.314 0.740 ram/rom/_and0001123_SW2 (N7332)
|
|
LUT4:I2->O 3 0.479 0.000 io/tf/Madd__add0002_lut<0> (io/tf/N222)
|
|
MUXCY:S->O 1 0.435 0.000 io/tf/Madd__add0002_cy<0> (io/tf/Madd__add0002_cy<0>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<1> (io/tf/Madd__add0002_cy<1>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<2> (io/tf/Madd__add0002_cy<2>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<3> (io/tf/Madd__add0002_cy<3>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<4> (io/tf/Madd__add0002_cy<4>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<5> (io/tf/Madd__add0002_cy<5>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<6> (io/tf/Madd__add0002_cy<6>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<7> (io/tf/Madd__add0002_cy<7>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<8> (io/tf/Madd__add0002_cy<8>)
|
|
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<9> (io/tf/Madd__add0002_cy<9>)
|
|
MUXCY:CI->O 0 0.056 0.000 io/tf/Madd__add0002_cy<10> (io/tf/Madd__add0002_cy<10>)
|
|
XORCY:CI->O 2 0.786 0.768 io/tf/Madd__add0002_xor<11> (io/tf/_add0002<11>)
|
|
LUT4:I3->O 1 0.479 0.000 io/tf/_mux0008<11>641 (N7129)
|
|
FDRS:D 0.176 io/tf/dma_wc_11
|
|
----------------------------------------
|
|
Total 8.209ns (4.897ns logic, 3.312ns route)
|
|
(59.7% logic, 40.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'io/tt/baud_rate_generator/rx_baud_clk1'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 1.572ns (Levels of Logic = 1)
|
|
Source: rs232_rxd (PAD)
|
|
Destination: io/tt/tt_uart/rx_d1 (FF)
|
|
Destination Clock: io/tt/baud_rate_generator/rx_baud_clk1 rising
|
|
|
|
Data Path: rs232_rxd to io/tt/tt_uart/rx_d1
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 1 0.715 0.681 rs232_rxd_IBUF (rs232_rxd_IBUF)
|
|
FDP:D 0.176 io/tt/tt_uart/rx_d1
|
|
----------------------------------------
|
|
Total 1.572ns (0.891ns logic, 0.681ns route)
|
|
(56.7% logic, 43.3% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1'
|
|
Total number of paths / destination ports: 8970 / 72
|
|
-------------------------------------------------------------------------
|
|
Offset: 16.039ns (Levels of Logic = 9)
|
|
Source: io/tf/db_state_FFd7 (FF)
|
|
Destination: sram1_io<0> (PAD)
|
|
Source Clock: clk1 rising
|
|
|
|
Data Path: io/tf/db_state_FFd7 to sram1_io<0>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDRS:C->Q 18 0.626 1.499 io/tf/db_state_FFd7 (io/tf/db_state_FFd7)
|
|
LUT2_D:I0->O 15 0.479 1.069 io/tf/ide_active1_1 (io/tf/ide_active1)
|
|
LUT4:I2->O 12 0.479 0.950 io/tf/buff_addr<1>1_1 (io/tf/buff_addr<1>1)
|
|
RAM32X1S:A1->O 1 0.793 0.851 io/tf/inst_Mram_mem96 (io/tf/N20)
|
|
LUT3:I1->O 1 0.479 0.000 io/tf/buff_addr<5>3 (io/tf/N51)
|
|
MUXF5:I0->O 1 0.314 0.000 io/tf/buff_addr<6>_f5_0 (io/tf/buff_addr<6>_f51)
|
|
MUXF6:I0->O 4 0.298 0.949 io/tf/inst_LPM_MUX_f6 (io/tf/buff_out<0>)
|
|
LUT4:I1->O 1 0.479 0.704 cpu/ram_data_out<0>32_SW1 (N7637)
|
|
LUT4:I3->O 1 0.479 0.681 cpu/ram_data_out<0>32 (ram_data_in<0>)
|
|
IOBUF:I->IO 4.909 sram1_io_0_IOBUF (sram1_io<0>)
|
|
----------------------------------------
|
|
Total 16.039ns (9.335ns logic, 6.704ns route)
|
|
(58.2% logic, 41.8% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'io/tt/baud_rate_generator/tx_baud_clk'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 6.280ns (Levels of Logic = 1)
|
|
Source: io/tt/tt_uart/tx_out (FF)
|
|
Destination: rs232_txd (PAD)
|
|
Source Clock: io/tt/baud_rate_generator/tx_baud_clk rising
|
|
|
|
Data Path: io/tt/tt_uart/tx_out to rs232_txd
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDPE:C->Q 2 0.626 0.745 io/tt/tt_uart/tx_out (io/tt/tt_uart/tx_out)
|
|
OBUF:I->O 4.909 rs232_txd_OBUF (rs232_txd)
|
|
----------------------------------------
|
|
Total 6.280ns (5.535ns logic, 0.745ns route)
|
|
(88.1% logic, 11.9% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'show_pc/aclk'
|
|
Total number of paths / destination ports: 74 / 12
|
|
-------------------------------------------------------------------------
|
|
Offset: 9.993ns (Levels of Logic = 4)
|
|
Source: show_pc/anode_0 (FF)
|
|
Destination: sevenseg<7> (PAD)
|
|
Source Clock: show_pc/aclk rising
|
|
|
|
Data Path: show_pc/anode_0 to sevenseg<7>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDR:C->Q 14 0.626 1.304 show_pc/anode_0 (show_pc/anode_0)
|
|
LUT3:I0->O 1 0.479 0.000 show_pc/anode<0>5 (N71)
|
|
MUXF5:I0->O 7 0.314 1.201 show_pc/Mmux_digit_f5_1 (show_pc/digit<2>)
|
|
LUT4:I0->O 1 0.479 0.681 show_pc/decode/Mrom_ss_out5 (sevenseg_5_OBUF)
|
|
OBUF:I->O 4.909 sevenseg_5_OBUF (sevenseg<5>)
|
|
----------------------------------------
|
|
Total 9.993ns (6.807ns logic, 3.186ns route)
|
|
(68.1% logic, 31.9% route)
|
|
|
|
=========================================================================
|
|
CPU : 48.75 / 49.17 s | Elapsed : 48.00 / 49.00 s
|
|
|
|
-->
|
|
|
|
Total memory usage is 186508 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 33 ( 0 filtered)
|
|
Number of infos : 13 ( 0 filtered)
|
|
|