540 lines
23 KiB
Plaintext
540 lines
23 KiB
Plaintext
Release 8.2i - xst I.31
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Parameter TMPDIR set to ./xst/projnav.tmp
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Parameter xsthdpdir set to ./xst
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Reading design: fpga.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "fpga.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "fpga"
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Output Format : NGC
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Target Device : xc2s200-5-fg256
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---- Source Options
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Top Module Name : fpga
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : lut
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100
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Add Generic Clock Buffer(BUFG) : 4
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : fpga.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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tristate2logic : Yes
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../v/scancode.v" in library work
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Compiling verilog include file "../../v/scancode_rom.v"
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Module <scancode_rom> compiled
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Compiling verilog file "../../v/fpga3.v" in library work
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Module <scancode_convert> compiled
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Module <fpga> compiled
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No errors in compilation
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Analysis of file <"fpga.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module <fpga> in library <work>.
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Analyzing hierarchy for module <scancode_convert> in library <work> with parameters.
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C_KEYRELEASE = "001000"
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C_IDLE = "000010"
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C_HOLD = "100000"
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C_INIT = "000001"
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C_KEYPRESS = "000100"
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C_RELEASE = "010000"
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Analyzing hierarchy for module <scancode_rom> in library <work>.
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module <fpga>.
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Module <fpga> is correct for synthesis.
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Analyzing module <scancode_convert> in library <work>.
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C_INIT = 6'b000001
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C_IDLE = 6'b000010
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C_KEYPRESS = 6'b000100
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C_KEYRELEASE = 6'b001000
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C_RELEASE = 6'b010000
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C_HOLD = 6'b100000
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"../../v/scancode.v" line 129: Found Full Case directive in module <scancode_convert>.
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Module <scancode_convert> is correct for synthesis.
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Analyzing module <scancode_rom> in library <work>.
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Module <scancode_rom> is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit <scancode_rom>.
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Related source file is "../../v/scancode_rom.v".
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Unit <scancode_rom> synthesized.
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Synthesizing Unit <scancode_convert>.
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Related source file is "../../v/scancode.v".
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Found finite state machine <FSM_0> for signal <state>.
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-----------------------------------------------------------------------
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| States | 6 |
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| Transitions | 13 |
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| Inputs | 7 |
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| Outputs | 6 |
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| Clock | clock (rising_edge) |
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| Reset | reset_n (negative) |
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| Reset type | asynchronous |
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| Reset State | 000001 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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WARNING:Xst:737 - Found 7-bit latch for signal <sc>.
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WARNING:Xst:737 - Found 8-bit latch for signal <ascii>.
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Found 1-bit register for signal <strobe_out>.
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Found 1-bit register for signal <key_up>.
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Found 8-bit subtractor for signal <$addsub0000> created at line 184.
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Found 1-bit register for signal <capslock>.
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Found 1-bit register for signal <ctrl>.
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Found 1-bit register for signal <release_prefix>.
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Found 1-bit register for signal <shift>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 6 D-type flip-flop(s).
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inferred 1 Adder/Subtractor(s).
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Unit <scancode_convert> synthesized.
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Synthesizing Unit <fpga>.
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Related source file is "../../v/fpga3.v".
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WARNING:Xst:647 - Input <ps2_clk> is never used.
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WARNING:Xst:647 - Input <ps2_data> is never used.
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WARNING:Xst:1306 - Output <vga_hsync_n> is never assigned.
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WARNING:Xst:1306 - Output <vga_red0> is never assigned.
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WARNING:Xst:1306 - Output <vga_red1> is never assigned.
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WARNING:Xst:1306 - Output <vga_red2> is never assigned.
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WARNING:Xst:1306 - Output <vga_green0> is never assigned.
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WARNING:Xst:1306 - Output <vga_green1> is never assigned.
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WARNING:Xst:1306 - Output <vga_green2> is never assigned.
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WARNING:Xst:647 - Input <clkb> is never used.
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WARNING:Xst:1306 - Output <vga_blue0> is never assigned.
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WARNING:Xst:1306 - Output <vga_blue1> is never assigned.
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WARNING:Xst:1306 - Output <vga_blue2> is never assigned.
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WARNING:Xst:1306 - Output <vga_vsync_n> is never assigned.
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WARNING:Xst:1780 - Signal <vsync> is never used or assigned.
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WARNING:Xst:646 - Signal <kb_ascii_rdy> is assigned but never used.
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WARNING:Xst:1780 - Signal <hsync> is never used or assigned.
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WARNING:Xst:646 - Signal <kb_release> is assigned but never used.
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WARNING:Xst:1780 - Signal <pixel> is never used or assigned.
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Found finite state machine <FSM_1> for signal <gray_cnt>.
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-----------------------------------------------------------------------
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| States | 4 |
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| Transitions | 4 |
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| Inputs | 0 |
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| Outputs | 2 |
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| Clock | clka (rising_edge) |
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| Reset | reset_n (negative) |
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| Reset type | asynchronous |
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| Reset State | 00 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 3-bit up counter for signal <clk8>.
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Found 1-bit register for signal <kb_rdy>.
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Found 8-bit up counter for signal <kb_scancode>.
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 2 Counter(s).
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inferred 1 D-type flip-flop(s).
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Unit <fpga> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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8-bit subtractor : 1
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# Counters : 2
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3-bit up counter : 1
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8-bit up counter : 1
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# Registers : 7
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1-bit register : 7
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# Latches : 2
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7-bit latch : 1
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8-bit latch : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM <FSM_1> for best encoding.
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Optimizing FSM <gray_cnt> on signal <gray_cnt[1:2]> with gray encoding.
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-------------------
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State | Encoding
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-------------------
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00 | 00
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01 | 01
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11 | 11
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10 | 10
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-------------------
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Analyzing FSM <FSM_0> for best encoding.
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Optimizing FSM <scancode_convert/state> on signal <state[1:3]> with sequential encoding.
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--------------------
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State | Encoding
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--------------------
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000001 | 000
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000010 | 001
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010000 | 010
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001000 | 011
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000100 | 100
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100000 | 101
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--------------------
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Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx.
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WARNING:Xst:1291 - FF/Latch <strobe_out> is unconnected in block <scancode_convert>.
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WARNING:Xst:1291 - FF/Latch <key_up> is unconnected in block <scancode_convert>.
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 2
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# Adders/Subtractors : 1
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8-bit subtractor : 1
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# Counters : 2
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3-bit up counter : 1
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8-bit up counter : 1
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# Registers : 12
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Flip-Flops : 12
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# Latches : 2
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7-bit latch : 1
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8-bit latch : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <fpga> ...
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Optimizing unit <scancode_convert> ...
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Optimizing unit <scancode_rom> ...
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Mapping all equations...
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WARNING:Xst:1291 - FF/Latch <scancode_convert/strobe_out> is unconnected in block <fpga>.
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WARNING:Xst:1291 - FF/Latch <scancode_convert/key_up> is unconnected in block <fpga>.
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 4.
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Final Macro Processing ...
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Processing Unit <fpga> :
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INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <gray_cnt_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
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Unit <fpga> processed.
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 21
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Flip-Flops : 21
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : fpga.ngr
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Top Level Output File Name : fpga
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : NO
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Design Statistics
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# IOs : 24
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Cell Usage :
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# BELS : 191
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# GND : 1
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# INV : 5
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# LUT1 : 7
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# LUT2 : 13
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# LUT3 : 22
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# LUT3_D : 1
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# LUT3_L : 2
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# LUT4 : 106
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# LUT4_D : 4
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# LUT4_L : 1
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# MUXCY : 7
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# MUXF5 : 14
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# VCC : 1
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# XORCY : 7
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# FlipFlops/Latches : 36
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# FDC : 5
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# FDCE : 12
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# FDE : 1
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# FDP : 3
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# LD : 8
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# LDE : 7
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# Clock Buffers : 1
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# BUFGP : 1
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# IO Buffers : 9
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# IBUF : 1
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# OBUF : 8
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 2s200fg256-5
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Number of Slices: 88 out of 2352 3%
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Number of Slice Flip Flops: 28 out of 4704 0%
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Number of 4 input LUTs: 161 out of 4704 3%
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Number of IOs: 24
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Number of bonded IOBs: 10 out of 180 5%
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IOB Flip Flops: 8
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Number of GCLKs: 1 out of 4 25%
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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----------------------------------------------------------------+----------------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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----------------------------------------------------------------+----------------------------------+-------+
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gray_cnt_FFd1 | NONE(kb_scancode_2) | 19 |
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clka | BUFGP | 2 |
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scancode_convert/strobe_out_set(scancode_convert/state_Out11:O) | NONE(*)(scancode_convert/ascii_0)| 8 |
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scancode_convert/_cmp_eq0005(scancode_convert/state_FFd1-In21:O)| NONE(*)(scancode_convert/sc_3) | 7 |
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----------------------------------------------------------------+----------------------------------+-------+
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(*) These 2 clock signal(s) are generated by combinatorial logic,
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and XST is not able to identify which are the primary clock signals.
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Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
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INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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Asynchronous Control Signals Information:
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----------------------------------------
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-------------------------------------+------------------------+-------+
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Control Signal | Buffer(FF name) | Load |
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-------------------------------------+------------------------+-------+
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clk8_Aset_inv(clk8_Aset_inv1_INV_0:O)| NONE(kb_scancode_2) | 20 |
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-------------------------------------+------------------------+-------+
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Timing Summary:
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---------------
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Speed Grade: -5
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Minimum period: 11.005ns (Maximum Frequency: 90.868MHz)
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Minimum input arrival time before clock: 3.150ns
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Maximum output required time after clock: 8.128ns
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Maximum combinational path delay: No path found
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'gray_cnt_FFd1'
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Clock period: 11.005ns (frequency: 90.868MHz)
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Total number of paths / destination ports: 260 / 31
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-------------------------------------------------------------------------
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Delay: 11.005ns (Levels of Logic = 4)
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Source: kb_scancode_2 (FF)
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Destination: scancode_convert/state_FFd3 (FF)
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Source Clock: gray_cnt_FFd1 rising
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Destination Clock: gray_cnt_FFd1 rising
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Data Path: kb_scancode_2 to scancode_convert/state_FFd3
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDCE:C->Q 8 1.292 2.050 kb_scancode_2 (kb_scancode_2)
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LUT4_D:I1->O 2 0.653 1.340 scancode_convert/_cmp_eq000211 (scancode_convert/N21)
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LUT4:I0->O 3 0.653 1.480 scancode_convert/_cmp_eq0000 (scancode_convert/_cmp_eq0000)
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MUXF5:S->O 1 0.981 1.150 scancode_convert/state_FFd3-In_SW0_SW0 (N1336)
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LUT4:I1->O 1 0.653 0.000 scancode_convert/state_FFd3-In (scancode_convert/state_FFd3-In)
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FDC:D 0.753 scancode_convert/state_FFd3
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----------------------------------------
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Total 11.005ns (4.985ns logic, 6.020ns route)
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(45.3% logic, 54.7% route)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'clka'
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Clock period: 7.048ns (frequency: 141.884MHz)
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Total number of paths / destination ports: 2 / 2
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-------------------------------------------------------------------------
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Delay: 7.048ns (Levels of Logic = 1)
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Source: gray_cnt_FFd1 (FF)
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Destination: gray_cnt_FFd2 (FF)
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Source Clock: clka rising
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Destination Clock: clka rising
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Data Path: gray_cnt_FFd1 to gray_cnt_FFd2
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDC:C->Q 20 1.292 3.200 gray_cnt_FFd1 (gray_cnt_FFd1)
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INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In)
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FDC:D 0.753 gray_cnt_FFd2
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----------------------------------------
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Total 7.048ns (2.698ns logic, 4.350ns route)
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(38.3% logic, 61.7% route)
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=========================================================================
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Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd1'
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Total number of paths / destination ports: 1 / 1
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-------------------------------------------------------------------------
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Offset: 3.150ns (Levels of Logic = 1)
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Source: reset_n (PAD)
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Destination: kb_rdy (FF)
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Destination Clock: gray_cnt_FFd1 rising
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Data Path: reset_n to kb_rdy
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 2 0.924 1.340 reset_n_IBUF (reset_n_IBUF)
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FDE:CE 0.886 kb_rdy
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----------------------------------------
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Total 3.150ns (1.810ns logic, 1.340ns route)
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(57.5% logic, 42.5% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'scancode_convert/strobe_out_set'
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Total number of paths / destination ports: 8 / 8
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-------------------------------------------------------------------------
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Offset: 8.128ns (Levels of Logic = 1)
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Source: scancode_convert/ascii_7 (LATCH)
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Destination: fpga_din_d0 (PAD)
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Source Clock: scancode_convert/strobe_out_set falling
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Data Path: scancode_convert/ascii_7 to fpga_din_d0
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
|
|
LD:G->Q 1 1.421 1.150 scancode_convert/ascii_7 (scancode_convert/ascii_7)
|
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OBUF:I->O 5.557 fpga_din_d0_OBUF (fpga_din_d0)
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----------------------------------------
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Total 8.128ns (6.978ns logic, 1.150ns route)
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(85.9% logic, 14.1% route)
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=========================================================================
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CPU : 13.09 / 13.20 s | Elapsed : 14.00 / 14.00 s
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-->
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Total memory usage is 245536 kilobytes
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|
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 25 ( 0 filtered)
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Number of infos : 2 ( 0 filtered)
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|