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Cleanup, fixes Interrupt logic, RL11 tests

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This commit is contained in:
Joerg Hoppe
2019-08-08 07:32:08 +02:00
parent 855f1a6cee
commit 313957631f
11 changed files with 954 additions and 657 deletions
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61
10.01_base/2_src/arm/unibusadapter.cpp
View File

@@ -71,7 +71,7 @@ using namespace std;
unibusadapter_c *unibusadapter; // another Singleton
// is registered in device_c.list<devices> ... order of static constructor calls ???
bool unibusadapter_debug_flag = 0 ;
bool unibusadapter_debug_flag = 0;
unibusadapter_c::unibusadapter_c() :
device_c() {
@@ -290,8 +290,8 @@ void unibusadapter_c::requests_cancel_scheduled(void) {
for (unsigned level_index = 0; level_index < PRIORITY_LEVEL_COUNT; level_index++) {
priority_request_level_c *prl = &request_levels[level_index];
prl->slot_request_mask = 0; // clear alls slot from request
prl->active = NULL ;
prl->active = NULL;
for (unsigned slot = 0; slot < PRIORITY_SLOT_COUNT; slot++)
if ((req = prl->slot_request[slot])) {
dma_request_c *dmareq;
@@ -343,9 +343,8 @@ priority_request_c *unibusadapter_c::request_activate_lowest_slot(unsigned level
// DEBUG("request_activate_lowest_slot(): ->active = dma_request %p, level %u, slot %u",prl->active, prl->active->level_index, prl->active->slot);
// else
// DEBUG("request_activate_lowest_slot(): ->active = NULL");
assert((prl->slot_request_mask == 0) == (prl->active == NULL)) ;
assert((prl->slot_request_mask == 0) == (prl->active == NULL));
return rq;
}
@@ -357,7 +356,7 @@ bool unibusadapter_c::request_is_blocking_active(uint8_t level_index) {
return true;
if (prl->slot_request_mask)
return true;
level_index++ ;
level_index++;
}
return false;
}
@@ -488,7 +487,7 @@ void unibusadapter_c::request_active_complete(unsigned level_index) {
priority_request_c *tmprq = prl->active;
prl->active = NULL;
// signal to DMA() or INTR()
tmprq->complete = true; // close to signal
pthread_mutex_unlock(&tmprq->complete_mutex);
@@ -582,7 +581,6 @@ void unibusadapter_c::INTR(intr_request_c& intr_request,
assert((intr_request.vector & 3) == 0); // multiple of 2 words
priority_request_level_c *prl = &request_levels[intr_request.level_index];
pthread_mutex_lock(&requests_mutex); // lock schedule table operations
// Is an INTR with same slot and level already executed on PRU
@@ -606,28 +604,34 @@ void unibusadapter_c::INTR(intr_request_c& intr_request,
// scheduled and request_active_complete() not called
pthread_mutex_unlock(&requests_mutex);
if (interrupt_register) {
// if device re-raises a blocked INTR, CSR must complete immediately
intr_request.device->set_register_dati_value(interrupt_register,
interrupt_register_value, __func__);
}
return; // do not schedule a 2nd time
}
intr_request.complete = false;
intr_request.executing_on_PRU = false;
// intr_request.level_index, priority_slot, vector in constructor
intr_request.interrupt_register = interrupt_register;
intr_request.interrupt_register_value = interrupt_register_value;
if (interrupt_register)
assert(intr_request.device == interrupt_register->device);
// The associated device interrupt register (if any) should be updated
// atomically with raising the INTR signal line by PRU.
//if (unibusadapter_debug_flag)
// printf("break here") ;
if (request_is_blocking_active(intr_request.level_index) && intr_request.interrupt_register) {
// one or more another requests are handled by PRU: INTR signal delayed by Arbitrator,
// write intr register asynchronically here.
intr_request.device->set_register_dati_value(intr_request.interrupt_register,
interrupt_register_value, __func__);
intr_request.interrupt_register = NULL; // don't do a 2nd time
}
// The associated device interrupt register (if any) should be updated
// atomically with raising the INTR signal line by PRU.
if (interrupt_register && request_is_blocking_active(intr_request.level_index)) {
// one or more another requests are handled by PRU: INTR signal delayed by Arbitrator,
// write intr register asynchronically here.
intr_request.device->set_register_dati_value(interrupt_register,
interrupt_register_value, __func__);
intr_request.interrupt_register = NULL; // don't do a 2nd time
} else { // forward to PRU
// intr_request.level_index, priority_slot, vector in constructor
intr_request.interrupt_register = interrupt_register;
intr_request.interrupt_register_value = interrupt_register_value;
}
// put into schedule tables
request_schedule(intr_request); // assertion, if twice for same slot
@@ -662,14 +666,14 @@ void unibusadapter_c::cancel_INTR(intr_request_c& intr_request) {
uint8_t level_index = intr_request.level_index; // alias
priority_request_level_c *prl = &request_levels[level_index];
if (prl->slot_request[intr_request.slot] == NULL)
return ; // not scheduled or active
return; // not scheduled or active
pthread_mutex_lock(&requests_mutex); // lock schedule table operations
if (&intr_request == prl->active) {
// already on PRU
mailbox_execute(ARM2PRU_INTR_CANCEL);
request_active_complete(level_index);
// restart next request
request_activate_lowest_slot(level_index);
if (prl->active)
@@ -680,7 +684,7 @@ void unibusadapter_c::cancel_INTR(intr_request_c& intr_request) {
prl->slot_request_mask &= ~(1 << intr_request.slot); // mask out slot bit
}
// both empty, or both filled
assert((prl->slot_request_mask == 0) == (prl->active == NULL)) ;
assert((prl->slot_request_mask == 0) == (prl->active == NULL));
pthread_mutex_unlock(&intr_request.complete_mutex);
pthread_mutex_unlock(&requests_mutex); // lock schedule table operations
@@ -925,11 +929,6 @@ void unibusadapter_c::worker(unsigned instance) {
any_event = true;
// at startup sequence, mailbox may be not yet valid
while (mailbox && res > 0 && any_event) { // res is const
ARM_DEBUG_PIN0(0);
ARM_DEBUG_PIN1(0);
ARM_DEBUG_PIN2(0);
any_event = false;
// Process multiple events sent by PRU.
//

103
10.02_devices/3_test/rl02/diagnostics.txt
View File

@@ -1,103 +0,0 @@
Diagnostics for RL11/RL02
Diagnostic versions are choosen by listing availability
Listing XXDP Info
ZRLG E0 x 25 RL11 controller test 1 OK 31.8. 46min
ZRLH B0 x 22 RL11 controller test 2 OK
TST 035 OP FLAG MODE
ZRLI D0 x 22 RL01/RL02 drive test 1 OK 30 min 12.9.
manual intervention test OK 13.9.
ZRLJ B0 x - RL01/RL02 drive test 2
ZRLJ B1 22 RL01/RL02 drive test 2
test1: wartet 8ms, soll 3ms - Fehler im test?
1-2x pro pass: INTR TOO LATE
11ms Verzögerung bis Ende von_after_register_access()
ZRLJ C0 25 RL01/RL02 drive test 2
17:46 -
ZRLN B0 x RL01/RL02 drive test 3 (seek & read)
A2 22
C0 X 25
ZRLK B0 x RL01/RL02 performance exerciser
B3 25
ZRLL C0 x 22 RL01/RL02 drive compatibilty test
ZRLM B0 x 22 RL01/RL02 bad sector file utility
-------------------------------
Run 21.9.:
MIT DEBUG MESSAGES
ZRLGE0: 5 Min 12 passes OK
ZRLHB1: 7 Min 5 passes OK
ZRLID1: 9 Min 3 passes OK
ZRLJC0: 16:50 HALT
3 passes, 20x INTR TOO LATE
ZRLNC0: 8 passes, 20x INTRP TOO LATE
ZRLKb3:
------------
Run 22.9.
LA OFF, DEBUG AUS:
ZRLGE0: 18095 Min 12 passes OK
ZRLHB1: 6 min 5 passes OK
ZRLID1: 10 min 3 passes 1x head switch "4 sb 5"
ZRLJC0: 7 min 2 * "intrp too late
hang mit HALT
4 passes, 1x INTR TOO LATE
ZRLNC0: 30 min 4 passes OK
ZRLKB3:
------------
Run 25.10.18
Neues PCB, langsameres reg write timing
100% RT priority, DEBUG, LA only on UNIBUS
ZRLGE0: 5 Min 14 passes OK
ZRLHB1: 8 Min 5 passes OK
ZRLID1: 12 Min 4 passes 2 ERR
2x HRD ERR 01002 SEEK SGN SWITCH TEST
ZRLJC0: 25 Min 1 pass
2x INTRPT TOO LATE
ZRLNC0: 18:12
19:45: "Eclispe: java error - remote connection to debugger closed"
29 MIn 2+passes
2x INTRPT TOO LATE
ZRLKB3: 23 Min
3 x GARBLED DATA
Running Diagnostics unter XXDP-DRS
copy xxdp.rl02 -> unibone2
Boot XXDP
.R ZRLH??
Unibone: clear error log
>>>dl c
HALT on ERROR, PRINT test numbers
DR>STA/FLA:HOE
Nur bestimmter Test:
DR>STA/FLA:HOE/TES:35
dl f <= save to bbb

630
10.02_devices/3_test/rl02/testrl11.lst
View File

@@ -15,265 +15,393 @@
15
16 165020 monitr = 165020 ; entry into M9312 monitor
17
18 ;; RL11 commands
19 000004 cmstat = 2*2 ; get status
20 000006 cmseek = 3*2 ; seek
21 000010 cmrdhd = 4*2 ; read header
22 000012 cmwrda = 5*2 ; write data
23 000014 cmrdda = 6*2 ; read data
24
18 ; RL11 commands
19 000000 cmnop = 2*0 ; no op
20 000004 cmstat = 2*2 ; get status
21 000006 cmseek = 3*2 ; seek
22 000010 cmrdhd = 4*2 ; read header
23 000012 cmwrda = 5*2 ; write data
24 000014 cmrdda = 6*2 ; read data
25
26 .asect
27
28 000160 .=160 ; addr for vector 160
29 rlvect:
30 000160 001302 .word isr ; new PC of ISR
31 000162 000340 .word 340 ; new PSW: priority is max = 7
32
26
27 .asect
28
29 000160 .=160 ; addr for vector 160
30 rlvect:
31 000160 001612 .word isr ; new PC of ISR
32 000162 000340 .word 340 ; new PSW: priority is max = 7
33
34
35 001000 .=1000
36
37 000776 stack = . - 2 ; stack grows down from start
38
39 ; --- main()
40 start:
41 001000 012706 000776 mov #stack,sp ; init stack
42 001004 012704 174400 mov #rlbase,r4 ; r4 points to RL11 register space
43
44 001010 012701 001453 mov #shello,r1
45 001014 004737 001326 call @#puts
35
36 001000 .=1000
37
38 000776 stack = . - 2 ; stack grows down from start
39
40 ; --- main()
41 start:
42 001000 012706 000776 mov #stack,sp ; init stack
43 001004 012704 174400 mov #rlbase,r4 ; r4 points to RL11 register space
44
45 001010 000005 reset
46
47 001020 004737 001030 call @#test1
48 ; call @#test2
47 001012 012701 002022 mov #shello,r1
48 001016 004737 001670 call @#puts
49
50 001024 000137 165020 jmp @#monitr
51
52
53
54 ; --- TEST1 do a "seek", like the PDP11GIUI driver does
55 test1:
56 ; wait until controller ready
57 001030 105714 0$: tstb (r4) ; wait for "controller ready" (csr.7)
58 001032 100376 bpl 0$
59
60 ; clear and get drive status
61 001034 012764 000013 000004 mov #013,da(r4) ; subcmd reset+getstatus
62 001042 012700 000004 mov #cmstat,r0
63 ; test: command acceptet dirclty aufter INIT singal
64 ; -> multiple event forwarding in ubibusadapter_c::worker()
65 001046 000005 reset
66
67 001050 010014 mov r0,(r4) ; GO
68 001052 105714 1$: tstb (r4) ; wait for "controller ready" (csr.7)
69 001054 100376 bpl 1$
70
71 ; call @#wait65 ;
72
73 ; AGAIN: clear and get drive status
74 001056 012764 000013 000004 mov #013,da(r4) ; subcmd reset+getstatus
75 001064 012700 000004 mov #cmstat,r0
76 001070 010014 mov r0,(r4) ; GO
77 001072 105714 2$: tstb (r4) ; wait for "controller ready" (csr.7)
78 001074 100376 bpl 2$
79
80 ; call @#wait65 ;
81
82 ; seek sector: read header
83 001076 012700 000010 mov #cmrdhd,r0 ; read header cmd
84 001102 010014 mov r0,(r4) ; execute
85 001104 105714 3$: tstb (r4) ; wait for "controller ready" (csr.7)
86 001106 100376 bpl 3$
87 001110 016403 000006 mov mp(r4),r3 ; retrieve cyl/head/sector
88
89 ; call @#wait65 ;
90
50 ; call @#test1
51 ; call @#test2
52 001022 004737 001302 call @#test3
53 001026 000137 165020 jmp @#monitr
54
55
56
57 ; --- TEST1 do a "seek", like the PDP11GIUI driver does
58 test1:
59 ; wait until controller ready
60 001032 105714 0$: tstb (r4) ; wait for "controller ready" (csr.7)
61 001034 100376 bpl 0$
62
63 ; clear and get drive status
64 001036 012764 000013 000004 mov #013,da(r4) ; subcmd reset+getstatus
65 001044 012700 000004 mov #cmstat,r0
66 ; test: command acceptet dirclty aufter INIT singal
67 ; -> multiple event forwarding in ubibusadapter_c::worker()
68 001050 000005 reset
69
70 001052 010014 mov r0,(r4) ; GO
71 001054 105714 1$: tstb (r4) ; wait for "controller ready" (csr.7)
72 001056 100376 bpl 1$
73
74 ; call @#wait65 ;
75
76 ; AGAIN: clear and get drive status
77 001060 012764 000013 000004 mov #013,da(r4) ; subcmd reset+getstatus
78 001066 012700 000004 mov #cmstat,r0
79 001072 010014 mov r0,(r4) ; GO
80 001074 105714 2$: tstb (r4) ; wait for "controller ready" (csr.7)
81 001076 100376 bpl 2$
82
83 ; call @#wait65 ;
84
85 ; seek sector: read header
86 001100 012700 000010 mov #cmrdhd,r0 ; read header cmd
87 001104 010014 mov r0,(r4) ; execute
88 001106 105714 3$: tstb (r4) ; wait for "controller ready" (csr.7)
89 001110 100376 bpl 3$
90 001112 016403 000006 mov mp(r4),r3 ; retrieve cyl/head/sector
91
92 ; seek ... distance = 0
93 ; assume a 0 track seek
94 001114 012764 000000 000004 mov #0,da(r4) ; clear disk address
95 001122 012700 000006 mov #cmseek,r0
96 001126 010014 mov r0,(r4) ; execute 0 track seek
97 001130 105714 4$: tstb (r4) ; wait for "controller ready" (csr.7)
98 001132 100376 bpl 4$
99
100 001134 000207 return
101
92 ; call @#wait65 ;
93
94
95 ; seek ... distance = 0
96 ; assume a 0 track seek
97 001116 012764 000000 000004 mov #0,da(r4) ; clear disk address
98 001124 012700 000006 mov #cmseek,r0
99 001130 010014 mov r0,(r4) ; execute 0 track seek
100 001132 105714 4$: tstb (r4) ; wait for "controller ready" (csr.7)
101 001134 100376 bpl 4$
102
103 ; --- TEST2 - read sector 0 into mem at 10000 and do interrupt
104 test2:
103 001136 000207 return
104
105
106 001136 005037 177776 clr @#psw ; enable all interrupt levels
107 ; wait until controller ready
108 001142 105714 0$: tstb (r4) ; wait for "controller ready" (csr.7)
109 001144 100376 bpl 0$
110
111
112 ; ; clear and get drive status
113 ; mov #013,da(r4) ; subcmd reset+getstatus
114 ; mov #cmstat,r0
115 ; mov r0,(r4) ; GO
116 ;1$: tstb (r4) ; wait for "controller ready" (csr.7)
117 ; bpl 1$
118
119
120
121 ; seek max inward , to cyl0, hd 0
122 001146 012764 177601 000004 mov #177600+1,da(r4)
123 001154 012700 000006 mov #cmseek,r0
124 001160 010014 mov r0,(r4) ; execute 0 track seek
125 001162 105714 2$: tstb (r4) ; wait for "controller ready" (csr.7)
126 001164 100376 bpl 2$
127 ; test for "drive ready"
128 001166 032714 000001 bit #1,(r4)
129 001172 001773 beq 2$
130
131 001174 012764 100000 000002 mov #buffer,ba(r4) ; setup memory address
132 001202 012764 000000 000004 mov #0,da(r4) ; disk address: cyl=0, hd=0, sec=0
133 001210 012764 177600 000006 mov #177600,mp(r4) ; load wordcount -128 = 0400
134
135 001216 005037 001300 clr @#isrcnt
136 001222 012764 000114 000000 mov #100+cmrdda,cs(r4) ; IE=1, function=6 read data
137 ; mov #cmrdda,cs(r4) ; IE=0, function=6 read data
138 ; wait for ISR
139 3$:
140 001230 005737 001300 tst @#isrcnt ; wait for ISR
141 001234 001775 beq 3$
142 ; tstb cs(r4) ; wait for CRDY
143 ; bpl 3$
144
145 001236 012701 001476 mov #sba,r1 ; "BA="
146 001242 004737 001326 call @#puts
147 001246 016400 000002 mov ba(r4),r0
148 001252 004737 001362 call @#putnum ; content of BA register
149 001256 012701 001450 mov #scrlf,r1 ; end of line
150 001262 004737 001326 call @#puts
151
152
153 001266 012701 001502 mov #sready,r1 ; print "READY"
154 001272 004737 001326 call @#puts
155 001276 000207 return
156
157
158
159 ; --------------
160 ; --- isr - called on interupt
161 ; print incremented BA ... is DMA really ready?
162 001300 000000 isrcnt: .word ; flag: ISR hit
163 isr:
164 001302 005237 001300 inc @#isrcnt ; signal "done"
165 001306 000002 rti
166
167
106 ; --- TEST2 - read sector 0 into mem at 10000 and do interrupt
107 test2:
108
109 001140 005037 177776 clr @#psw ; enable all interrupt levels
110 ; wait until controller ready
111 001144 105714 0$: tstb (r4) ; wait for "controller ready" (csr.7)
112 001146 100376 bpl 0$
113
114
115 ; ; clear and get drive status
116 ; mov #013,da(r4) ; subcmd reset+getstatus
117 ; mov #cmstat,r0
118 ; mov r0,(r4) ; GO
119 ;1$: tstb (r4) ; wait for "controller ready" (csr.7)
120 ; bpl 1$
121
122
123
124 ; seek max inward , to cyl0, hd 0
125 001150 012764 177601 000004 mov #177600+1,da(r4)
126 001156 012700 000006 mov #cmseek,r0
127 001162 010014 mov r0,(r4) ; execute 0 track seek
128 001164 105714 2$: tstb (r4) ; wait for "controller ready" (csr.7)
129 001166 100376 bpl 2$
130 ; test for "drive ready"
131 001170 032714 000001 bit #1,(r4)
132 001174 001773 beq 2$
133
134 001176 012764 100000 000002 mov #buffer,ba(r4) ; setup memory address
135 001204 012764 000000 000004 mov #0,da(r4) ; disk address: cyl=0, hd=0, sec=0
136 001212 012764 177600 000006 mov #177600,mp(r4) ; load wordcount -128 = 0400
137
138 001220 005037 001610 clr @#isrcnt
139 001224 012764 000114 000000 mov #100+cmrdda,cs(r4) ; IE=1, function=6 read data
140 ; mov #cmrdda,cs(r4) ; IE=0, function=6 read data
141 ; wait for ISR
142 3$:
143 001232 005737 001610 tst @#isrcnt ; wait for ISR
144 001236 001775 beq 3$
145 ; tstb cs(r4) ; wait for CRDY
146 ; bpl 3$
147
148 001240 012701 002052 mov #sba,r1 ; "BA="
149 001244 004737 001670 call @#puts
150 001250 016400 000002 mov ba(r4),r0
151 001254 004737 001724 call @#putnum ; content of BA register
152 001260 012701 002047 mov #scrlf,r1 ; end of line
153 001264 004737 001670 call @#puts
154
155
156 001270 012701 002056 mov #sready,r1 ; print "READY"
157 001274 004737 001670 call @#puts
158 001300 000207 return
159
160
161 ; --- TEST3 - ZRLG test 24
162 ; execute NOP with Interrupt, with multiple CPU intr levels
163 ; INTR accepted for level 5 and 4
164 test3:
165 001302 005037 001610 clr @#isrcnt
166 ; mov #1,r0 ; idle: expected CRDY and not INTR
167 ; call @#test3b
168
169
170 ; -- wait 65ms, uses r0
171 wait65:
172 001310 005000 clr r0
173 0$:
174 001312 077001 sob r0,0$ : subtract one, loop until zero
175 001314 000207 return
176
177
178 ; --- check for error
179 chkerr:
180 ; verify controller ready
181 001316 105714 0$: tstb (r4) ; wait for "controller ready" (csr.7)
182 001320 100376 bpl 0$ ;
169 001306 012737 000340 177776 mov #340,@#psw ; level 7
170 001314 004737 001462 call @#test3a ; NOP
171 001320 012700 000001 mov #1,r0 ; expected CRDY and not INTR
172 001324 004737 001476 call @#test3b
173
174 001330 012737 000300 177776 mov #300,@#psw ; level 6
175 001336 004737 001462 call @#test3a ; NOP
176 001342 012700 000001 mov #1,r0 ; expected CRDY and not INTR
177 001346 004737 001476 call @#test3b
178
179 001352 012737 000240 177776 mov #240,@#psw ; level 5
180 001360 004737 001462 call @#test3a ; NOP
181 001364 012700 000001 mov #1,r0 ; expected CRDY and not INTR
182 001370 004737 001476 call @#test3b
183
184 001322 011400 mov (r4),r0 ; return status CSR
185 ; bic #1777,r0 ; ignore bits 9:0, error flags are in 15:10
186 ; bne 1$
187 ; clc
188 001324 000207 return ; CSR = R1 = 0: no error
189
190
191 ; ----------------------
192 ; puts - print a string
193 ; r1 = pointer, r0,r1 changed
194 puts:
195 001326 112100 movb (r1)+,r0 ; load xmt char
196 001330 001403 beq 1$ ; string ends with 0
197 001332 004737 001434 call @#putc
198 001336 000773 br puts ; transmit nxt char of string
199 001340 000207 1$: return
184 001374 012737 000200 177776 mov #200,@#psw ; level 4, below BR5, pending triggered
185 001402 012700 000003 mov #3,r0 ; expected CRDY and INTR
186 001406 004737 001476 call @#test3b
187
188 001412 005037 001610 clr @#isrcnt
189 001416 004737 001462 call @#test3a ; NOP at level 4
190 001422 012700 000003 mov #3,r0 ; expected CRDY and INTR
191 001426 004737 001476 call @#test3b
192
193 001432 005037 001610 clr @#isrcnt
194 001436 012737 000000 177776 mov #0,@#psw ; level 0
195 001444 004737 001462 call @#test3a ; NOP
196 001450 012700 000003 mov #3,r0 ; expected CRDY and INTR
197 001454 004737 001476 call @#test3b
198 001460 000207 return
199
200
201
202 ; ----------------------
203 ; putnum - print the octal number in r0
204 001342 numbf0: .blkw 10 ; space to mount number string
205 001362 numbf1 =.
206 putnum:
207 001362 010002 mov r0,r2 ; r2 = shifter
208 001364 012701 001362 mov #numbf1,r1 ; r1 = buffer pointer, backwards
209 001370 112741 000000 movb #0,-(r1) ; set terminating 0
210 ; repeat 6 times
211 001374 012703 000006 mov #6,r3
212 1$:
213 001400 010200 mov r2,r0
214 ; extract lower 3 bits = octal digit
215 001402 042700 177770 bic #177770,r0 ; r0 &= 0x07
216 001406 062700 000060 add #60,r0 ; r0 += '0'
217 001412 110041 movb r0,-(r1) ; write in buffer
218 001414 000241 clc
219 001416 006002 ror r2 ; shift to next digit
220 001420 006002 ror r2
221 001422 006002 ror r2
222 001424 077313 sob r3,1$ ; loop for all 6 digits
223
224 001426 004737 001326 call @#puts
225 001432 000207 return
226
227
228 ; DEC DL11 console I/O
229 ; ----------------------
230 ; putc - output a single char
231 ; r0 = char
232 putc:
233 001434 110037 177566 movb r0,@#dladr+6 ; char into transmit buffer
234 001440 105737 177564 1$: tstb @#dladr+4 ; XMT RDY?
235 001444 100375 bpl 1$ ; no, loop
236 001446 000207 return
237
238
239 ; --- string constants
240 001450 015 012 scrlf: .byte 15,12 ; CR, LF,
241 001452 000 .byte 0
242
243
244 shello:
245 001453 015 012 .byte 15,12 ; CR, LF,
246 001455 123 164 141 .ascii /Starting test!/
001460 162 164 151
001463 156 147 040
001466 164 145 163
001471 164 041
247 001473 015 012 .byte 15,12 ; CR, LF,
248 001475 000 .byte 0
249
250 001476 102 101 075 sba: .ascii /BA=/
251 001501 000 .byte 0 ; NUL=end marker
252
253 001502 123 145 143 sready: .ascii /Sector 0 transfered to 100000, ISR hit./
001505 164 157 162
001510 040 060 040
001513 164 162 141
001516 156 163 146
001521 145 162 145
001524 144 040 164
001527 157 040 061
001532 060 060 060
001535 060 060 054
001540 040 111 123
001543 122 040 150
001546 151 164 056
254 001551 015 012 .byte 15,12 ; CR, LF,
255 001553 000 .byte 0
256
257 ; ---- 32kb page
258 100000 . = 100000
259 buffer:
260 .end ;
261
262 .end
262
201 ; send NOP cmd and wait for crdy
202 test3a:
203 ; pending interupt condition not cleared
204 001462 005037 001610 clr @#isrcnt
205 001466 012700 000100 mov #cmnop!100,r0 ; nop with Interrupt Enable
206 001472 010014 mov r0,(r4) ; NOOP
207 001474 000207 return
208
209 ; check CRDY and ISR
210 ; r0: expected result
211 ; 0 = neither ISR nor CRDY
212 ; 1 = CRDY without ISR
213 ; 2 = ISR without CRDY
214 ; 3 = ISR and CRDY
215 test3b:
216 001476 010046 mov r0,-(sp) ; push
217 ; pending interupt condition not cleared
218 001500 005003 clr r3 ; result
219 001502 012700 001750 mov #1750,r0 ; wait 1000us for ISR and CRDY
220 001506 004737 001620 call @#wtcrdy
221 001512 103402 bcs 1$
222 001514 052703 000001 bis #1,r3 ; Carry clear = NO timeout: CRDY r3 = 1
223 1$:
224 001520 005737 001610 tst @#isrcnt
225 001524 001402 beq 2$
226 001526 052703 000002 bis #2,r3 ; ISR detected: result |= 2
227 2$:
228 001532 012602 mov (sp)+,r2 ; pop
229 ; r2 = crd+isr code as expected, r3 = as measured
230 001534 020203 cmp r2,r3
231 001536 001401 beq 3$
232 001540 000000 halt
233 3$:
234 ; print "CRDY+ISR = ..., expected ....
235 001542 012701 002130 mov #scrdy1,r1 ; "CRDY+ISR ="
236 001546 004737 001670 call @#puts
237 001552 010300 mov r3,r0
238 001554 004737 001724 call @#putnum
239 001560 012701 002144 mov #scrdy2,r1 ; "expected"
240 001564 004737 001670 call @#puts
241 001570 010200 mov r2,r0
242 001572 004737 001724 call @#putnum
243 001576 012701 002047 mov #scrlf,r1 ; print end of line
244 001602 004737 001670 call @#puts
245 001606 000207 return
246
247
248 ; --------------
249 ; --- isr - called on interupt
250 ; print incremented BA ... is DMA really ready?
251 001610 000000 isrcnt: .word ; flag: ISR hit
252 isr:
253 001612 005237 001610 inc @#isrcnt ; signal "done"
254 001616 000002 rti
255
256 ; - wait for "controller ready", but max r0 microseconds
257 ; result: carry clear = OK,
258 ; carry set = timeout
259
260 wtcrdy:
261 001620 006200 asr r0 ; wait loop is 4 cycles
262 001622 006200 asr r0
263 1$:
264 001624 105714 tstb (r4) ; 2 cycles
265 001626 100403 bmi 9$ ; bit 7 set -> controller ready
266 001630 077003 sob r0,1$
267
268 001632 000261 sec ; "timeout"
269 001634 000207 return
270 9$:
271 001636 000241 clc ; "OK"
272 001640 000207 return
273
274
275 ; -- wait 65ms, uses r0
276 wait65:
277 001642 005000 clr r0
278 0$:
279 001644 077001 sob r0,0$ : subtract one, loop until zero
280 001646 000207 return
281
282 ; -- wait 1ms, uses r0
283 wait1:
284 001650 012700 001750 mov #1750,r0 ; 1000 us
285 0$:
286 001654 077001 sob r0,0$ : subtract one, loop until zero
287 001656 000207 return
288
289
290 ; --- check for error
291 chkerr:
292 ; verify controller ready
293 001660 105714 0$: tstb (r4) ; wait for "controller ready" (csr.7)
294 001662 100376 bpl 0$ ;
295
296 001664 011400 mov (r4),r0 ; return status CSR
297 ; bic #1777,r0 ; ignore bits 9:0, error flags are in 15:10
298 ; bne 1$
299 ; clc
300 001666 000207 return ; CSR = R1 = 0: no error
301
302
303 ; ----------------------
304 ; puts - print a string
305 ; r1 = pointer, r0,r1 changed
306 puts:
307 001670 112100 movb (r1)+,r0 ; load xmt char
308 001672 001403 beq 1$ ; string ends with 0
309 001674 004737 002006 call @#putc
310 001700 000773 br puts ; transmit nxt char of string
311 001702 000207 1$: return
312
313
314 ; ----------------------
315 ; putnum - print the octal number in r0
316 001704 numbf0: .blkw 10 ; space to mount number string
317 001724 numbf1 =.
318 putnum:
319 001724 010246 mov r2,-(sp)
320 001726 010346 mov r3,-(sp)
321 001730 010002 mov r0,r2 ; r2 = shifter
322 001732 012701 001724 mov #numbf1,r1 ; r1 = buffer pointer, backwards
323 001736 112741 000000 movb #0,-(r1) ; set terminating 0
324 ; repeat 6 times
325 001742 012703 000006 mov #6,r3
326 1$:
327 001746 010200 mov r2,r0
328 ; extract lower 3 bits = octal digit
329 001750 042700 177770 bic #177770,r0 ; r0 &= 0x07
330 001754 062700 000060 add #60,r0 ; r0 += '0'
331 001760 110041 movb r0,-(r1) ; write in buffer
332 001762 000241 clc
333 001764 006202 asr r2 ; shift to next digit
334 001766 006202 asr r2
335 001770 006202 asr r2
336 001772 077313 sob r3,1$ ; loop for all 6 digits
337
338 001774 004737 001670 call @#puts
339 002000 012603 mov (sp)+,r3
340 002002 012602 mov (sp)+,r2
341 002004 000207 return
342
343
344 ; DEC DL11 console I/O
345 ; ----------------------
346 ; putc - output a single char
347 ; r0 = char
348 putc:
349 002006 110037 177566 movb r0,@#dladr+6 ; char into transmit buffer
350 002012 105737 177564 1$: tstb @#dladr+4 ; XMT RDY?
351 002016 100375 bpl 1$ ; no, loop
352 002020 000207 return
353
354
355 ; --- string constants
356 shello:
357 002022 015 012 .byte 15,12 ; CR, LF,
358 002024 123 164 141 .ascii /Starting RL11 test!/
002027 162 164 151
002032 156 147 040
002035 122 114 061
002040 061 040 164
002043 145 163 164
002046 041
359 scrlf:
360 002047 015 012 .byte 15,12 ; CR, LF,
361 002051 000 .byte 0
362
363 002052 102 101 075 sba: .ascii /BA=/
364 002055 000 .byte 0 ; NUL=end marker
365
366 002056 123 145 143 sready: .ascii /Sector 0 transfered to 100000, ISR hit./
002061 164 157 162
002064 040 060 040
002067 164 162 141
002072 156 163 146
002075 145 162 145
002100 144 040 164
002103 157 040 061
002106 060 060 060
002111 060 060 054
002114 040 111 123
002117 122 040 150
002122 151 164 056
367 002125 015 012 .byte 15,12 ; CR, LF,
368 002127 000 .byte 0
369
370
371 002130 103 122 104 scrdy1: .ascii /CRDY+ISR = /
002133 131 053 111
002136 123 122 040
002141 075 040
372 002143 000 .byte 0
373 002144 054 040 145 scrdy2: .ascii /, expected /
002147 170 160 145
002152 143 164 145
002155 144 040
374 002157 000 .byte 0
375
376
377 ; ---- 32kb page
378 100000 . = 100000
379 buffer:
380 .end ;
381
382 .end
382

630
10.02_devices/3_test/rl02/testrl11.lst.hex
View File

@@ -15,265 +15,393 @@
15
16 EA10h monitr = 165020 ; entry into M9312 monitor
17
18 ;; RL11 commands
19 0004h cmstat = 2*2 ; get status
20 0006h cmseek = 3*2 ; seek
21 0008h cmrdhd = 4*2 ; read header
22 000Ah cmwrda = 5*2 ; write data
23 000Ch cmrdda = 6*2 ; read data
24
18 ; RL11 commands
19 0000h cmnop = 2*0 ; no op
20 0004h cmstat = 2*2 ; get status
21 0006h cmseek = 3*2 ; seek
22 0008h cmrdhd = 4*2 ; read header
23 000Ah cmwrda = 5*2 ; write data
24 000Ch cmrdda = 6*2 ; read data
25
26 .asect
27
28 0070h .=160 ; addr for vector 160
29 rlvect:
30 0070h 02C2h .word isr ; new PC of ISR
31 0072h 00E0h .word 340 ; new PSW: priority is max = 7
32
26
27 .asect
28
29 0070h .=160 ; addr for vector 160
30 rlvect:
31 0070h 038Ah .word isr ; new PC of ISR
32 0072h 00E0h .word 340 ; new PSW: priority is max = 7
33
34
35 0200h .=1000
36
37 01FEh stack = . - 2 ; stack grows down from start
38
39 ; --- main()
40 start:
41 0200h 15C6h 01FEh mov #stack,sp ; init stack
42 0204h 15C4h F900h mov #rlbase,r4 ; r4 points to RL11 register space
43
44 0208h 15C1h 032Bh mov #shello,r1
45 020Ch 09DFh 02D6h call @#puts
35
36 0200h .=1000
37
38 01FEh stack = . - 2 ; stack grows down from start
39
40 ; --- main()
41 start:
42 0200h 15C6h 01FEh mov #stack,sp ; init stack
43 0204h 15C4h F900h mov #rlbase,r4 ; r4 points to RL11 register space
44
45 0208h 0005h reset
46
47 0210h 09DFh 0218h call @#test1
48 ; call @#test2
47 020Ah 15C1h 0412h mov #shello,r1
48 020Eh 09DFh 03B8h call @#puts
49
50 0214h 005Fh EA10h jmp @#monitr
51
52
53
54 ; --- TEST1 do a "seek", like the PDP11GIUI driver does
55 test1:
56 ; wait until controller ready
57 0218h 8BCCh 0$: tstb (r4) ; wait for "controller ready" (csr.7)
58 021Ah 80FEh bpl 0$
59
60 ; clear and get drive status
61 021Ch 15F4h 000Bh 0004h mov #013,da(r4) ; subcmd reset+getstatus
62 0222h 15C0h 0004h mov #cmstat,r0
63 ; test: command acceptet dirclty aufter INIT singal
64 ; -> multiple event forwarding in ubibusadapter_c::worker()
65 0226h 0005h reset
66
67 0228h 100Ch mov r0,(r4) ; GO
68 022Ah 8BCCh 1$: tstb (r4) ; wait for "controller ready" (csr.7)
69 022Ch 80FEh bpl 1$
70
71 ; call @#wait65 ;
72
73 ; AGAIN: clear and get drive status
74 022Eh 15F4h 000Bh 0004h mov #013,da(r4) ; subcmd reset+getstatus
75 0234h 15C0h 0004h mov #cmstat,r0
76 0238h 100Ch mov r0,(r4) ; GO
77 023Ah 8BCCh 2$: tstb (r4) ; wait for "controller ready" (csr.7)
78 023Ch 80FEh bpl 2$
79
80 ; call @#wait65 ;
81
82 ; seek sector: read header
83 023Eh 15C0h 0008h mov #cmrdhd,r0 ; read header cmd
84 0242h 100Ch mov r0,(r4) ; execute
85 0244h 8BCCh 3$: tstb (r4) ; wait for "controller ready" (csr.7)
86 0246h 80FEh bpl 3$
87 0248h 1D03h 0006h mov mp(r4),r3 ; retrieve cyl/head/sector
88
89 ; call @#wait65 ;
90
50 ; call @#test1
51 ; call @#test2
52 0212h 09DFh 02C2h call @#test3
53 0216h 005Fh EA10h jmp @#monitr
54
55
56
57 ; --- TEST1 do a "seek", like the PDP11GIUI driver does
58 test1:
59 ; wait until controller ready
60 021Ah 8BCCh 0$: tstb (r4) ; wait for "controller ready" (csr.7)
61 021Ch 80FEh bpl 0$
62
63 ; clear and get drive status
64 021Eh 15F4h 000Bh 0004h mov #013,da(r4) ; subcmd reset+getstatus
65 0224h 15C0h 0004h mov #cmstat,r0
66 ; test: command acceptet dirclty aufter INIT singal
67 ; -> multiple event forwarding in ubibusadapter_c::worker()
68 0228h 0005h reset
69
70 022Ah 100Ch mov r0,(r4) ; GO
71 022Ch 8BCCh 1$: tstb (r4) ; wait for "controller ready" (csr.7)
72 022Eh 80FEh bpl 1$
73
74 ; call @#wait65 ;
75
76 ; AGAIN: clear and get drive status
77 0230h 15F4h 000Bh 0004h mov #013,da(r4) ; subcmd reset+getstatus
78 0236h 15C0h 0004h mov #cmstat,r0
79 023Ah 100Ch mov r0,(r4) ; GO
80 023Ch 8BCCh 2$: tstb (r4) ; wait for "controller ready" (csr.7)
81 023Eh 80FEh bpl 2$
82
83 ; call @#wait65 ;
84
85 ; seek sector: read header
86 0240h 15C0h 0008h mov #cmrdhd,r0 ; read header cmd
87 0244h 100Ch mov r0,(r4) ; execute
88 0246h 8BCCh 3$: tstb (r4) ; wait for "controller ready" (csr.7)
89 0248h 80FEh bpl 3$
90 024Ah 1D03h 0006h mov mp(r4),r3 ; retrieve cyl/head/sector
91
92 ; seek ... distance = 0
93 ; assume a 0 track seek
94 024Ch 15F4h 0000h 0004h mov #0,da(r4) ; clear disk address
95 0252h 15C0h 0006h mov #cmseek,r0
96 0256h 100Ch mov r0,(r4) ; execute 0 track seek
97 0258h 8BCCh 4$: tstb (r4) ; wait for "controller ready" (csr.7)
98 025Ah 80FEh bpl 4$
99
100 025Ch 0087h return
101
92 ; call @#wait65 ;
93
94
95 ; seek ... distance = 0
96 ; assume a 0 track seek
97 024Eh 15F4h 0000h 0004h mov #0,da(r4) ; clear disk address
98 0254h 15C0h 0006h mov #cmseek,r0
99 0258h 100Ch mov r0,(r4) ; execute 0 track seek
100 025Ah 8BCCh 4$: tstb (r4) ; wait for "controller ready" (csr.7)
101 025Ch 80FEh bpl 4$
102
103 ; --- TEST2 - read sector 0 into mem at 10000 and do interrupt
104 test2:
103 025Eh 0087h return
104
105
106 025Eh 0A1Fh FFFEh clr @#psw ; enable all interrupt levels
107 ; wait until controller ready
108 0262h 8BCCh 0$: tstb (r4) ; wait for "controller ready" (csr.7)
109 0264h 80FEh bpl 0$
110
111
112 ; ; clear and get drive status
113 ; mov #013,da(r4) ; subcmd reset+getstatus
114 ; mov #cmstat,r0
115 ; mov r0,(r4) ; GO
116 ;1$: tstb (r4) ; wait for "controller ready" (csr.7)
117 ; bpl 1$
118
119
120
121 ; seek max inward , to cyl0, hd 0
122 0266h 15F4h FF81h 0004h mov #177600+1,da(r4)
123 026Ch 15C0h 0006h mov #cmseek,r0
124 0270h 100Ch mov r0,(r4) ; execute 0 track seek
125 0272h 8BCCh 2$: tstb (r4) ; wait for "controller ready" (csr.7)
126 0274h 80FEh bpl 2$
127 ; test for "drive ready"
128 0276h 35CCh 0001h bit #1,(r4)
129 027Ah 03FBh beq 2$
130
131 027Ch 15F4h 8000h 0002h mov #buffer,ba(r4) ; setup memory address
132 0282h 15F4h 0000h 0004h mov #0,da(r4) ; disk address: cyl=0, hd=0, sec=0
133 0288h 15F4h FF80h 0006h mov #177600,mp(r4) ; load wordcount -128 = 0400
134
135 028Eh 0A1Fh 02C0h clr @#isrcnt
136 0292h 15F4h 004Ch 0000h mov #100+cmrdda,cs(r4) ; IE=1, function=6 read data
137 ; mov #cmrdda,cs(r4) ; IE=0, function=6 read data
138 ; wait for ISR
139 3$:
140 0298h 0BDFh 02C0h tst @#isrcnt ; wait for ISR
141 029Ch 03FDh beq 3$
142 ; tstb cs(r4) ; wait for CRDY
143 ; bpl 3$
144
145 029Eh 15C1h 033Eh mov #sba,r1 ; "BA="
146 02A2h 09DFh 02D6h call @#puts
147 02A6h 1D00h 0002h mov ba(r4),r0
148 02AAh 09DFh 02F2h call @#putnum ; content of BA register
149 02AEh 15C1h 0328h mov #scrlf,r1 ; end of line
150 02B2h 09DFh 02D6h call @#puts
151
152
153 02B6h 15C1h 0342h mov #sready,r1 ; print "READY"
154 02BAh 09DFh 02D6h call @#puts
155 02BEh 0087h return
156
157
158
159 ; --------------
160 ; --- isr - called on interupt
161 ; print incremented BA ... is DMA really ready?
162 02C0h 0000h isrcnt: .word ; flag: ISR hit
163 isr:
164 02C2h 0A9Fh 02C0h inc @#isrcnt ; signal "done"
165 02C6h 0002h rti
166
167
106 ; --- TEST2 - read sector 0 into mem at 10000 and do interrupt
107 test2:
108
109 0260h 0A1Fh FFFEh clr @#psw ; enable all interrupt levels
110 ; wait until controller ready
111 0264h 8BCCh 0$: tstb (r4) ; wait for "controller ready" (csr.7)
112 0266h 80FEh bpl 0$
113
114
115 ; ; clear and get drive status
116 ; mov #013,da(r4) ; subcmd reset+getstatus
117 ; mov #cmstat,r0
118 ; mov r0,(r4) ; GO
119 ;1$: tstb (r4) ; wait for "controller ready" (csr.7)
120 ; bpl 1$
121
122
123
124 ; seek max inward , to cyl0, hd 0
125 0268h 15F4h FF81h 0004h mov #177600+1,da(r4)
126 026Eh 15C0h 0006h mov #cmseek,r0
127 0272h 100Ch mov r0,(r4) ; execute 0 track seek
128 0274h 8BCCh 2$: tstb (r4) ; wait for "controller ready" (csr.7)
129 0276h 80FEh bpl 2$
130 ; test for "drive ready"
131 0278h 35CCh 0001h bit #1,(r4)
132 027Ch 03FBh beq 2$
133
134 027Eh 15F4h 8000h 0002h mov #buffer,ba(r4) ; setup memory address
135 0284h 15F4h 0000h 0004h mov #0,da(r4) ; disk address: cyl=0, hd=0, sec=0
136 028Ah 15F4h FF80h 0006h mov #177600,mp(r4) ; load wordcount -128 = 0400
137
138 0290h 0A1Fh 0388h clr @#isrcnt
139 0294h 15F4h 004Ch 0000h mov #100+cmrdda,cs(r4) ; IE=1, function=6 read data
140 ; mov #cmrdda,cs(r4) ; IE=0, function=6 read data
141 ; wait for ISR
142 3$:
143 029Ah 0BDFh 0388h tst @#isrcnt ; wait for ISR
144 029Eh 03FDh beq 3$
145 ; tstb cs(r4) ; wait for CRDY
146 ; bpl 3$
147
148 02A0h 15C1h 042Ah mov #sba,r1 ; "BA="
149 02A4h 09DFh 03B8h call @#puts
150 02A8h 1D00h 0002h mov ba(r4),r0
151 02ACh 09DFh 03D4h call @#putnum ; content of BA register
152 02B0h 15C1h 0427h mov #scrlf,r1 ; end of line
153 02B4h 09DFh 03B8h call @#puts
154
155
156 02B8h 15C1h 042Eh mov #sready,r1 ; print "READY"
157 02BCh 09DFh 03B8h call @#puts
158 02C0h 0087h return
159
160
161 ; --- TEST3 - ZRLG test 24
162 ; execute NOP with Interrupt, with multiple CPU intr levels
163 ; INTR accepted for level 5 and 4
164 test3:
165 02C2h 0A1Fh 0388h clr @#isrcnt
166 ; mov #1,r0 ; idle: expected CRDY and not INTR
167 ; call @#test3b
168
169
170 ; -- wait 65ms, uses r0
171 wait65:
172 02C8h 0A00h clr r0
173 0$:
174 02CAh 7E01h sob r0,0$ : subtract one, loop until zero
175 02CCh 0087h return
176
177
178 ; --- check for error
179 chkerr:
180 ; verify controller ready
181 02CEh 8BCCh 0$: tstb (r4) ; wait for "controller ready" (csr.7)
182 02D0h 80FEh bpl 0$ ;
169 02C6h 15DFh 00E0h FFFEh mov #340,@#psw ; level 7
170 02CCh 09DFh 0332h call @#test3a ; NOP
171 02D0h 15C0h 0001h mov #1,r0 ; expected CRDY and not INTR
172 02D4h 09DFh 033Eh call @#test3b
173
174 02D8h 15DFh 00C0h FFFEh mov #300,@#psw ; level 6
175 02DEh 09DFh 0332h call @#test3a ; NOP
176 02E2h 15C0h 0001h mov #1,r0 ; expected CRDY and not INTR
177 02E6h 09DFh 033Eh call @#test3b
178
179 02EAh 15DFh 00A0h FFFEh mov #240,@#psw ; level 5
180 02F0h 09DFh 0332h call @#test3a ; NOP
181 02F4h 15C0h 0001h mov #1,r0 ; expected CRDY and not INTR
182 02F8h 09DFh 033Eh call @#test3b
183
184 02D2h 1300h mov (r4),r0 ; return status CSR
185 ; bic #1777,r0 ; ignore bits 9:0, error flags are in 15:10
186 ; bne 1$
187 ; clc
188 02D4h 0087h return ; CSR = R1 = 0: no error
189
190
191 ; ----------------------
192 ; puts - print a string
193 ; r1 = pointer, r0,r1 changed
194 puts:
195 02D6h 9440h movb (r1)+,r0 ; load xmt char
196 02D8h 0303h beq 1$ ; string ends with 0
197 02DAh 09DFh 031Ch call @#putc
198 02DEh 01FBh br puts ; transmit nxt char of string
199 02E0h 0087h 1$: return
184 02FCh 15DFh 0080h FFFEh mov #200,@#psw ; level 4, below BR5, pending triggered
185 0302h 15C0h 0003h mov #3,r0 ; expected CRDY and INTR
186 0306h 09DFh 033Eh call @#test3b
187
188 030Ah 0A1Fh 0388h clr @#isrcnt
189 030Eh 09DFh 0332h call @#test3a ; NOP at level 4
190 0312h 15C0h 0003h mov #3,r0 ; expected CRDY and INTR
191 0316h 09DFh 033Eh call @#test3b
192
193 031Ah 0A1Fh 0388h clr @#isrcnt
194 031Eh 15DFh 0000h FFFEh mov #0,@#psw ; level 0
195 0324h 09DFh 0332h call @#test3a ; NOP
196 0328h 15C0h 0003h mov #3,r0 ; expected CRDY and INTR
197 032Ch 09DFh 033Eh call @#test3b
198 0330h 0087h return
199
200
201
202 ; ----------------------
203 ; putnum - print the octal number in r0
204 02E2h numbf0: .blkw 10 ; space to mount number string
205 02F2h numbf1 =.
206 putnum:
207 02F2h 1002h mov r0,r2 ; r2 = shifter
208 02F4h 15C1h 02F2h mov #numbf1,r1 ; r1 = buffer pointer, backwards
209 02F8h 95E1h 0000h movb #0,-(r1) ; set terminating 0
210 ; repeat 6 times
211 02FCh 15C3h 0006h mov #6,r3
212 1$:
213 0300h 1080h mov r2,r0
214 ; extract lower 3 bits = octal digit
215 0302h 45C0h FFF8h bic #177770,r0 ; r0 &= 0x07
216 0306h 65C0h 0030h add #60,r0 ; r0 += '0'
217 030Ah 9021h movb r0,-(r1) ; write in buffer
218 030Ch 00A1h clc
219 030Eh 0C02h ror r2 ; shift to next digit
220 0310h 0C02h ror r2
221 0312h 0C02h ror r2
222 0314h 7ECBh sob r3,1$ ; loop for all 6 digits
223
224 0316h 09DFh 02D6h call @#puts
225 031Ah 0087h return
226
227
228 ; DEC DL11 console I/O
229 ; ----------------------
230 ; putc - output a single char
231 ; r0 = char
232 putc:
233 031Ch 901Fh FF76h movb r0,@#dladr+6 ; char into transmit buffer
234 0320h 8BDFh FF74h 1$: tstb @#dladr+4 ; XMT RDY?
235 0324h 80FDh bpl 1$ ; no, loop
236 0326h 0087h return
237
238
239 ; --- string constants
240 0328h 0Dh 0Ah scrlf: .byte 15,12 ; CR, LF,
241 032Ah 00h .byte 0
242
243
244 shello:
245 032Bh 0Dh 0Ah .byte 15,12 ; CR, LF,
246 032Dh 53h 74h 61h .ascii /Starting test!/
0330h 72h 74h 69h
0333h 6Eh 67h 20h
0336h 74h 65h 73h
0339h 74h 21h
247 033Bh 0Dh 0Ah .byte 15,12 ; CR, LF,
248 033Dh 00h .byte 0
249
250 033Eh 42h 41h 3Dh sba: .ascii /BA=/
251 0341h 00h .byte 0 ; NUL=end marker
252
253 0342h 53h 65h 63h sready: .ascii /Sector 0 transfered to 100000, ISR hit./
0345h 74h 6Fh 72h
0348h 20h 30h 20h
034Bh 74h 72h 61h
034Eh 6Eh 73h 66h
0351h 65h 72h 65h
0354h 64h 20h 74h
0357h 6Fh 20h 31h
035Ah 30h 30h 30h
035Dh 30h 30h 2Ch
0360h 20h 49h 53h
0363h 52h 20h 68h
0366h 69h 74h 2Eh
254 0369h 0Dh 0Ah .byte 15,12 ; CR, LF,
255 036Bh 00h .byte 0
256
257 ; ---- 32kb page
258 8000h . = 100000
259 buffer:
260 .end ;
261
262 .end
262
201 ; send NOP cmd and wait for crdy
202 test3a:
203 ; pending interupt condition not cleared
204 0332h 0A1Fh 0388h clr @#isrcnt
205 0336h 15C0h 0040h mov #cmnop!100,r0 ; nop with Interrupt Enable
206 033Ah 100Ch mov r0,(r4) ; NOOP
207 033Ch 0087h return
208
209 ; check CRDY and ISR
210 ; r0: expected result
211 ; 0 = neither ISR nor CRDY
212 ; 1 = CRDY without ISR
213 ; 2 = ISR without CRDY
214 ; 3 = ISR and CRDY
215 test3b:
216 033Eh 1026h mov r0,-(sp) ; push
217 ; pending interupt condition not cleared
218 0340h 0A03h clr r3 ; result
219 0342h 15C0h 03E8h mov #1750,r0 ; wait 1000us for ISR and CRDY
220 0346h 09DFh 0390h call @#wtcrdy
221 034Ah 8702h bcs 1$
222 034Ch 55C3h 0001h bis #1,r3 ; Carry clear = NO timeout: CRDY r3 = 1
223 1$:
224 0350h 0BDFh 0388h tst @#isrcnt
225 0354h 0302h beq 2$
226 0356h 55C3h 0002h bis #2,r3 ; ISR detected: result |= 2
227 2$:
228 035Ah 1582h mov (sp)+,r2 ; pop
229 ; r2 = crd+isr code as expected, r3 = as measured
230 035Ch 2083h cmp r2,r3
231 035Eh 0301h beq 3$
232 0360h 0000h halt
233 3$:
234 ; print "CRDY+ISR = ..., expected ....
235 0362h 15C1h 0458h mov #scrdy1,r1 ; "CRDY+ISR ="
236 0366h 09DFh 03B8h call @#puts
237 036Ah 10C0h mov r3,r0
238 036Ch 09DFh 03D4h call @#putnum
239 0370h 15C1h 0464h mov #scrdy2,r1 ; "expected"
240 0374h 09DFh 03B8h call @#puts
241 0378h 1080h mov r2,r0
242 037Ah 09DFh 03D4h call @#putnum
243 037Eh 15C1h 0427h mov #scrlf,r1 ; print end of line
244 0382h 09DFh 03B8h call @#puts
245 0386h 0087h return
246
247
248 ; --------------
249 ; --- isr - called on interupt
250 ; print incremented BA ... is DMA really ready?
251 0388h 0000h isrcnt: .word ; flag: ISR hit
252 isr:
253 038Ah 0A9Fh 0388h inc @#isrcnt ; signal "done"
254 038Eh 0002h rti
255
256 ; - wait for "controller ready", but max r0 microseconds
257 ; result: carry clear = OK,
258 ; carry set = timeout
259
260 wtcrdy:
261 0390h 0C80h asr r0 ; wait loop is 4 cycles
262 0392h 0C80h asr r0
263 1$:
264 0394h 8BCCh tstb (r4) ; 2 cycles
265 0396h 8103h bmi 9$ ; bit 7 set -> controller ready
266 0398h 7E03h sob r0,1$
267
268 039Ah 00B1h sec ; "timeout"
269 039Ch 0087h return
270 9$:
271 039Eh 00A1h clc ; "OK"
272 03A0h 0087h return
273
274
275 ; -- wait 65ms, uses r0
276 wait65:
277 03A2h 0A00h clr r0
278 0$:
279 03A4h 7E01h sob r0,0$ : subtract one, loop until zero
280 03A6h 0087h return
281
282 ; -- wait 1ms, uses r0
283 wait1:
284 03A8h 15C0h 03E8h mov #1750,r0 ; 1000 us
285 0$:
286 03ACh 7E01h sob r0,0$ : subtract one, loop until zero
287 03AEh 0087h return
288
289
290 ; --- check for error
291 chkerr:
292 ; verify controller ready
293 03B0h 8BCCh 0$: tstb (r4) ; wait for "controller ready" (csr.7)
294 03B2h 80FEh bpl 0$ ;
295
296 03B4h 1300h mov (r4),r0 ; return status CSR
297 ; bic #1777,r0 ; ignore bits 9:0, error flags are in 15:10
298 ; bne 1$
299 ; clc
300 03B6h 0087h return ; CSR = R1 = 0: no error
301
302
303 ; ----------------------
304 ; puts - print a string
305 ; r1 = pointer, r0,r1 changed
306 puts:
307 03B8h 9440h movb (r1)+,r0 ; load xmt char
308 03BAh 0303h beq 1$ ; string ends with 0
309 03BCh 09DFh 0406h call @#putc
310 03C0h 01FBh br puts ; transmit nxt char of string
311 03C2h 0087h 1$: return
312
313
314 ; ----------------------
315 ; putnum - print the octal number in r0
316 03C4h numbf0: .blkw 10 ; space to mount number string
317 03D4h numbf1 =.
318 putnum:
319 03D4h 10A6h mov r2,-(sp)
320 03D6h 10E6h mov r3,-(sp)
321 03D8h 1002h mov r0,r2 ; r2 = shifter
322 03DAh 15C1h 03D4h mov #numbf1,r1 ; r1 = buffer pointer, backwards
323 03DEh 95E1h 0000h movb #0,-(r1) ; set terminating 0
324 ; repeat 6 times
325 03E2h 15C3h 0006h mov #6,r3
326 1$:
327 03E6h 1080h mov r2,r0
328 ; extract lower 3 bits = octal digit
329 03E8h 45C0h FFF8h bic #177770,r0 ; r0 &= 0x07
330 03ECh 65C0h 0030h add #60,r0 ; r0 += '0'
331 03F0h 9021h movb r0,-(r1) ; write in buffer
332 03F2h 00A1h clc
333 03F4h 0C82h asr r2 ; shift to next digit
334 03F6h 0C82h asr r2
335 03F8h 0C82h asr r2
336 03FAh 7ECBh sob r3,1$ ; loop for all 6 digits
337
338 03FCh 09DFh 03B8h call @#puts
339 0400h 1583h mov (sp)+,r3
340 0402h 1582h mov (sp)+,r2
341 0404h 0087h return
342
343
344 ; DEC DL11 console I/O
345 ; ----------------------
346 ; putc - output a single char
347 ; r0 = char
348 putc:
349 0406h 901Fh FF76h movb r0,@#dladr+6 ; char into transmit buffer
350 040Ah 8BDFh FF74h 1$: tstb @#dladr+4 ; XMT RDY?
351 040Eh 80FDh bpl 1$ ; no, loop
352 0410h 0087h return
353
354
355 ; --- string constants
356 shello:
357 0412h 0Dh 0Ah .byte 15,12 ; CR, LF,
358 0414h 53h 74h 61h .ascii /Starting RL11 test!/
0417h 72h 74h 69h
041Ah 6Eh 67h 20h
041Dh 52h 4Ch 31h
0420h 31h 20h 74h
0423h 65h 73h 74h
0426h 21h
359 scrlf:
360 0427h 0Dh 0Ah .byte 15,12 ; CR, LF,
361 0429h 00h .byte 0
362
363 042Ah 42h 41h 3Dh sba: .ascii /BA=/
364 042Dh 00h .byte 0 ; NUL=end marker
365
366 042Eh 53h 65h 63h sready: .ascii /Sector 0 transfered to 100000, ISR hit./
0431h 74h 6Fh 72h
0434h 20h 30h 20h
0437h 74h 72h 61h
043Ah 6Eh 73h 66h
043Dh 65h 72h 65h
0440h 64h 20h 74h
0443h 6Fh 20h 31h
0446h 30h 30h 30h
0449h 30h 30h 2Ch
044Ch 20h 49h 53h
044Fh 52h 20h 68h
0452h 69h 74h 2Eh
367 0455h 0Dh 0Ah .byte 15,12 ; CR, LF,
368 0457h 00h .byte 0
369
370
371 0458h 43h 52h 44h scrdy1: .ascii /CRDY+ISR = /
045Bh 59h 2Bh 49h
045Eh 53h 52h 20h
0461h 3Dh 20h
372 0463h 00h .byte 0
373 0464h 2Ch 20h 65h scrdy2: .ascii /, expected /
0467h 78h 70h 65h
046Ah 63h 74h 65h
046Dh 64h 20h
374 046Fh 00h .byte 0
375
376
377 ; ---- 32kb page
378 8000h . = 100000
379 buffer:
380 .end ;
381
382 .end
382

142
10.02_devices/3_test/rl02/testrl11.mac
View File

@@ -15,7 +15,8 @@ psw = 177776 ; processor status
monitr = 165020 ; entry into M9312 monitor
;; RL11 commands
; RL11 commands
cmnop = 2*0 ; no op
cmstat = 2*2 ; get status
cmseek = 3*2 ; seek
cmrdhd = 4*2 ; read header
@@ -41,12 +42,14 @@ start:
mov #stack,sp ; init stack
mov #rlbase,r4 ; r4 points to RL11 register space
reset
mov #shello,r1
call @#puts
call @#test1
; call @#test1
; call @#test2
call @#test3
jmp @#monitr
@@ -155,6 +158,92 @@ test2:
return
; --- TEST3 - ZRLG test 24
; execute NOP with Interrupt, with multiple CPU intr levels
; INTR accepted for level 5 and 4
test3:
clr @#isrcnt
; mov #1,r0 ; idle: expected CRDY and not INTR
; call @#test3b
mov #340,@#psw ; level 7
call @#test3a ; NOP
mov #1,r0 ; expected CRDY and not INTR
call @#test3b
mov #300,@#psw ; level 6
call @#test3a ; NOP
mov #1,r0 ; expected CRDY and not INTR
call @#test3b
mov #240,@#psw ; level 5
call @#test3a ; NOP
mov #1,r0 ; expected CRDY and not INTR
call @#test3b
mov #200,@#psw ; level 4, below BR5, pending triggered
mov #3,r0 ; expected CRDY and INTR
call @#test3b
clr @#isrcnt
call @#test3a ; NOP at level 4
mov #3,r0 ; expected CRDY and INTR
call @#test3b
clr @#isrcnt
mov #0,@#psw ; level 0
call @#test3a ; NOP
mov #3,r0 ; expected CRDY and INTR
call @#test3b
return
; send NOP cmd and wait for crdy
test3a:
; pending interupt condition not cleared
clr @#isrcnt
mov #cmnop!100,r0 ; nop with Interrupt Enable
mov r0,(r4) ; NOOP
return
; check CRDY and ISR
; r0: expected result
; 0 = neither ISR nor CRDY
; 1 = CRDY without ISR
; 2 = ISR without CRDY
; 3 = ISR and CRDY
test3b:
mov r0,-(sp) ; push
; pending interupt condition not cleared
clr r3 ; result
mov #1750,r0 ; wait 1000us for ISR and CRDY
call @#wtcrdy
bcs 1$
bis #1,r3 ; Carry clear = NO timeout: CRDY r3 = 1
1$:
tst @#isrcnt
beq 2$
bis #2,r3 ; ISR detected: result |= 2
2$:
mov (sp)+,r2 ; pop
; r2 = crd+isr code as expected, r3 = as measured
cmp r2,r3
beq 3$
halt
3$:
; print "CRDY+ISR = ..., expected ....
mov #scrdy1,r1 ; "CRDY+ISR ="
call @#puts
mov r3,r0
call @#putnum
mov #scrdy2,r1 ; "expected"
call @#puts
mov r2,r0
call @#putnum
mov #scrlf,r1 ; print end of line
call @#puts
return
; --------------
; --- isr - called on interupt
@@ -164,7 +253,23 @@ isr:
inc @#isrcnt ; signal "done"
rti
; - wait for "controller ready", but max r0 microseconds
; result: carry clear = OK,
; carry set = timeout
wtcrdy:
asr r0 ; wait loop is 4 cycles
asr r0
1$:
tstb (r4) ; 2 cycles
bmi 9$ ; bit 7 set -> controller ready
sob r0,1$
sec ; "timeout"
return
9$:
clc ; "OK"
return
; -- wait 65ms, uses r0
@@ -174,6 +279,13 @@ wait65:
sob r0,0$ : subtract one, loop until zero
return
; -- wait 1ms, uses r0
wait1:
mov #1750,r0 ; 1000 us
0$:
sob r0,0$ : subtract one, loop until zero
return
; --- check for error
chkerr:
@@ -204,6 +316,8 @@ puts:
numbf0: .blkw 10 ; space to mount number string
numbf1 =.
putnum:
mov r2,-(sp)
mov r3,-(sp)
mov r0,r2 ; r2 = shifter
mov #numbf1,r1 ; r1 = buffer pointer, backwards
movb #0,-(r1) ; set terminating 0
@@ -216,12 +330,14 @@ putnum:
add #60,r0 ; r0 += '0'
movb r0,-(r1) ; write in buffer
clc
ror r2 ; shift to next digit
ror r2
ror r2
asr r2 ; shift to next digit
asr r2
asr r2
sob r3,1$ ; loop for all 6 digits
call @#puts
mov (sp)+,r3
mov (sp)+,r2
return
@@ -237,13 +353,10 @@ putc:
; --- string constants
scrlf: .byte 15,12 ; CR, LF,
.byte 0
shello:
.byte 15,12 ; CR, LF,
.ascii /Starting test!/
.ascii /Starting RL11 test!/
scrlf:
.byte 15,12 ; CR, LF,
.byte 0
@@ -254,6 +367,13 @@ sready: .ascii /Sector 0 transfered to 100000, ISR hit./
.byte 15,12 ; CR, LF,
.byte 0
scrdy1: .ascii /CRDY+ISR = /
.byte 0
scrdy2: .ascii /, expected /
.byte 0
; ---- 32kb page
. = 100000
buffer:

40
10.02_devices/3_test/rl02/xxdp.cmd
View File

@@ -1,21 +1,36 @@
# inputfile for demo to select a rl1 device in the "device test" menu.
# Read in with command line option "demo --cmdfile ..."
td # device test menu
d # device test menu
# first, make a serial port. Default ist
# sd dl11
# p p ttyS2 # use "UART2 connector
# en dl11
pwr
.wait 3000 # wait for PDP-11 to reset
m i # install max UNIBUS memory
# mount XXDP22 in RL02 #0 and start
sd rl0 # select drive #0
# Deposit bootloader into memory
m ll dl.lst
en rl # enable RL11 controller
# mount scratch 0 in RL02 #0 and start
en rl0 # enable drive #0
sd rl0 # select
p emulation_speed 10 # 10x speed. Load disk in 5 seconds
# set type to "rl02"
p runstopbutton 0 # released: "LOAD"
p powerswitch 1 # power on, now in "load" state
p image xxdp22.rl02 # mount image file with test pattern
p image scratch2.rl02 # mount image file with test pattern
p runstopbutton 1 # press RUN/STOP, will start
#.end
# mount XXDP25 in RL02 #1 and start
sd rl1 # select drive #1
en rl1 # enable drive #1
sd rl1 # select
p emulation_speed 10 # 10x speed. Load disk in 5 seconds
# set type to "rl02"
p runstopbutton 0 # released: "LOAD"
@@ -23,17 +38,19 @@ p powerswitch 1 # power on, now in "load" state
p image xxdp25.rl02 # mount image file with test pattern
p runstopbutton 1 # press RUN/STOP, will start
# mount scratch2 in RL02 #2 and start
sd rl2 # select drive #2
# mount XXDP22 in RL02 #2 and start
en rl2 # enable drive #2
sd rl2 # select
p emulation_speed 10 # 10x speed. Load disk in 5 seconds
# set type to "rl02"
p runstopbutton 0 # released: "LOAD"
p powerswitch 1 # power on, now in "load" state
p image scratch2.rl02 # mount image file with test pattern
p image xxdp22.rl02 # mount image file with test pattern
p runstopbutton 1 # press RUN/STOP, will start
# mount scratch3 in RL02 #3 and start
sd rl3 # select drive #3
en rl3 # enable drive #3
sd rl3 # select
p emulation_speed 10 # 10x speed. Load disk in 5 seconds
# set type to "rl02"
p runstopbutton 0 # released: "LOAD"
@@ -45,4 +62,7 @@ p runstopbutton 1 # press RUN/STOP, will start
.wait 6000 # wait until drive spins up
p # show all params of RL1
.print RL drives ready.
.print RL11 boot loader installed.
.print Start 10000 to boot from drive 0, 10010 for drive 1, ...
.print Reload with "m ll"

BIN
10.02_devices/3_test/rl02/xxdp25_boot.als
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BIN
10.02_devices/3_test/rl02/zrlg.als
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Binary file not shown.

BIN
10.02_devices/3_test/rl02/zrlg_22.als
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4
90_common/src/inputline.c
View File

@@ -35,6 +35,7 @@
#include <ctype.h>
#include <time.h>
#include "kbhit.h"
#include "inputline.h"
/*
@@ -99,6 +100,9 @@ static int inputline_internal(char *line) {
} else if (!strncasecmp(line, ".input", 6)) {
char buffer[100] ;
printf("<<< Press ENTER to continue.\n");
// flush stuff on stdin. (Eclipse remote debugging)
while (os_kbhit()) ;
fgets(buffer, sizeof(buffer), stdin) ;
return 1 ;
} else if (!strncasecmp(line, ".end", 3)) {

1
90_common/src/logger.cpp
View File

@@ -259,6 +259,7 @@ void logger_c::message_render(char *buffer, unsigned buffer_size, logmessage_t *
// very long text? 10000 = reserve for % place holder expansion
assert(buffer_size > (strlen(msg->printf_format) + 1000));
assert(strlen(msg->logsource->log_label .c_str())) ; // forgotten?
switch (style) {
case RENDER_STYLE_CONSOLE: