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Merge remote-tracking branch 'upstream/master'

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This commit is contained in:
Josh Dersch
2019-06-19 22:26:49 +02:00
parent 8f72cb2324 ccd6747892
commit 76166ce7a1
13 changed files with 75 additions and 327 deletions
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4
10.01_base/2_src/pru1/pru1_statemachine_dma.c
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@@ -142,7 +142,7 @@ static uint8_t sm_dma_state_1() {
// prev SSYN & DATA may be still on bus, disturbes DATA
while (buslatches_getbyte(4) & BIT(5))
; // wait for SSYN inactive
__delay_cycles(NANOSECS(150) - 10);
__delay_cycles(NANOSECS(UNIBUS_DMA_MASTER_PRE_MSYN_NS) - 10);
// assume 10 cycles for buslatches_getbyte and address test
// ADDR, CONTROL (and DATA) stable since 150ns, set MSYN
@@ -192,7 +192,7 @@ static uint8_t sm_dma_state_1() {
buslatches_setbits(4, 0x3f, tmpval);
// wait 150ns after MSYN, no distance to SSYN required
__delay_cycles(NANOSECS(150) - 10);
__delay_cycles(NANOSECS(UNIBUS_DMA_MASTER_PRE_MSYN_NS) - 10);
// assume 10 cycles for buslatches_getbyte and address test
// ADDR, CONTROL (and DATA) stable since 150ns, set MSYN next

35
10.01_base/2_src/shared/mailbox.h
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@@ -32,22 +32,23 @@
#include "unibus.h"
// arm to pru
#define ARM2PRU_NONE 0 // don't change
#define ARM2PRU_HALT 1 // run PRU1 into halt
#define ARM2PRU_MAILBOXTEST1 2
#define ARM2PRU_BUSLATCH_INIT 3 // reset all mux registers to "neutral"
#define ARM2PRU_BUSLATCH_SET 4 // set a mux register
#define ARM2PRU_BUSLATCH_GET 5 // read a mux register
#define ARM2PRU_BUSLATCH_EXERCISER 6 // exercise 8 accesses to mux registers
#define ARM2PRU_BUSLATCH_TEST 7 // read a mux register
#define ARM2PRU_INITPULSE 8 // pulse UNIBUS INIT
#define ARM2PRU_POWERCYCLE 9 // ACLO/DCLO power cycle simulation
#define ARM2PRU_DMA_ARB_NONE 10 // DMA without NPR/NPG/SACK arbitration
#define ARM2PRU_DMA_ARB_CLIENT 11 // DMA with arbitration by external Arbitrator
#define ARM2PRU_DMA_ARB_MASTER 12 // DMA as Arbitrator
#define ARM2PRU_DDR_FILL_PATTERN 13 // fill DDR with test pattern
#define ARM2PRU_DDR_SLAVE_MEMORY 14 // use DDR as UNIBUS slave memory
#define ARM2PRU_INTR 15 // INTR, only with arbitration
#define ARM2PRU_NONE 0 // Operation complete: don't change
#define ARM2PRU_NOP 1 // to check wether PRU is running
#define ARM2PRU_HALT 2 // run PRU1 into halt
#define ARM2PRU_MAILBOXTEST1 3
#define ARM2PRU_BUSLATCH_INIT 4 // reset all mux registers to "neutral"
#define ARM2PRU_BUSLATCH_SET 5 // set a mux register
#define ARM2PRU_BUSLATCH_GET 6 // read a mux register
#define ARM2PRU_BUSLATCH_EXERCISER 7 // exercise 8 accesses to mux registers
#define ARM2PRU_BUSLATCH_TEST 8 // read a mux register
#define ARM2PRU_INITPULSE 9 // pulse UNIBUS INIT
#define ARM2PRU_POWERCYCLE 10 // ACLO/DCLO power cycle simulation
#define ARM2PRU_DMA_ARB_NONE 11 // DMA without NPR/NPG/SACK arbitration
#define ARM2PRU_DMA_ARB_CLIENT 12 // DMA with arbitration by external Arbitrator
#define ARM2PRU_DMA_ARB_MASTER 13 // DMA as Arbitrator
#define ARM2PRU_DDR_FILL_PATTERN 14 // fill DDR with test pattern
#define ARM2PRU_DDR_SLAVE_MEMORY 15 // use DDR as UNIBUS slave memory
#define ARM2PRU_INTR 16 // INTR, only with arbitration
// possible states of DMA machine
#define DMA_STATE_READY 0 // idle
@@ -165,7 +166,7 @@ typedef struct {
mailbox_test_t mailbox_test;
mailbox_buslatch_t buslatch;
mailbox_buslatch_test_t buslatch_test;
mailbox_buslatch_exerciser_t buslatch_exerciser;
mailbox_buslatch_exerciser_t buslatch_exerciser;
mailbox_dma_t dma;
mailbox_intr_t intr;
};

2
10.01_base/2_src/shared/tuning.h
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@@ -38,7 +38,7 @@
#if defined(TUNING_PCB_TEST)
// experimental to test error rates
#define BUSLATCHES_GETBYTE_DELAY 10
#define BUSLATCHES_SETBITS_DELAY 2
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
#elif defined(TUNING_PCB_LEGACY_SECURE)