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Fix GitHub repository

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This commit is contained in:
Joerg Hoppe
2019-08-05 08:37:03 +02:00
parent 10cf1598f1
commit d9b49ac70f
7 changed files with 256 additions and 297 deletions
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14
10.01_base/2_src/shared/ddrmem.h
View File

@@ -38,26 +38,25 @@ public:
/* these values are generated by prussdrv functions */
// base address of shared DDR memory, in ARM Linux memory space
volatile ddrmem_t *base_virtual;
uint32_t len;// size of allocated range as given by UIO driver
uint32_t len; // size of allocated range as given by UIO driver
// physical ddrmem_base address, for access by PRU
uint32_t base_physical;
// emulated address range
bool enabled = false ; // true if startaddr <= endaddr
bool enabled = false; // true if startaddr <= endaddr
uint32_t unibus_startaddr;
uint32_t unibus_endaddr;
ddrmem_c() ;
ddrmem_c();
void info(void);
void save(char *fname);
void load(char *fname);
void clear(void);
void fill_pattern(void);
void fill_pattern_pru(void);
void unibus_slave(uint32_t startaddr, uint32_t endaddr);
bool set_range(uint32_t startaddr, uint32_t endaddr);
bool deposit(uint32_t addr, uint16_t w);
bool exam(uint32_t addr, uint16_t *w);
void unibus_slave(uint32_t startaddr, uint32_t endaddr);bool set_range(uint32_t startaddr,
uint32_t endaddr);bool deposit(uint32_t addr, uint16_t w);bool exam(uint32_t addr,
uint16_t *w);
};
#ifndef _DDRMEM_C_
@@ -78,7 +77,6 @@ extern ddrmem_c *ddrmem;
#define DDRMEM_MEMGET_W(addr) \
( mailbox.ddrmem_base_physical->memory.words[(addr)/2] )
void ddrmem_fill_pattern(void);
#endif

39
10.01_base/2_src/shared/iopageregister.h
View File

@@ -1,28 +1,28 @@
/* iopageregister.h: Tables of implemented devices and their registers.
Datastructures common to ARM and PRU.
/* iopageregister.h: Tables of implemented devices and their registers.
Datastructures common to ARM and PRU.
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered Beta phase
12-nov-2018 JH entered Beta phase
Implementation of UNIBUS devices:
@@ -116,7 +116,6 @@
// #define MAX_REGISTERS_PER_DEVICE 32 // RK611 has the most?
#define MAX_DEVICE_HANDLE 255 // 0 not used, must fit in 8bits
// Bitmask: Create event fpr iopagergister DATI/DATO access ?
#define IOPAGEREGISTER_EVENT_FLAG_DATI 0x01
#define IOPAGEREGISTER_EVENT_FLAG_DATO 0x02

157
10.01_base/2_src/shared/mailbox.h
View File

@@ -1,29 +1,28 @@
/* mailbox.h: Command and status data structures common to ARM and PRU
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
*/
12-nov-2018 JH entered beta phase
*/
#ifndef _MAILBOX_H_
#define _MAILBOX_H_
@@ -32,7 +31,7 @@
#include "unibus.h"
// arm to pru
#define ARM2PRU_NONE 0 // Operation complete: don't change
#define ARM2PRU_NONE 0 // Operation complete: must be 0!
#define ARM2PRU_NOP 1 // to check wether PRU is running
#define ARM2PRU_HALT 2 // run PRU1 into halt
#define ARM2PRU_MAILBOXTEST1 3
@@ -43,12 +42,14 @@
#define ARM2PRU_BUSLATCH_TEST 8 // read a mux register
#define ARM2PRU_INITPULSE 9 // pulse UNIBUS INIT
#define ARM2PRU_POWERCYCLE 10 // ACLO/DCLO power cycle simulation
#define ARM2PRU_DMA_ARB_NONE 11 // DMA without NPR/NPG/SACK arbitration
#define ARM2PRU_DMA_ARB_CLIENT 12 // DMA with arbitration by external Arbitrator
#define ARM2PRU_DMA_ARB_MASTER 13 // DMA as Arbitrator
#define ARM2PRU_DDR_FILL_PATTERN 14 // fill DDR with test pattern
#define ARM2PRU_DDR_SLAVE_MEMORY 15 // use DDR as UNIBUS slave memory
#define ARM2PRU_INTR 16 // INTR, only with arbitration
#define ARM2PRU_ARB_MODE_NONE 11 // DMA without NPR/NPG/SACK arbitration
#define ARM2PRU_ARB_MODE_CLIENT 12 // DMA with arbitration by external Arbitrator
#define ARM2PRU_ARB_MODE_MASTER 13 // DMA as Arbitrator
#define ARM2PRU_DMA 14 // DMA with selcted arbitration
#define ARM2PRU_INTR 15 // INTR with arbitration by external Arbitrator
#define ARM2PRU_INTR_CANCEL 16 // clear INTR which has been requested
#define ARM2PRU_DDR_FILL_PATTERN 17 // fill DDR with test pattern
#define ARM2PRU_DDR_SLAVE_MEMORY 18 // use DDR as UNIBUS slave memory
// possible states of DMA machine
#define DMA_STATE_READY 0 // idle
@@ -58,12 +59,17 @@
#define DMA_STATE_INITSTOP 4 // stop because INIT signal sensed
// bits BR*/NPR interrupts in buslatch 0 and 1
#define ARBITRATION_PRIORITY_BIT_B4 0x01
#define ARBITRATION_PRIORITY_BIT_B5 0x02
#define ARBITRATION_PRIORITY_BIT_B6 0x04
#define ARBITRATION_PRIORITY_BIT_B7 0x08
#define ARBITRATION_PRIORITY_BIT_NP 0x10
#define ARBITRATION_PRIORITY_MASK 0x1f
// bit # is index into arbitration_request[] array.
#define PRIORITY_ARBITRATION_BIT_B4 0x01
#define PRIORITY_ARBITRATION_BIT_B5 0x02
#define PRIORITY_ARBITRATION_BIT_B6 0x04
#define PRIORITY_ARBITRATION_BIT_B7 0x08
#define PRIORITY_ARBITRATION_BIT_NP 0x10
#define PRIORITY_ARBITRATION_INTR_MASK 0x0f // BR4|BR5|BR6|BR7
#define PRIORITY_ARBITRATION_BIT_MASK 0x1f
// data for a requested DMA operation
#define PRU_MAX_DMA_WORDCOUNT 512
#include "ddrmem.h"
@@ -87,13 +93,12 @@ typedef struct {
#define MAILBOX_BUSLATCH_EXERCISER_PATTERN_COUNT 4
typedef struct {
uint8_t pattern ; // input: which access pattern?
uint8_t addr[8] ; // access sequence of register addresses
uint8_t writeval[8] ; // data value for each
uint8_t readval[8] ; // read back results
uint8_t pattern; // input: which access pattern?
uint8_t addr[8]; // access sequence of register addresses
uint8_t writeval[8]; // data value for each
uint8_t readval[8]; // read back results
} mailbox_buslatch_exerciser_t;
typedef struct {
uint8_t addr_0_7; // start values for test sequence
uint8_t addr_8_15;
@@ -102,27 +107,35 @@ typedef struct {
} mailbox_buslatch_test_t;
// data for a requested DMA operation
#define MAX_DMA_WORDCOUNT 512
typedef struct {
// take care of 32 bit word borders for struct members
uint8_t cur_status; // 0 = idle, 1 = running, 2 = timeout error
uint8_t control; // cycle to perform: only DATO, DATI allowed
uint16_t wordcount; // # of remaining words transmit/receive, static
uint32_t cur_addr; // current address in tranwfer, if timeout: offending address.
// ---dword---
uint32_t cur_addr; // current address in transfer, if timeout: offending address.
// if complete: last address accessed.
uint32_t startaddr; // address of 1st word to transfer
uint16_t words[MAX_DMA_WORDCOUNT]; // buffer for rcv/xmt data
uint16_t words[PRU_MAX_DMA_WORDCOUNT]; // buffer for rcv/xmt data
} mailbox_dma_t;
// data for all 4 pending INTR requests
// vector for an INTR transaction
typedef struct {
uint16_t vector; // interrupt vector to be transferred
uint8_t priority_bit; // one of ARBITRATION_PRIORITY_B[4-7]
} mailbox_intr_t;
/* all requested INTRs */
uint16_t vector[4]; // interrupt vectors for BR4..7 to be transferred
// ---dword---
// event triggered on UNIBUS access to "active" device registers
// set by PRU, read by ARM on event. Bitmask.
#define EVENT_DEVICEREGISTER 0x01
#define EVENT_INITIALIZATIONSIGNALS 0x02
/* data for currently requested with ARM2PRU_INTR */
uint8_t priority_arbitration_bit; // PRIORITY_ARBITRATION_BIT_*
uint8_t level_index; // newly requested BR*. 0 = BR4, ... 3 = BR7
// interrupt register state to be set atomically with BR line
uint16_t iopage_register_value;
// ---dword---
uint8_t iopage_register_handle;
uint8_t _dummy1, _dummy2, _dummy3;
// multiple of 32 bit now
} mailbox_intr_t;
// states of initialization section lines. Bitmask = latch[7]
#define INITIALIZATIONSIGNAL_INIT (1 << 3)
@@ -130,20 +143,47 @@ typedef struct {
#define INITIALIZATIONSIGNAL_DCLO (1 << 5)
typedef struct {
uint8_t eventmask; // bitwise. triggered, 0 = invalid/ACKEed by ARM
/*** EVENT_DEVICEREGISTER ***/
// trigger flags raised by PRU, reset by ARM
// differemt events can be raised asynchronically and concurrent,
// but a single event type is sequentially raised by PRU and cleared by ARM.
/* Access to device register ***/
uint8_t event_deviceregister; // trigger flag
// info about register access
uint8_t unibus_control; // DATI,DATO,DATOB
// handle of controller
uint8_t device_handle;
// # of register in device space
uint8_t device_register_idx;
// ---dword---
// UNIBUS address accessed
uint32_t addr; // accessed address: odd/even important for DATOB
uint16_t data ; // data vale for DATO event
// ---dword---
uint16_t data; // data value for DATO event
/*** EVENT_INITIALIZATIONSIGNALS ***/
/*** DMA transfer complete
After ARM2PRU_DMA_*, NPR/NPG/SACK protocll was executed and
Data trasnfered accoring to mailbox_dma_t.
After that, mailbox_dma_t is updated and signal raised.
*/
uint8_t event_dma; // trigger flag
/*** Event priority arbitration data transfer complete
After ARM2PRU_INTR, one of BR4/5/6/7 NP was requested,
granted, and the data transfer was handled as bus master.
*/
uint8_t _dummy1;
// ---dword---
uint8_t event_intr; // trigger flag: 1 = one of BR4,5,6,7 vector on UNIBUS
uint8_t event_intr_level_index; // 0..3 -> BR4..BR7
uint8_t _dummy2, _dummy3;
// ---dword---
/*** INIT or Power cycle seen on UNIBUS ***/
uint8_t event_init; // trigger flag
uint8_t event_power; // trigger flag
uint8_t initialization_signals_prev; // on event: a signal changed from this ...
// ---dword---
uint8_t initialization_signals_cur; // ... to this
// uint8_t dummy[2]; // make record multiple of dword !!!
@@ -161,14 +201,16 @@ typedef struct {
// set by PRU, read by ARM on event
mailbox_events_t events;
mailbox_intr_t intr;
mailbox_dma_t dma;
// data structs for misc. opcodes
union {
mailbox_test_t mailbox_test;
mailbox_buslatch_t buslatch;
mailbox_buslatch_test_t buslatch_test;
mailbox_buslatch_exerciser_t buslatch_exerciser;
mailbox_dma_t dma;
mailbox_intr_t intr;
mailbox_buslatch_exerciser_t buslatch_exerciser;
};
} mailbox_t;
@@ -188,7 +230,7 @@ extern volatile mailbox_t *mailbox;
void mailbox_print(void);
int mailbox_connect(void);
void mailbox_test1(void);
void mailbox_execute(uint8_t request, uint8_t stopcode);
void mailbox_execute(uint8_t request);
#else
// included by PRU code
@@ -204,8 +246,9 @@ extern volatile far mailbox_t mailbox;
mailbox.events.device_handle = _reg->event_device_handle ;\
mailbox.events.device_register_idx = _reg->event_device_register_idx ; \
mailbox.events.addr = _addr ; \
mailbox.events.data = _data ; \
mailbox.events.eventmask |= EVENT_DEVICEREGISTER ; /* data for ARM valid now*/ \
mailbox.events.data = _data ; \
mailbox.events.event_deviceregister = 1 ; \
/* data for ARM valid now*/ \
PRU2ARM_INTERRUPT ; \
/* leave SSYN asserted until mailbox.event.signal ACKEd to 0 */ \
} while(0)

78
10.01_base/2_src/shared/priority_arbitration_requests.h
View File

@@ -1,78 +0,0 @@
/* priority_arbitration_requests.h: data struct to describe requests
Datastructures common to ARM and PRU.
Copyright (c) 2019, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28-jun-2019 JH begin
PRU handles all 5 requests in parlalel.
4x INMTR BR4-BR7
1x DMA NPR.
Several ARM devcie may raise same BR|NPR level, ARM must serialize this to PRU.
1. ARM sets a REQUEST by
filling the RQUEST struct and perhaps DMA data
doing AMR2PRO_PRIORITY_ARBITRATION_REQUEST,
2. PRU sets BR4567|NPR lines according to open requests
3. PRU monitors IN GRANT lines BG4567,NPG.
IN state of idle requests is forwarded to BG|NPG OUT liens,
to be processed by other UNIBUS cards.
BG*|NPG IN state line of active request cleares BR*|NPR line,
sets SACK, and starts INTR or DMA state machine.
4. INTR or DMA sent a signal on compelte to PRU.
PRU may then start next request on same (completed) BR*|NPR level.
*/
// bits BR*/NPR interrupts in buslatch 0 and 1
// bit # is index into arbitration_request[] array.
#define PRIORITY_ARBITRATION_BIT_B4 0x01
#define PRIORITY_ARBITRATION_BIT_B5 0x02
#define PRIORITY_ARBITRATION_BIT_B6 0x04
#define PRIORITY_ARBITRATION_BIT_B7 0x08
#define PRIORITY_ARBITRATION_BIT_NP 0x10
#define PRIORITY_ARBITRATION_BIT_MASK 0x1f
// info for one of 5 busrequests (BR4,5,6,7,NPR) generated by ARM
typedef struct {
// INTR BR* and DMA/NPR
uint8_t priority_bit ; // PRIORITY_ARBITRATION_BIT_* for buslatch 0
uint32_t data_transfer_complete_signal_tag ; // value returned with signal on complete
// only INTR: interrupt register state to be set atomically with BR line
uint8_t iopage_register_handle ;
uint16_t iopage_register_value ;
uint16_t vector; // interrupt vector to be transferred
// DMA transaction data in mailbox_dma_t struct
} priority_arbitration_request_t ;
// list of all requests, some possible active
typedef struct {
// active BR/NPR signals, buslatch 0, PRIORITY_ARBITRATION_*
uint8_t active_request_bits ;
// index by bit # in "pirity b:it
// BR4->[0], .. BR7 -> [3], NPR->[4]
// Bit # in GRANT line is index here
priority_arbitration_request_t priority_arbitration_request[5] ;
} priority_arbitration_requests_t ;

45
10.01_base/2_src/shared/pru_pru_mailbox.h
View File

@@ -1,28 +1,28 @@
/* pru_pru_mailbox.h: structure for data exchange between PRU0 and PRU1
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
*/
12-nov-2018 JH entered beta phase
*/
#ifndef _PRU_PRU_MAILBOX_H_
#define _PRU_PRU_MAILBOX_H_
@@ -30,16 +30,15 @@
#include <stdint.h>
typedef struct {
// just the state of PRU0 R30 output.
// just the state of PRU0 R30 output.
// PRU1 writes the value
// PRU0 monitors and copies to its local R30 = REG_DATA_OUT pins
uint32_t xxx_pru0_r30 ;
} pru_pru_mailbox_t ;
uint32_t xxx_pru0_r30;
} pru_pru_mailbox_t;
#ifndef _PRU_PRU_MAILBOX_C_
extern volatile pru_pru_mailbox_t pru_pru_mailbox ;
extern volatile pru_pru_mailbox_t pru_pru_mailbox;
#endif
#endif

109
10.01_base/2_src/shared/tuning.h
View File

@@ -1,30 +1,28 @@
/* tuning.h: Constants to adapt UNIBUS functions
Copyright (c) 2019, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2019, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7-jun-2019 JH entered beta phase
*/
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7-jun-2019 JH entered beta phase
*/
#define TUNING_PCB_LEGACY_SECURE
//#define TUNING_PCB_2018_12_OPTIMIZED
@@ -34,50 +32,47 @@
// A BBB with optimized terminators can reach 8
// BBG can reach *ALMOST* 9
// #define BUSLATCHES_GETBYTE_DELAY 10 // Standard
#if defined(TUNING_PCB_TEST)
// experimental to test error rates
#define BUSLATCHES_GETBYTE_DELAY 10
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
// experimental to test error rates
#define BUSLATCHES_GETBYTE_DELAY 10
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
#elif defined(TUNING_PCB_LEGACY_SECURE)
/* Secure setting for PCBs <= 2018-12, delivered before June 2019.
Necessary for longtime ZKMA on critical PCBs.
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138
RN8,9 (DATIN) : 47
RN10 <1:6>(REGADR): 33
RN10 <7:8>(REGWRITE): 33
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22
RN4,RN5 [[/DATOUT]] end) -> 1K/-
*/
#define BUSLATCHES_GETBYTE_DELAY 11
#define BUSLATCHES_SETBITS_DELAY 5
#define BUSLATCHES_SETBYTE_DELAY 7
/* Secure setting for PCBs <= 2018-12, delivered before June 2019.
Necessary for longtime ZKMA on critical PCBs.
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138
RN8,9 (DATIN) : 47
RN10 <1:6>(REGADR): 33
RN10 <7:8>(REGWRITE): 33
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22
RN4,RN5 [[/DATOUT]] end) -> 1K/-
*/
#define BUSLATCHES_GETBYTE_DELAY 11
#define BUSLATCHES_SETBITS_DELAY 5
#define BUSLATCHES_SETBYTE_DELAY 7
#elif defined(TUNING_PCB_2018_12_OPTIMIZED)
/* Setting for PCB v2018_12 with optimized timing (ticket 21, June 2019)
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138 -> 74AHC138
RN8,9 (DATIN) : 47 -> 68 Ohm
RN10 <1:6>(REGADR): 33->0 Ohm
RN10 <7:8>(REGWRITE): 33->0 Ohm
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22 -> 27
RN4,RN5 [[/DATOUT]] end) -> 180/-
*/
#define BUSLATCHES_GETBYTE_DELAY 9
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
//#define BUSLATCHES_GETBYTE_DELAY 8
//#define BUSLATCHES_SETBITS_DELAY 3
//#define BUSLATCHES_SETBYTE_DELAY 5
/* Setting for PCB v2018_12 with optimized timing (ticket 21, June 2019)
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138 -> 74AHC138
RN8,9 (DATIN) : 47 -> 68 Ohm
RN10 <1:6>(REGADR): 33->0 Ohm
RN10 <7:8>(REGWRITE): 33->0 Ohm
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22 -> 27
RN4,RN5 [[/DATOUT]] end) -> 180/-
*/
#define BUSLATCHES_GETBYTE_DELAY 9
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
//#define BUSLATCHES_GETBYTE_DELAY 8
//#define BUSLATCHES_SETBITS_DELAY 3
//#define BUSLATCHES_SETBYTE_DELAY 5
#endif
// UNIBUS timing: Wait to stabilize DATA before MSYN asserted
// per DEC spec
// #define UNIBUS_DMA_MASTER_PRE_MSYN_NS 150

111
10.01_base/2_src/shared/unibus.h
View File

@@ -1,31 +1,30 @@
/* unibus.h: shared structs used in PRU and ARM
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
19-may-2018 JH created
*/
12-nov-2018 JH entered beta phase
19-may-2018 JH created
*/
#ifndef _UNIBUS_H_
#define _UNIBUS_H_
@@ -34,13 +33,12 @@
#define UNIBUS_WORDCOUNT 0x20000 // 128KiW = 256 KiB
// bus transaction. can be directly assigned to lines C1,C0
#define UNIBUS_CONTROL_DATI 0x00 // 16 bit word from slave to master
#define UNIBUS_CONTROL_DATIP 0x01 // DATI, inhibts core restore. DATO must follow.
#define UNIBUS_CONTROL_DATO 0x02 // 16 bit word from master to slave
#define UNIBUS_CONTROL_DATOB 0x03 // 8 bit byte from master to slave
// data<15:8> for a00 = 1, data<7:0> for a00 = 0
// data<15:8> for a00 = 1, data<7:0> for a00 = 0
#define UNIBUS_CONTROL_ISDATO(c) (!!((c) & 0x02)) // check for DATO/B
#define UNIBUS_TIMEOUTVAL 0xffffffff // EXAM result for bus timeout
@@ -51,27 +49,29 @@
// pru c-compile is NOT called with --endian=big
typedef struct {
union {
uint16_t words[UNIBUS_WORDCOUNT] ;
uint8_t bytes[2*UNIBUS_WORDCOUNT] ;
} ;
uint16_t words[UNIBUS_WORDCOUNT];
uint8_t bytes[2 * UNIBUS_WORDCOUNT];
};
} unibus_memory_t;
#ifdef ARM
// included only by ARM code
#include "logsource.hpp"
#include "utils.hpp"
// parameter and functions for low level UNIBUS control
class dma_request_c;
class intr_request_c;
class unibus_c: public logsource_c {
public:
enum arbitration_mode_enum {
ARBITRATION_MODE_NONE = 0, // no BR*/BG*, NR/NPG SACK protocoll
ARBITRATION_MODE_CLIENT = 1, // external Arbitrator (running PDP-11 CPU) required
ARBITRATION_MODE_MASTER = 2 // implmenet Arbitrator
// with or without physical CPU for arbitration
} ;
enum arbitration_mode_enum {
ARBITRATION_MODE_NONE = 0, // no BR*/BG*, NR/NPG SACK protocoll
ARBITRATION_MODE_CLIENT = 1, // external Arbitrator (running PDP-11 CPU) required
ARBITRATION_MODE_MASTER = 2 // implmenet Arbitrator
// with or without physical CPU for arbitration
};
private:
@@ -79,40 +79,43 @@ private:
public:
// percent of time to be used for DMA master cycles
unsigned dma_bandwidth_percent ;
// default size of dma block transfers
unsigned dma_wordcount ;
unibus_c();
~unibus_c();
unibus_c() ;
static char *control2text(uint8_t control) ;
static char *control2text(uint8_t control);
static char *data2text(unsigned val);
void init(void);
void powercycle(void) ;
static void set_arbitration_mode(enum arbitration_mode_enum arbitration_mode);
void interrupt(uint8_t priority, uint16_t vector) ;
bool dma(enum unibus_c::arbitration_mode_enum arbitration_mode, uint8_t control, uint32_t startaddr,
unsigned blocksize);
void powercycle(void);
void mem_read(enum unibus_c::arbitration_mode_enum arbitration_mode,
uint16_t *words, uint32_t start_addr,
uint32_t end_addr, unsigned blocksize, bool *timeout) ;
void mem_write(enum unibus_c::arbitration_mode_enum arbitration_mode,
uint16_t *words, unsigned start_addr,
unsigned end_addr, unsigned blocksize, bool *timeout) ;
// functions of unibusadapter to do simple DMA
dma_request_c *dma_request;
//intr_request_c *intr_request;
uint32_t test_sizer(enum unibus_c::arbitration_mode_enum arbitration_mode) ;
bool dma(enum unibus_c::arbitration_mode_enum arbitration_mode, bool blocking, uint8_t control,
uint32_t startaddr, uint16_t *buffer, unsigned wordcount);
void mem_read(enum unibus_c::arbitration_mode_enum arbitration_mode, uint16_t *words,
uint32_t unibus_start_addr, uint32_t unibus_end_addr, bool *timeout);
void mem_write(enum unibus_c::arbitration_mode_enum arbitration_mode, uint16_t *words,
unsigned unibus_start_addr, unsigned unibus_end_addr, bool *timeout);
void mem_access_random(enum unibus_c::arbitration_mode_enum arbitration_mode,
uint8_t unibus_control, uint16_t *words, uint32_t unibus_start_addr,
uint32_t unibus_end_addr, bool *timeout, uint32_t *block_counter);
uint32_t test_sizer(enum unibus_c::arbitration_mode_enum arbitration_mode);
uint16_t testwords[UNIBUS_WORDCOUNT];
void test_mem(enum unibus_c::arbitration_mode_enum arbitration_mode, uint32_t start_addr, uint32_t end_addr, unsigned mode) ;
void test_mem(enum unibus_c::arbitration_mode_enum arbitration_mode, uint32_t start_addr,
uint32_t end_addr, unsigned mode);
};
extern unibus_c *unibus ;
extern unibus_c *unibus;
#endif /* ARM */