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Version 2019-06: many changes

Browse Source 
PRU1 code split into multiple images
1. test functions
2. UNIBUS operation

PRU1 bus latch interface
Write byte/bits access not with MACROS (random optimizer influence),
now with *_helper() procedures. Same timing, more determinism, much code saving.
Nono more  ASM code to write PRU0 XFER area.

demo: menu to test UNIBUS signals directly

rework "Arbitration" logic: now 3-fold
Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER
- no Arbitrator (SACK penidng for 11/34 Konsole) (NONE)
- phyiscal PDP_11 CPU is Arbitrator (CLIENT)
- UniBone implements Arbitrator (MASTER)
- Same PRU code loop handles all arbitration types

PRU buslatch timing slower, for some problematic PCBs

 More aggressive bus latch  selftest
 (mixed patterns, running on PRU now)

Refinement of ready-to-run scripts
- Adapted to changed "demo" menu
- new name scheme
<OS>_<boot- drive>_<PDP-11CPU>
indicates
- which OS is run
- which disk emulation is used and what is the boot device
- what is the (minimum) PDP-11 to run that

Merged in Joshs DMA timing for 11/84
UNIBUS master cycles waits 350 us before MSYN, instead 150.

Merged in Joshs DMA request queue
multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially

Merged in Joshs MSCP driver
- Build RT-11v5.5 for MSCP
- added boot loader "du.lst"

MSCP run scrips
2.11BSD on MSCP on PDP-11/44
RT11 on MSCP

Fix: image file sizing
Disk image file exptend automatically if block beyond current file end is written
This commit is contained in:
Joerg Hoppe
2019-06-14 16:31:01 +02:00
parent 81012ce54c
commit db0167afe1
183 changed files with 7189 additions and 105106 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
10.01_base/2_src/arm/ddrmem.cpp
View File

@@ -87,7 +87,7 @@ void ddrmem_c::save(char *fname) {
unsigned n;
fout = fopen(fname, "wb");
if (!fout) {
ERROR("Error opening file %s for write", fname);
ERROR(fileErrorText("Error opening file %s for write", fname));
return;
}
n = fwrite((void *) base_virtual->memory.words, 2, wordcount, fout);
@@ -104,7 +104,7 @@ void ddrmem_c::load(char *fname) {
FILE *fin;
fin = fopen(fname, "rb");
if (!fin) {
ERROR("Error opening file %s for read", fname);
ERROR(fileErrorText("Error opening file %s for read", fname));
return;
}
// try to read max address range, shorter files are OK
@@ -180,7 +180,7 @@ void ddrmem_c::unibus_slave(uint32_t startaddr, uint32_t endaddr) {
mailbox->arm2pru_req = ARM2PRU_DDR_SLAVE_MEMORY;
printf("Hit 'q' ENTER to end.\n");
do { // only this code wait for input under Eclipse
s = inputline(buf, sizeof(buf));
s = inputline(buf, sizeof(buf), NULL);
} while (strlen(s) == 0);
// clearing arm2pru_req stops the emulation
mailbox_execute(ARM2PRU_NONE, ARM2PRU_NONE);

42
10.01_base/2_src/arm/device.cpp
View File

@@ -52,17 +52,34 @@ list<device_c *> device_c::mydevices;
// argument is a device_c
// called reentrant in parallel for all different devices
void *worker_pthread_wrapper(void *context) {
// called on cancel and exit()
static void device_worker_pthread_cleanup_handler(void *context) {
device_c *device = (device_c *) context;
#define this device // make INFO work
device->worker_terminate = false;
device->worker_terminated = true; // ended on its own or on worker_terminate
INFO("Worker terminated for device %s.", device->name.value.c_str());
device->worker_terminate = false;
device->worker_terminated = true; // ended on its own or on worker_terminate
// printf("cleanup for device %s\n", device->name.value.c_str()) ;
#undef this
}
static void *device_worker_pthread_wrapper(void *context) {
device_c *device = (device_c *) context;
int oldstate ; // not used
#define this device // make INFO work
// call real worker
INFO("%s::worker() started", device->name.value.c_str());
pthread_setcancelstate(PTHREAD_CANCEL_ENABLE, &oldstate) ;
pthread_setcanceltype(PTHREAD_CANCEL_DEFERRED, &oldstate) ; //ASYNCH not allowed!
device->worker_terminate = false;
device->worker_terminated = false;
pthread_cleanup_push(device_worker_pthread_cleanup_handler, device) ;
device->worker();
INFO("%s::worker() terminated", device->name.value.c_str());
device->worker_terminate = false;
device->worker_terminated = true; // ended on its own or on worker_terminate
pthread_cleanup_pop(1) ; // call cleanup_handler on regular exit
// not reached on pthread_cancel()
#undef this
return NULL;
}
@@ -245,11 +262,12 @@ void device_c::worker_start(void) {
pthread_attr_t attr;
pthread_attr_init(&attr);
// pthread_attr_setstacksize(&attr, 1024*1024);
int status = pthread_create(&worker_pthread, &attr, &worker_pthread_wrapper,
int status = pthread_create(&worker_pthread, &attr, &device_worker_pthread_wrapper,
(void *) this);
if (status != 0) {
FATAL("Failed to create pthread with status = %d", status);
}
pthread_attr_destroy(&attr) ; // why?
}
}
@@ -257,20 +275,24 @@ void device_c::worker_stop(void) {
timeout_c timeout;
int status;
if (worker_terminated) {
DEBUG("%s.worker_stop(): already termianted.", name.name.c_str());
DEBUG("%s.worker_stop(): already terminated.", name.name.c_str());
return;
}
INFO("Waiting for %s.worker() to stop ...", name.name.c_str());
INFO("Waiting for %s.worker() to stop ...", name.value.c_str());
worker_terminate = true;
// 100ms
timeout.wait_ms(100);
// worker_wrapper must do "worker_terminated = true;" on exit
if (!worker_terminated) {
// if thread is hanging in pthread_cond_wait()
pthread_cancel(worker_pthread);
// if thread is hanging in pthread_cond_wait(): send a cancellation request
status = pthread_cancel(worker_pthread);
if (status != 0)
FATAL("Failed to send cancellation request to worker_pthread with status = %d", status);
}
// !!! this crashes for unibusadapter if realtime priority SCHED_FIFO is set !!!
// !! If crosscompling: this causes a crash in the worker thread
// !! at pthread_cond_wait() or other cancellation points.
// !! No problem for compiles build on BBB itself.
status = pthread_join(worker_pthread, NULL);
if (status != 0) {
FATAL("Failed to join worker_pthread with status = %d", status);

451
10.01_base/2_src/arm/gpios.cpp
View File

@@ -21,6 +21,7 @@
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21-may-2019 JH added UNIBUS signals
12-nov-2018 JH entered beta phase
*/
@@ -37,6 +38,7 @@
#include "mailbox.h"
#include "pru.hpp"
#include "utils.hpp"
#include "logsource.hpp"
#include "logger.hpp"
@@ -250,7 +252,7 @@ void gpios_c::test_loopback(void) {
/* return a string with board signal path for an UNIBUS signal
* used as error info for loopback failures
*/
buslatches_signal_info_t buslatches_signal_info[] = { //
buslatches_wire_info_t buslatches_wire_info[] = { //
//
// Register 0 write (PRU -> 74LS377 -> DS8641)
{ 0, 0, 0, 1, "BG4_OUT",
@@ -416,9 +418,9 @@ buslatches_signal_info_t buslatches_signal_info[] = { //
//
// Register 4 read (PRU <- 74LVTH541 <- DS8641)
{ 4, 0, 1, 0, "A16",
"P8.45 <- J17.1 DATIN_0 <- U13.18 <- U13.02 <- U27.13 <- U27.15 <- A16" },//
"P8.45 <- J17.1 DATIN_0 <- U25.18 <- U25.02 <- U27.13 <- U27.15 <- A16" },//
{ 4, 1, 1, 0, "A17",
"P8.46 <- J17.2 DATIN_1 <- U13.17 <- U13.03 <- U27.10 <- U27.12 <- A17" },//
"P8.46 <- J17.2 DATIN_1 <- U25.17 <- U25.03 <- U27.10 <- U27.12 <- A17" },//
{ 4, 2, 1, 0, "C0",
"P8.43 <- J17.3 DATIN_2 <- U13.16 <- U13.04 <- U27.03 <- U27.01 <- C0" },//
{ 4, 3, 1, 0, "C1",
@@ -543,23 +545,22 @@ buslatches_signal_info_t buslatches_signal_info[] = { //
};
// search a register bit by UNIBUS signal name and direction
buslatches_signal_info_t *buslatches_get_signal_info(const char *unibus_name,
unsigned is_input) {
buslatches_wire_info_t *buslatches_get_wire_info(const char *unibus_name, unsigned is_input) {
unsigned i;
buslatches_signal_info_t *si;
buslatches_wire_info_t *si;
for (i = 0; (si = &buslatches_signal_info[i]) && si->path; i++)
for (i = 0; (si = &buslatches_wire_info[i]) && si->path; i++)
if (si->is_input == is_input && !strcasecmp(si->unibus_name, unibus_name))
return si;
return NULL; // not found
}
// print info for a loop back mismatch bitmask
static void buslatches_print_signal_path(unsigned reg, unsigned mismatch_bitmask) {
static void buslatches_print_wire_path(unsigned reg, unsigned mismatch_bitmask) {
unsigned bit;
unsigned bitmask;
unsigned i;
buslatches_signal_info_t *si;
buslatches_wire_info_t *si;
for (bit = 0; bit < 8; bit++) {
bitmask = 1 << bit;
@@ -568,18 +569,17 @@ static void buslatches_print_signal_path(unsigned reg, unsigned mismatch_bitmask
printf("Signal path for bus latch %u, bit %u (mask 0x%02x):\n", reg, bit,
(1 << bit));
for (i = 0; (si = &buslatches_signal_info[i]) && si->path; i++)
for (i = 0; (si = &buslatches_wire_info[i]) && si->path; i++)
if (si->reg_sel == reg && !si->is_input && si->bit_nr == bit)
printf(" Write: %s\n", si->path);
for (i = 0; (si = &buslatches_signal_info[i]) && si->path; i++)
for (i = 0; (si = &buslatches_wire_info[i]) && si->path; i++)
if (si->reg_sel == reg && si->is_input && si->bit_nr == bit)
printf(" Read : %s\n", si->path);
}
}
}
// enable=1: activate UNIBUS drivers
// can be called BEFORE buslatches_init()
// activate AFTER RPU code started and reset bus latches values
void buslatches_output_enable(bool enable) {
enable = !!enable;
GPIO_SETVAL(gpios->bus_enable, enable);
@@ -589,14 +589,13 @@ void buslatches_output_enable(bool enable) {
// register signals to standard
// all outputs to standard:
// init state
// UNIBUS lines all H / only BR4567, NPR_OUT auf LOW
void buslatches_init() {
void buslatches_register() {
unsigned i;
// chips are all 8bit width, but not all input/outputs are
// connected to bidirektional terminated UNIBUs lines.
// see PCB schematic!
// chips are all 8bit width, but not all input/outputs are
// connected to bidirektional terminated UNIBUs lines.
// see PCB schematic!
buslatches.bidi_bitwidth[0] = 5; // BG4567, NPG
// LTC on .6 ignored, is input only
// LTC on .6 ignored, is input only
buslatches.bidi_bitwidth[1] = 7; // BR4..BR7,NPR,SACK,BBSY
buslatches.bidi_bitwidth[2] = 8; // addresses 0..7 ;
buslatches.bidi_bitwidth[3] = 8; // addresses 8..15
@@ -604,21 +603,26 @@ void buslatches_init() {
buslatches.bidi_bitwidth[5] = 8; // data 0..7
buslatches.bidi_bitwidth[6] = 8; // data 8..15
buslatches.bidi_bitwidth[7] = 6; // INTR,PA,PB,INIT,ACLO,DCLO
for (i = 0; i < 8; i++) {
for (i = 0; i < BUSLATCHES_COUNT; i++) {
buslatches.read_inverted[i] = false;
buslatches.bidi_bitmask[i] = BitmaskFromLen32[buslatches.bidi_bitwidth[i]];
}
// BG4567, NPG are read back non inverted from UNIBUS
// BG4567, NPG are read back non inverted from UNIBUS
buslatches.read_inverted[0] = true;
// PRU1 does it
}
// UNIBUS lines all H / only BR4567, NPR_OUT auf LOW
// PRU1 does it
void buslatches_pru_reset() {
assert(pru->prucode_id == pru_c::PRUCODE_TEST);
mailbox_execute(ARM2PRU_BUSLATCH_INIT, ARM2PRU_NONE);
}
// read the REG_DATIN[0..7] pins
// highly optimized, to reduce access to memory mapped gpio registers
unsigned buslatches_getval(unsigned reg_sel) {
// PRU1 does it
// PRU1 does it
mailbox->buslatch.addr = reg_sel;
while (mailbox->buslatch.addr != reg_sel)
; // cache !
@@ -629,7 +633,7 @@ unsigned buslatches_getval(unsigned reg_sel) {
}
// write the REG_DATOUT[0..7] pins into one latch
// only bits "bitmask" are written
// only bits "bitmask" are written. Other bits are cleared (PRU logic)
void buslatches_setval(unsigned reg_sel, unsigned bitmask, unsigned val) {
mailbox->buslatch.addr = reg_sel;
mailbox->buslatch.bitmask = bitmask & 0xff;
@@ -653,7 +657,7 @@ void buslatches_test_simple_pattern(unsigned pattern, unsigned reg_sel) {
unsigned idx, setval = 0, chkval;
unsigned bitwidth, bitmask;
unsigned count;
assert(reg_sel < 8);
assert(reg_sel < BUSLATCHES_COUNT);
bitwidth = buslatches.bidi_bitwidth[reg_sel];
bitmask = buslatches.bidi_bitmask[reg_sel];
@@ -675,9 +679,9 @@ void buslatches_test_simple_pattern(unsigned pattern, unsigned reg_sel) {
break;
}
// Setup ^C catcher
// Setup ^C catcher
SIGINTcatchnext();
// high speed loop
// high speed loop
idx = 0;
count = 0;
while (!SIGINTreceived) {
@@ -716,12 +720,13 @@ void buslatches_test_simple_pattern(unsigned pattern, unsigned reg_sel) {
if (chkval != setval) {
printf("pass %u test_register_simple_pattern(%d, %d): wrote 0x%x, read 0x%x\n",
count, pattern, reg_sel, setval, chkval);
if (reg_sel == 0) {
printf("Testing BR*,NPR with BG*,NPG feedback.\n");
printf("Are there 5*3 jumpers in the \"||\"\n");
printf(" \"--\" position?\n");
}
buslatches_print_signal_path(reg_sel, setval ^ chkval);
buslatches_print_wire_path(reg_sel, setval ^ chkval);
return;
}
count++;
@@ -729,39 +734,52 @@ void buslatches_test_simple_pattern(unsigned pattern, unsigned reg_sel) {
printf("\n%u tests successful.\n", count);
}
void buslatches_test_simple_pattern_multi(unsigned reg_first, unsigned reg_last,
unsigned pattern) {
unsigned reg_count = reg_last - reg_first + 1;
// shuffles entries in mailbox.exerciser work list
static void buslatches_exerciser_random_order() {
for (unsigned i = 0; i < 2 * BUSLATCHES_COUNT; i++) {
unsigned reg_sel1 = rand() % BUSLATCHES_COUNT;
unsigned reg_sel2 = rand() % BUSLATCHES_COUNT;
uint8_t tmp;
// swap addr and testval
tmp = mailbox->buslatch_exerciser.addr[reg_sel1];
mailbox->buslatch_exerciser.addr[reg_sel1] = mailbox->buslatch_exerciser.addr[reg_sel2];
mailbox->buslatch_exerciser.addr[reg_sel2] = tmp;
tmp = mailbox->buslatch_exerciser.writeval[reg_sel1];
mailbox->buslatch_exerciser.writeval[reg_sel1] =
mailbox->buslatch_exerciser.writeval[reg_sel2];
mailbox->buslatch_exerciser.writeval[reg_sel2] = tmp;
}
}
unsigned testno; // global test number counter
unsigned i;
unsigned testval[8]; // test data for all latches
void buslatches_test_simple_pattern_multi(unsigned pattern) {
unsigned pass_no; // global test number counter
uint64_t total_errors, total_tests;
unsigned reg_sel; // register address
unsigned testval[BUSLATCHES_COUNT]; // test data for all latches
switch (pattern) {
// case 1:
// printf("Highspeed count register latch %d, stop with ^C.\n", reg_sel);
// break;
case 2:
printf("Highspeed \"moving ones\" in register latches %d-%d, stop with ^C.\n",
reg_first, reg_last);
printf("Highspeed \"moving ones\" in register latches, stop with ^C.\n");
break;
case 3:
printf("Highspeed \"moving zeros\" in register latches %d-%d, stop with ^C.\n",
reg_first, reg_last);
printf("Highspeed \"moving zeros\" in register latches, stop with ^C.\n");
break;
case 4:
printf("Highspeed toggle 0x00 - 0xff in register latches %d-%d, stop with ^C.\n",
reg_first, reg_last);
printf("Highspeed toggle 0x00 - 0xff in register latches, stop with ^C.\n");
break;
case 5:
printf("Highspeed random values in register latches %d-%d, stop with ^C.\n", reg_first,
reg_last);
printf("Highspeed random values in register latches, stop with ^C.\n");
break;
default:
printf("Error: unknown test pattern %u.\n", pattern);
}
testno = 0;
pass_no = 0;
total_errors = 0;
total_tests = 0;
// Setup ^C catcher
SIGINTcatchnext();
@@ -770,74 +788,117 @@ void buslatches_test_simple_pattern_multi(unsigned reg_first, unsigned reg_last,
// 1 cycle = 8 bits of 8 registers
// some tests are no-op because of reduced bitwidth
/* 1. generate pattern */
for (i = reg_first; i <= reg_last; i++) {
switch (pattern) {
case 2: { // moving ones
unsigned bitidx = testno % 8; // circle all 8 bits per register
unsigned regidx = reg_first + ((testno / 8) % reg_count); // circle all registers
/* 1. generate pattern. Output: testval[reg_addr] */
switch (pattern) {
case 2: // moving ones, linear addressing
for (reg_sel = 0; reg_sel < BUSLATCHES_COUNT; reg_sel++) {
unsigned bitidx = pass_no % 8; // circle all 8 bits per register
unsigned regidx = (pass_no / 8) % BUSLATCHES_COUNT; // circle all registers
// set only one bit
if (i == regidx)
testval[i] = 1 << bitidx;
if (reg_sel == regidx)
testval[reg_sel] = 1 << bitidx;
else
testval[i] = 0;
break;
testval[reg_sel] = 0;
}
case 3: { // moving zeros
break;
case 3: // moving zeros, linear addressing
for (reg_sel = 0; reg_sel < BUSLATCHES_COUNT; reg_sel++) {
// clear only one bit
unsigned bitidx = testno % 8; // circle all 8 bits per register
unsigned regidx = reg_first + ((testno / 8) % reg_count); // circle all registers
if (i == regidx)
testval[i] = ~(1 << bitidx);
unsigned bitidx = pass_no % 8; // circle all 8 bits per register
unsigned regidx = (pass_no / 8) % BUSLATCHES_COUNT; // circle all registers
if (reg_sel == regidx)
testval[reg_sel] = ~(1 << bitidx);
else
testval[i] = 0xff;
break;
testval[reg_sel] = 0xff;
}
case 4: // toggle all regs simultaneously 0x00, 0xff, 0xff, ...
if (testno & 1)
testval[i] = 0xff;
break;
case 4: // toggle all regs simultaneously 0x00, 0xff, 0xff, ...
// linear addressing
for (reg_sel = 0; reg_sel < BUSLATCHES_COUNT; reg_sel++) {
if (pass_no & 1)
testval[reg_sel] = 0xff;
else
testval[i] = 0x00;
break;
case 5:
testval[i] = rand() & 0xff; // slow?
break;
default:
printf("Error: unknown test pattern %u.\n", pattern);
testval[reg_sel] = 0x00;
}
// mask out unimplemented bits
testval[i] &= buslatches.bidi_bitmask[i];
break;
case 5:
// random values, random addressing
for (reg_sel = 0; reg_sel < BUSLATCHES_COUNT; reg_sel++)
testval[reg_sel] = rand() & 0xff; // slow?
break;
default:
printf("Error: unknown test pattern %u.\n", pattern);
}
/* 2. write pattern into output latches.
* Also write unused bits */
for (i = reg_first; i <= reg_last; i++)
buslatches_setval(i, 0xff, testval[i]);
// mask out unimplemented bits
for (reg_sel = 0; reg_sel < BUSLATCHES_COUNT; reg_sel++)
testval[reg_sel] &= buslatches.bidi_bitmask[reg_sel];
/* 3. read back pattern in output latches over UNIBUS into input muxes */
for (i = reg_first; i <= reg_last; i++) {
unsigned bitmask = buslatches.bidi_bitmask[i];
unsigned chkval = buslatches_getval(i);
if (buslatches.read_inverted[i])
chkval = ~chkval; // input latches invert
chkval &= bitmask;
if (chkval != testval[i]) {
// Setup mailbox for PRU buslatch exerciser
// it tests always 8 accesses
for (reg_sel = 0; reg_sel < BUSLATCHES_COUNT; reg_sel++) {
mailbox->buslatch_exerciser.addr[reg_sel] = reg_sel;
mailbox->buslatch_exerciser.writeval[reg_sel] = testval[reg_sel];
mailbox->buslatch_exerciser.readval[reg_sel] = 0xff; // invalid at the moment
}
// shuffle worklist to create random access order
buslatches_exerciser_random_order();
// alternatingly use byte or bit access procedures
// unindented synchronoized with moving one/moving zero or other peridioc tests
mailbox->buslatch_exerciser.pattern = (pass_no
% MAILBOX_BUSLATCH_EXERCISER_PATTERN_COUNT);
mailbox_execute(ARM2PRU_BUSLATCH_EXERCISER, ARM2PRU_NONE);
// check: mailbox readvalues == write values ?
for (unsigned i = 0; i < BUSLATCHES_COUNT; i++) {
reg_sel = mailbox->buslatch_exerciser.addr[i];
unsigned writeval = mailbox->buslatch_exerciser.writeval[i];
unsigned readval = mailbox->buslatch_exerciser.readval[i];
unsigned bitmask = buslatches.bidi_bitmask[reg_sel];
total_tests++;
if (buslatches.read_inverted[reg_sel])
readval = ~readval; // input latches invert
readval &= bitmask;
if (readval != writeval) {
total_errors++;
printf(
"Error buslatches_test_simple_pattern_multi(regs=%u-%u,pattern=%d), pass %u:\n",
reg_first, reg_last, pattern, testno);
printf(" register %u: wrote 0x%x, read back 0x%x\n", i, testval[i], chkval);
if (i == 0) {
"Error buslatches_test_simple_pattern_multi(pattern=%d), pass %u, pattern = %d:\n",
pattern, pass_no, (unsigned) mailbox->buslatch_exerciser.pattern);
printf(" register %u: wrote 0x%x, read back 0x%x, error bit mask 0x%02x\n",
reg_sel, writeval, readval, writeval ^ readval);
if (i == 0)
printf(" No prev addr/val history\n");
else {
// prinout previous test data. for access pattern see "pattern" and sourcecode
printf(" Prev addr/val history:");
for (unsigned j = 0; j < i; j++)
printf(" %u/0x%02x", mailbox->buslatch_exerciser.addr[j],
mailbox->buslatch_exerciser.writeval[j]);
printf(".\n");
}
if (reg_sel == 0) {
printf("Testing BR*,NPR with BG*,NPG feedback.\n");
printf("Are there 5*3 jumpers in the \"||\"\n");
printf(" \"--\" position?\n");
}
buslatches_print_signal_path(i, testval[i] ^ chkval);
return;
buslatches_print_wire_path(reg_sel, writeval ^ readval);
printf("%llu of %llu tests failed, error rate = %0.5f%% = %gppm)\n\n",
total_errors, total_tests, 100.0 * total_errors / total_tests,
1000000.0 * total_errors / total_tests);
}
}
testno++;
pass_no++;
}
printf("\n%u tests successful.\n", testno);
if (total_errors == 0)
printf("\n%llu tests successful.\n", total_tests);
else
printf("\n%llu of %llu tests failed, error rate = %0.5f%% = %gppm)\n", total_errors,
total_tests, 100.0 * total_errors / total_tests,
1000000.0 * total_errors / total_tests);
}
/* stress test on highspeed timing
@@ -862,7 +923,7 @@ void buslatches_test_timing(uint8_t addr_0_7, uint8_t addr_8_15, uint8_t data_0_
mailbox->buslatch_test.data_0_7 = data_0_7;
mailbox->buslatch_test.data_8_15 = data_8_15;
// Setup ^C catcher
// Setup ^C catcher
SIGINTcatchnext();
mailbox->arm2pru_req = ARM2PRU_BUSLATCH_TEST; // start PRU test loop
@@ -870,7 +931,7 @@ void buslatches_test_timing(uint8_t addr_0_7, uint8_t addr_8_15, uint8_t data_0_
while (!SIGINTreceived) {
timeout.wait_ms(0);
}
// stop PRU loop by settting something != ARM2PRU_BUSLATCH_TEST
// stop PRU loop by settting something != ARM2PRU_BUSLATCH_TEST
mailbox->arm2pru_req = ARM2PRU_BUSLATCH_INIT; //
timeout.wait_ms(1);
if (mailbox->arm2pru_req != ARM2PRU_NONE)
@@ -879,3 +940,205 @@ void buslatches_test_timing(uint8_t addr_0_7, uint8_t addr_8_15, uint8_t data_0_
printf("PRU test loop stopped.\n");
}
/**** GPIO access to UNIBUS sigbals ****/
unibus_signals_c *unibus_signals; // singleton
unibus_signal_info_c::unibus_signal_info_c(enum unibus_signal_info_c::id_enum id, string name,
unsigned bitwidth) {
this->id = id;
this->name = name;
this->bitwidth = bitwidth;
}
unibus_signals_c::unibus_signals_c() {
// fill dictionary
// order like in DEC manual
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_address, "ADDR", 18));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_data, "DATA", 16));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_control, "C1,C0", 2));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_msyn, "MSYN", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_ssyn, "SSYN", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_pa, "PA", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_pb, "PB", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_intr, "INTR", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_br4, "BR4", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_br5, "BR5", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_br6, "BR6", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_br7, "BR7", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_bg4, "BG4", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_bg5, "BG5", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_bg6, "BG6", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_bg7, "BG7", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_npr, "NPR", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_npg, "NPG", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_sack, "SACK", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_bbsy, "BBSY", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_init, "INIT", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_aclo, "ACLO", 1));
signals.push_back(unibus_signal_info_c(unibus_signal_info_c::ub_dclo, "DCLO", 1));
}
unsigned unibus_signals_c::max_name_len() {
return 5; // see above
}
unsigned unibus_signals_c::size() {
return signals.size();
}
void unibus_signals_c::set_val(enum unibus_signal_info_c::id_enum id, unsigned value) {
switch (id) {
case unibus_signal_info_c::ub_address:
buslatches_setval(2, 0xff, value); // ADDR0:7
buslatches_setval(3, 0xff, value >> 8); // ADDR8:15
buslatches_setval(4, 0x03, value >> 12); // ADDR16,17
break;
case unibus_signal_info_c::ub_data:
buslatches_setval(5, 0xff, value); // DATA0:7
buslatches_setval(6, 0xff, value >> 8); // DATA8:15
break;
case unibus_signal_info_c::ub_control:
buslatches_setval(4, 0x0C, value << 2); // C1 = 0x8, C0 = 0x4
break;
case unibus_signal_info_c::ub_msyn:
buslatches_setval(4, 0x10, value << 4); // MSYN = 0x10
break;
case unibus_signal_info_c::ub_ssyn:
buslatches_setval(4, 0x20, value << 5); // ssyn=0x20
break;
case unibus_signal_info_c::ub_pa:
buslatches_setval(7, 0x02, value << 1);
break;
case unibus_signal_info_c::ub_pb:
buslatches_setval(7, 0x04, value << 2);
break;
case unibus_signal_info_c::ub_intr:
buslatches_setval(7, 0x01, value);
break;
case unibus_signal_info_c::ub_br4:
buslatches_setval(1, 0x01, value);
break;
case unibus_signal_info_c::ub_br5:
buslatches_setval(1, 0x02, value << 1);
break;
case unibus_signal_info_c::ub_br6:
buslatches_setval(1, 0x04, value << 2);
break;
case unibus_signal_info_c::ub_br7:
buslatches_setval(1, 0x08, value << 3);
break;
case unibus_signal_info_c::ub_bg4:
buslatches_setval(0, 0x01, !value);
break;
case unibus_signal_info_c::ub_bg5:
buslatches_setval(0, 0x02, (!value) << 1);
break;
case unibus_signal_info_c::ub_bg6:
buslatches_setval(0, 0x04, (!value) << 2);
break;
case unibus_signal_info_c::ub_bg7:
buslatches_setval(0, 0x08, (!value) << 3);
break;
case unibus_signal_info_c::ub_npr:
buslatches_setval(1, 0x10, value << 4);
break;
case unibus_signal_info_c::ub_npg:
buslatches_setval(0, 0x10, (!value) << 4);
break;
case unibus_signal_info_c::ub_sack:
buslatches_setval(1, 0x20, value << 5);
break;
case unibus_signal_info_c::ub_bbsy:
buslatches_setval(1, 0x40, value << 6);
break;
case unibus_signal_info_c::ub_init:
buslatches_setval(7, 0x08, value << 3);
break;
case unibus_signal_info_c::ub_aclo:
buslatches_setval(7, 0x10, value << 4);
break;
case unibus_signal_info_c::ub_dclo:
buslatches_setval(7, 0x20, value << 5);
break;
}
}
unsigned unibus_signals_c::get_val(enum unibus_signal_info_c::id_enum id) {
unsigned result = 0;
switch (id) {
case unibus_signal_info_c::ub_address:
result = buslatches_getval(2); // ADDR0:7
result |= buslatches_getval(3) << 8; // ADDR8:15
result |= (buslatches_getval(4) & 0x03) << 16; // ADDR8:15
break;
case unibus_signal_info_c::ub_data:
result = buslatches_getval(5); // DATA0:7
result |= buslatches_getval(6) << 8; // DATA8:15
break;
case unibus_signal_info_c::ub_control:
result = (buslatches_getval(4) & 0x0c) >> 2; // C1 = 0x8, C0 = 0x4
break;
case unibus_signal_info_c::ub_msyn:
result = (buslatches_getval(4) & 0x10) >> 4; // MSYN = 0x10
break;
case unibus_signal_info_c::ub_ssyn:
result = (buslatches_getval(4) & 0x20) >> 5; // ssyn=0x20
break;
case unibus_signal_info_c::ub_pa:
result = (buslatches_getval(7) & 0x02) >> 1;
break;
case unibus_signal_info_c::ub_pb:
result = (buslatches_getval(7) & 0x04) >> 2;
break;
case unibus_signal_info_c::ub_intr:
result = (buslatches_getval(7) & 0x01);
break;
case unibus_signal_info_c::ub_br4:
result = (buslatches_getval(1) & 0x01);
break;
case unibus_signal_info_c::ub_br5:
result = (buslatches_getval(1) & 0x02) >> 1;
break;
case unibus_signal_info_c::ub_br6:
result = (buslatches_getval(1) & 0x04) >> 2;
break;
case unibus_signal_info_c::ub_br7:
result = (buslatches_getval(1) & 0x08) >> 3;
break;
case unibus_signal_info_c::ub_bg4:
result = !(buslatches_getval(0) & 0x01);
break;
case unibus_signal_info_c::ub_bg5:
result = !(buslatches_getval(0) & 0x02) >> 1;
break;
case unibus_signal_info_c::ub_bg6:
result = !(buslatches_getval(0) & 0x04) >> 2;
break;
case unibus_signal_info_c::ub_bg7:
result = !(buslatches_getval(0) & 0x08) >> 3;
break;
case unibus_signal_info_c::ub_npr:
result = (buslatches_getval(1) & 0x10) >> 4;
break;
case unibus_signal_info_c::ub_npg:
result = !(buslatches_getval(0) & 0x10) >> 4;
break;
case unibus_signal_info_c::ub_sack:
result = (buslatches_getval(1) & 0x20) >> 5;
break;
case unibus_signal_info_c::ub_bbsy:
result = (buslatches_getval(1) & 0x40) >> 6;
break;
case unibus_signal_info_c::ub_init:
result = (buslatches_getval(7) & 0x08) >> 3;
break;
case unibus_signal_info_c::ub_aclo:
result = (buslatches_getval(7) & 0x10) >> 4;
break;
case unibus_signal_info_c::ub_dclo:
result = (buslatches_getval(7) & 0x20) >> 5;
break;
}
return result;
}

76
10.01_base/2_src/arm/gpios.hpp
View File

@@ -117,21 +117,24 @@ public:
void test_loopback(void);
};
#define BUSLATCHES_COUNT 8
// save current state uf gpios and registers,
// to suppress redundant write accesses
typedef struct {
// # of bits in each register connected bidirectionally to UNIBUS
// ( for example, LTC ignored)
unsigned bidi_bitwidth[8]; // # of bits in each
unsigned bidi_bitmask[8]; // mask with valid bits
unsigned bidi_bitwidth[BUSLATCHES_COUNT]; // # of bits in each
unsigned bidi_bitmask[BUSLATCHES_COUNT]; // mask with valid bits
bool read_inverted[8]; // true: read back inverted with respect to write levels
bool read_inverted[BUSLATCHES_COUNT]; // true: read back inverted with respect to write levels
// current signal state, used for optimization
unsigned cur_output_enable; // state of ENABLE
unsigned cur_reg_sel; // state of SEL A0,A1,A2
unsigned cur_reg_val[8]; // content of output latches
unsigned cur_reg_val[BUSLATCHES_COUNT]; // content of output latches
} buslatches_t;
extern gpios_c *gpios; // singleton
@@ -160,6 +163,7 @@ extern buslatches_t buslatches;
: (!! ( *((gpio)->bank->datain_addr) & (gpio)->pin_in_bank_mask ) ) \
)
// raw 1 bit signal traces
typedef struct {
unsigned reg_sel;
unsigned bit_nr;
@@ -167,21 +171,71 @@ typedef struct {
unsigned is_inverted; // only BG*_OUT
const char *unibus_name; // UNIBUS signal name
const char *path; // long info with net list
} buslatches_signal_info_t;
} buslatches_wire_info_t;
extern buslatches_signal_info_t buslatches_signal_info[];
extern buslatches_wire_info_t buslatches_wire_info[];
// compound unibus signals
class unibus_signal_info_c {
public:
enum id_enum {
ub_address, ub_data, ub_control, // c1,c0
ub_msyn,
ub_ssyn,
ub_pa,
ub_pb,
ub_intr,
ub_br4,
ub_br5,
ub_br6,
ub_br7,
ub_bg4,
ub_bg5,
ub_bg6,
ub_bg7,
ub_npr,
ub_npg,
ub_sack,
ub_bbsy,
ub_init,
ub_aclo,
ub_dclo
};
id_enum id;
string name;
unsigned bitwidth;
unibus_signal_info_c() {
}
;
unibus_signal_info_c(id_enum id, string name, unsigned bitwidth);
};
class unibus_signals_c {
public:
unibus_signals_c();
vector<unibus_signal_info_c> signals;
unsigned max_name_len();
unsigned size();
void set_val(enum unibus_signal_info_c::id_enum id, unsigned value);
unsigned get_val(enum unibus_signal_info_c::id_enum id);
};
extern unibus_signals_c *unibus_signals; // singleton
void buslatches_output_enable(bool enable);
void buslatches_init(void);
buslatches_signal_info_t *buslatches_get_signal_info(const char * unibus_name,
unsigned is_input);
void buslatches_register(void);
void buslatches_pru_reset(void);
buslatches_wire_info_t *buslatches_get_wire_info(const char * unibus_name, unsigned is_input);
void buslatches_setval(unsigned reg_sel, unsigned bitmask, unsigned val);
unsigned buslatches_getval(unsigned reg_sel);
void buslatches_test_simple_pattern(unsigned pattern, unsigned reg_sel);
void buslatches_test_simple_pattern_multi(unsigned reg_first, unsigned reg_last,
unsigned pattern);
void buslatches_test_simple_pattern_multi( unsigned pattern);
void buslatches_test_timing(uint8_t addr_0_7, uint8_t addr_8_15, uint8_t data_0_7,
uint8_t data_8_15);

5
10.01_base/2_src/arm/iopageregister.cpp
View File

@@ -28,8 +28,9 @@
#include <stdio.h>
#include <string.h>
#include "prussdrv.h"
#include "pru1_config.h"
#include "pru.hpp"
//#include "pru1_config.h"
#include "iopageregister.h"
// Device register struct shared between PRU and ARM.

20
10.01_base/2_src/arm/mailbox.cpp
View File

@@ -28,18 +28,21 @@
#define _MAILBOX_CPP_
#include <stdio.h>
#include <string.h>
#include "prussdrv.h"
#include "pru.hpp"
#include "logger.hpp"
#include "ddrmem.h"
#include "mailbox.h"
#include "pru1_config.h"
// is located in PRU 12kb shared memory.
// address symbol "" fetched from linker map
volatile mailbox_t *mailbox;
// Init all fields, most to 0's
int mailbox_connect(void) {
void *pru_shared_dataram;
// get pointer to RAM
@@ -54,12 +57,16 @@ int mailbox_connect(void) {
// now ARM and PRU can access the mailbox
memset((void*)mailbox, 0, sizeof(mailbox_t)) ;
// tell PRU location of shared DDR RAM
mailbox->ddrmem_base_physical = (ddrmem_t *) ddrmem->base_physical;
return 0;
}
void mailbox_print(void) {
printf("INFO: Content of mailbox to PRU:\n"
"arm2pru: req=0x%x, resp=0x%x\n", mailbox->arm2pru_req, mailbox->arm2pru_resp);
@@ -98,10 +105,19 @@ void mailbox_test1() {
/* start cmd to PRU via mailbox. Wait until ready
* mailbox union members must have been filled
*/
uint32_t xxx ;
void mailbox_execute(uint8_t request, uint8_t stopcode) {
// write to arm2pru_req must be last memory operation
__sync_synchronize();
mailbox->arm2pru_req = request; // go!
do {
xxx = mailbox-> arm2pru_req ;
if (mailbox->events.eventmask) {
// event not processed? will hang DMA.
// printf("WARNING: Unprocessed mailbox.events.eventmask = 0x%x\n", (unsigned) mailbox->events.eventmask) ;
// mailbox->events.eventmask = 0 ;
}
} while (xxx != stopcode) ;
while (mailbox->arm2pru_req != stopcode)
; // wait until processed
}

19
10.01_base/2_src/arm/memoryimage.cpp
View File

@@ -45,7 +45,6 @@
#include <assert.h>
#include "logger.hpp"
#include "main.h" // own
#include "memoryimage.hpp" // own
// single multi purpose memory image buffer
@@ -130,12 +129,10 @@ void memoryimage_c::put_byte(unsigned addr, unsigned b) {
*/
bool memoryimage_c::load_binary(const char *fname) {
FILE *fin;
char linebuff[1024];
unsigned wordidx, n;
fin = fopen(fname, "rb");
if (!fin) {
sprintf(linebuff, "Error opening file %s for read", fname);
perror(linebuff);
printf("%s\n",fileErrorText("Error opening file %s for read", fname));
return false;
}
// try to read max address range, shorter files are OK
@@ -148,13 +145,11 @@ bool memoryimage_c::load_binary(const char *fname) {
void memoryimage_c::save_binary(const char *fname, unsigned bytecount) {
FILE *fout;
char linebuff[1024];
unsigned wordcount = (bytecount + 1) / 2;
unsigned n;
fout = fopen(fname, "wb");
if (!fout) {
sprintf(linebuff, "Error opening file %s for write", fname);
perror(linebuff);
printf("%s\n",fileErrorText("Error opening file %s for write", fname));
return;
}
// try to read max address range, shorter files are OK
@@ -209,8 +204,7 @@ bool memoryimage_c::load_addr_value_text(const char *fname) {
fin = fopen(fname, "r");
if (!fin) {
sprintf(linebuff, "Error opening file %s", fname);
perror(linebuff);
printf("%s\n", fileErrorText("Error opening file %s for write", fname)) ;
return false;
}
entry_address = MEMORY_ADDRESS_INVALID; // not known
@@ -446,8 +440,7 @@ bool memoryimage_c::load_macro11_listing(const char *fname, const char *entrylab
fin = fopen(fname, "r");
if (!fin) {
sprintf(linebuff, "Error opening file %s", fname);
perror(linebuff);
printf("%s\n", fileErrorText("Error opening file %s", fname));
return false;
}
entry_address = MEMORY_ADDRESS_INVALID; // not (yet) known
@@ -538,9 +531,7 @@ bool memoryimage_c::load_papertape(const char *fname) {
fin = fopen(fname, "r");
if (!fin) {
char buff[1024];
sprintf(buff, "Error opening file %s", fname);
perror(buff);
printf("%s\n", fileErrorText("Error opening file %s for read", fname));
return false;
}

168
10.01_base/2_src/arm/pru.cpp
View File

@@ -1,27 +1,27 @@
/* pru.cpp: Management interface to PRU0 & PRU1.
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
12-nov-2018 JH entered beta phase
Management interface to PRU0 & 1:
- setup interrupt
@@ -29,7 +29,13 @@
Partly copyright (c) 2014 dhenke@mythopoeic.org
usage: sudo ./example
PRU progam code:
For different UniBone operation modes special program code is used for PRU0 nad PRU1 each.
One single omnipotent program code can not be used due to 2K code space limit.
ARM code asu to reload appropriate PRU program code according to current function
(PRU selftest, UNIBUS slave, UNIBUS master, logic analyzer, etc.)
***/
#define _PRU_CPP_
@@ -37,9 +43,11 @@
#include <stdlib.h>
#include <stdint.h>
#include <unistd.h>
#include <assert.h>
#include <fcntl.h>
#include "utils.hpp"
#include "logger.hpp"
#include "prussdrv.h"
#include "pruss_intc_mapping.h"
@@ -49,23 +57,37 @@
#include "pru.hpp"
#define PRUSS_MAX_IRAM_SIZE 8192
/*** PRU code arrays generated by clpru / hexpru ***
Program code is generated by "lcpru" and "hexpru --array" as C-array source code.
// Array with program code for PRU
// generated by 'hexpru --array'
#include "pru0_config.h"
#include "pru1_config.h"
#define PRU0_CODE_IMAGE pru0_image_0 // name of bianry array in include
#define PRU1_CODE_IMAGE pru1_image_0 // name of bianry array in include
These arrays are included here and wrapped for use by ARM/C++ classes.
Format:
const uint32_t target_image_0[] = {
0x240000c0,
..
0x20c30000};
const uint8_t target_image_1[] = {
0x01,
...
0x00};
*/
// under c++ linker error with const attribute ?!
#define const
#include "pru0_code_all_array.c"
#include "pru1_code_test_array.c"
#include "pru1_code_unibus_array.c"
#undef const
// Singleton
pru_c *pru ;
pru_c *pru;
pru_c::pru_c() {
log_label = "PRU" ;
prucode_id = PRUCODE_NONE;
log_label = "PRU";
}
/*** pru_setup() -- initialize PRU and interrupt handler
Initializes both PRUs and sets up PRU_EVTOUT_0 handler.
@@ -75,26 +97,59 @@ pru_c::pru_c() {
Returns 0 on success, non-0 on error.
***/
int pru_c::setup() {
// entry for one program code variant for both PRUs
struct prucode_entry {
unsigned id;
// ptr to PRU0 code array generated by clpru
uint32_t *pru0_code_array;
unsigned pru0_code_array_sizeof;
uint32_t pru0_entry;
// smame for PRU1
uint32_t *pru1_code_array;
unsigned pru1_code_array_sizeof;
uint32_t pru1_entry;
// properties required for certain functions
};
// local static dictionary of program code variants
struct prucode_entry prucode[] = {
// self test functions
{ pru_c::PRUCODE_TEST, //
pru0_code_all_image_0, sizeof(pru0_code_all_image_0), PRU0_ENTRY_ADDR, //
pru1_code_test_image_0, sizeof(pru1_code_test_image_0), PRU1_ENTRY_ADDR //
},//
{ pru_c::PRUCODE_UNIBUS, //
pru0_code_all_image_0, sizeof(pru0_code_all_image_0), PRU0_ENTRY_ADDR, //
pru1_code_unibus_image_0, sizeof(pru1_code_unibus_image_0), PRU1_ENTRY_ADDR //
},//
// end marker
{ pru_c::PRUCODE_EOD, NULL, 0, 0, NULL, 0, 0 } };
int pru_c::start(enum prucode_enum prucode_id) {
timeout_c timeout;
int rtn;
tpruss_intc_initdata intc = PRUSS_INTC_INITDATA;
// use stop() before restart()
assert(this->prucode_id == PRUCODE_NONE);
/* initialize PRU */
if ((rtn = prussdrv_init()) != 0) {
ERROR("prussdrv_init() failed");
return rtn;
goto error;
}
/* open the interrupt */
if ((rtn = prussdrv_open(PRU_EVTOUT_0)) != 0) {
ERROR("prussdrv_open() failed");
return rtn;
goto error;
}
/* initialize interrupt */
if ((rtn = prussdrv_pruintc_init(&intc)) != 0) {
ERROR("prussdrv_pruintc_init() failed");
return rtn;
goto error;
}
/*
@@ -110,46 +165,63 @@ int pru_c::setup() {
ddrmem->base_physical = prussdrv_get_phys_addr((void *) (ddrmem->base_virtual));
ddrmem->info(); // may abort program
/* load code from arrays PRU*_code[] into PRU and start at 0
// search code in dictionary
struct prucode_entry *pce;
for (pce = prucode; pce->id != prucode_id && pce->id != PRUCODE_EOD; pce++)
;
if (pce->id == PRUCODE_EOD)
FATAL("PRU program code for config %u not found", pce->id);
/* load code from arrays PRU*_code[] into PRU and start at 0
*/
if (pru0_sizeof_code() > PRUSS_MAX_IRAM_SIZE) {
if (pce->pru0_code_array_sizeof > PRUSS_MAX_IRAM_SIZE) {
FATAL("PRU0 code too large. Closing program");
}
if ((rtn = prussdrv_exec_code_at(0, PRU0_CODE_IMAGE, pru0_sizeof_code(), PRU0_ENTRY_ADDR))
!= 0) {
ERROR("prussdrv_exec_program() failed");
return rtn;
if ((rtn = prussdrv_exec_code_at(0, pce->pru0_code_array, pce->pru0_code_array_sizeof,
pce->pru0_entry)) != 0) {
FATAL("prussdrv_exec_program(PRU0) failed");
goto error;
}
if (pru1_sizeof_code() > PRUSS_MAX_IRAM_SIZE) {
FATAL("PRU1 code too large. Closing program");
exit(1);
if (pce->pru1_code_array_sizeof > PRUSS_MAX_IRAM_SIZE) {
FATAL("PRU1 code too large.");
}
if ((rtn = prussdrv_exec_code_at(1, PRU1_CODE_IMAGE, pru1_sizeof_code(), PRU1_ENTRY_ADDR))
!= 0) {
ERROR("prussdrv_exec_program() failed");
return rtn;
if ((rtn = prussdrv_exec_code_at(1, pce->pru1_code_array, pce->pru1_code_array_sizeof,
pce->pru1_entry)) != 0) {
FATAL("prussdrv_exec_program(PRU1) failed");
}
INFO("Loaded pru code with id = %d", prucode_id);
sleep(1); // wait for PRU to come up, much too long
timeout.wait_ms(100); // wait for PRU to come up, much too long
// get address of mail box struct in PRU
mailbox_connect();
// now all fields initialized/cleared
// get address of device register descriptor struct in PRU
iopageregisters_connect();
this->prucode_id = prucode_id;
return rtn;
error: //
pru->stop();
FATAL("Could not connect to PRU.\n"
"- Correct Device Tree Overlay loaded?\n"
"- Check also /sys/class/uio/uio*.");
return rtn; // not reached
}
/*** pru_cleanup() -- halt PRU and release driver
/*** pru_c::stop() -- halt PRU and release driver
Performs all necessary de-initialization tasks for the prussdrv library.
Returns 0 on success, non-0 on error.
***/
int pru_c::cleanup(void) {
int pru_c::stop(void) {
int rtn = 0;
prucode_id = PRUCODE_NONE;
/* clear the event (if asserted) */
if (prussdrv_pru_clear_event(PRU_EVTOUT_0, PRU0_ARM_INTERRUPT)) {

50
10.01_base/2_src/arm/pru.hpp
View File

@@ -31,19 +31,65 @@
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
18-apr-2019 JH added PRU code dictionary
12-nov-2018 JH entered beta phase
*/
#ifndef _PRU_HPP_
#define _PRU_HPP_
#include <stdint.h>
#include "prussdrv.h"
#include "logsource.hpp"
/*** PRU Shared addresses ***/
// Mailbox page & offset in PRU internal shared 12 KB RAM
// Accessible by both PRUs, must be located in shared RAM
// offset 0 == addr 0x10000 in linker cmd files for PRU0 AND PRU1 projects.
// For use with prussdrv_map_prumem()
#define PRUSS_MAX_IRAM_SIZE 8192
// all entry addresses at 0
// code entry point "_c_int00_noinit_noargs" from linker map file:
#define PRU0_ENTRY_ADDR 0x00000000
#define PRU1_ENTRY_ADDR 0x00000000
#ifndef PRU_MAILBOX_RAM_ID
#define PRU_MAILBOX_RAM_ID PRUSS0_SHARED_DATARAM
#define PRU_MAILBOX_RAM_OFFSET 0
#endif
// Device register page & offset in PRU0 8KB RAM mapped into PRU1 space
// offset 0 == addr 0x2000 in linker cmd files for PRU1 projects.
// For use with prussdrv_map_prumem()
#ifndef PRU_DEVICEREGISTER_RAM_ID
#define PRU_DEVICEREGISTER_RAM_ID PRUSS0_PRU0_DATARAM
#define PRU_DEVICEREGISTER_RAM_OFFSET 0
#endif
class pru_c: public logsource_c {
public:
// IDs for code variants, so callers can select one
enum prucode_enum {
PRUCODE_EOD = 0, // special marker: end of dictionary
PRUCODE_NONE = 0, // no code running, RPU reset
PRUCODE_TEST = 1, // only selftest functions
PRUCODE_UNIBUS = 2 // regular UNIBUS operation
// with or without physical CPU for arbitration
} ;
public:
enum prucode_enum prucode_id ; // currently running code
pru_c();
int setup(void);
int cleanup(void);
int start(enum prucode_enum prucode_id);
int stop(void);
};
extern pru_c *pru; // singleton

190
10.01_base/2_src/arm/storagedrive.cpp
View File

@@ -1,31 +1,32 @@
/* storagedrive.cpp: disk or tape drive, with an image file as storage medium.
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
may-2019 JD file_size()
12-nov-2018 JH entered beta phase
A storagedrive is a disk or tape drive, with an image file as storage medium.
a couple of these are connected to a single "storagecontroler"
supports the "attach" command
A storagedrive is a disk or tape drive, with an image file as storage medium.
a couple of these are connected to a single "storagecontroler"
supports the "attach" command
*/
#include <assert.h>
@@ -48,12 +49,10 @@ storagedrive_c::storagedrive_c(storagecontroller_c *controller) :
// implements params, so must handle "change"
bool storagedrive_c::on_param_changed(parameter_c *param) {
UNUSED(param) ;
return true ;
UNUSED(param);
return true;
}
// http://www.cplusplus.com/doc/tutorial/files/
// open a file, if possible.
@@ -113,41 +112,138 @@ void storagedrive_c::file_read(uint8_t *buffer, uint64_t position, unsigned len)
* if file too short, it is extended
*/
void storagedrive_c::file_write(uint8_t *buffer, uint64_t position, unsigned len) {
// uint8_t *fillbuff;
int64_t write_pos = (int64_t) position; // unsigned-> int
const int max_chunk_size = 0x40000; //256KB: trade-off between performance and mem usage
uint8_t *fillbuff = NULL;
int64_t file_size, p;
assert(file_is_open());
assert(!file_readonly); // caller must take care
/*
// get current file size
f.seekp(0, ios::end) ; // move to end
p = f.tellp(); // current file len
// fill 00s until 'pos' reached
if (p == -1)
p = 0 ;
if (p < offset) {
unsigned fillcount = offset - p; // 00's to write
// extedn file with 00's
fillbuff = (uint8_t *) malloc(fillcount);
memset(fillbuff, 0, fillcount);
f.write((const char *)fillbuff, fillcount);
free(fillbuff);
}
*/
// move write pointer to target position
f.seekp(position);
// enlarge file in chunks until filled up to "position"
f.clear() ; // clear fail bit
f.seekp(0, ios::end); // move to current EOF
file_size = f.tellp(); // current file len
if (file_size < 0)
file_size = 0 ; // -1 on emtpy files
while (file_size < write_pos) {
// fill in '00' 'chunks up to desired end, but limit to max_chunk_size
int chunk_size = std::min(max_chunk_size, (int) (write_pos - file_size));
if (!fillbuff) {
// allocate 00-buffer only once
fillbuff = (uint8_t *) malloc(max_chunk_size);
assert(fillbuff);
memset(fillbuff, 0, max_chunk_size);
}
f.clear() ; // clear fail bit
f.seekp(file_size, ios::beg); // move to end
f.write((const char *) fillbuff, chunk_size);
file_size += chunk_size;
}
if (fillbuff)
free(fillbuff); // has been used, discard
// p = f.tellp(); // position now < target?
// p = -1 after seekp(0) ??? Some discussion about this!
// assert(p == (int64_t )position);
if (file_size == 0)
// p = -1 error after seekp(0) on empty files?
assert(write_pos == 0);
else {
// move write pointer to target position
f.clear() ; // clear fail bit
f.seekp(write_pos, ios::beg);
p = f.tellp(); // position now < target?
assert(p == write_pos);
}
// 3. write data
f.write((const char*) buffer, len);
if (f.fail())
ERROR("file_write() failure on %s", name);
f.flush();
}
uint64_t storagedrive_c::file_size(void) {
f.seekp(0, ios::end);
return f.tellp();
}
void storagedrive_c::file_close(void) {
assert(file_is_open());
f.close();
file_readonly = false ;
file_readonly = false;
}
// fill buffer with test data to be placed at "file_offset"
void storagedrive_selftest_c::block_buffer_fill(unsigned block_number) {
assert((block_size % 4) == 0); // whole uint32
for (unsigned i = 0; i < block_size / 4; i++) {
// i counts dwords in buffer
// pattern: global incrementing uint32
uint32_t pattern = i + (block_number * block_size / 4);
((uint32_t*) block_buffer)[i] = pattern;
}
}
// verify pattern generated by fillbuff
void storagedrive_selftest_c::block_buffer_check(unsigned block_number) {
assert((block_size % 4) == 0); // whole uint32
for (unsigned i = 0; i < block_size / 4; i++) {
// i counts dwords in buffer
// pattern: global incrementing uint32
uint32_t pattern_expected = i + (block_number * block_size / 4);
uint32_t pattern_found = ((uint32_t*) block_buffer)[i];
if (pattern_expected != pattern_found) {
printf(
"ERROR storage_drive selftest: Block %d, dword %d: expected 0x%x, found 0x%x\n",
block_number, i, pattern_expected, pattern_found);
exit(1);
}
}
}
// self test of random access file interface
// test file has 'block_count' blocks with 'block_size' bytes capacity each.
void storagedrive_selftest_c::test() {
unsigned i;
bool *block_touched = (bool *) malloc(block_count * sizeof(bool)); // dyn array
int blocks_to_touch;
/*** fill all blocks with random accesses, until all blcoks touched ***/
file_open(imagefname, true);
for (i = 0; i < block_count; i++)
block_touched[i] = false;
blocks_to_touch = block_count;
while (blocks_to_touch > 0) {
unsigned block_number = random() % block_count;
block_buffer_fill(block_number);
file_write(block_buffer, /*position*/block_size * block_number, block_size);
if (!block_touched[block_number]) { // mark
block_touched[block_number] = true;
blocks_to_touch--;
}
}
file_close();
/*** verify all blocks with random accesses, until all blcoks touched ***/
file_open(imagefname, true);
for (i = 0; i < block_count; i++)
block_touched[i] = false;
blocks_to_touch = block_count;
while (blocks_to_touch > 0) {
unsigned block_number = random() % block_count;
file_read(block_buffer, /*position*/block_size * block_number, block_size);
block_buffer_check(block_number);
if (!block_touched[block_number]) { // mark
block_touched[block_number] = true;
blocks_to_touch--;
}
}
file_close();
free(block_touched);
}

85
10.01_base/2_src/arm/storagedrive.hpp
View File

@@ -1,27 +1,27 @@
/* storagedrive.hpp: disk or tape drive, with an image file as storage medium.
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
may-2019 JD file_size()
12-nov-2018 JH entered beta phase
*/
#ifndef _STORAGEDRIVE_HPP_
@@ -32,6 +32,7 @@ using namespace std;
#include <stdint.h>
#include <string>
#include <fstream>
#include <assert.h>
#include "utils.hpp"
#include "device.hpp"
@@ -42,6 +43,7 @@ class storagecontroller_c;
class storagedrive_c: public device_c {
private:
fstream f; // image file
public:
storagecontroller_c *controller; // link to parent
@@ -50,27 +52,60 @@ public:
true, "", "%d", "Unit # of drive", 3, 10); // 3 bits = 0..7 allowed
// capacity of medium (disk/tape) in bytes
parameter_unsigned64_c capacity = parameter_unsigned64_c(this, "capacity",
"cap", /*readonly*/
true, "byte", "%d", "Storage capacity", 64, 10);
parameter_unsigned64_c capacity = parameter_unsigned64_c(this, "capacity", "cap", /*readonly*/
true, "byte", "%d", "Storage capacity", 64, 10);
parameter_string_c image_filepath = parameter_string_c(this, "image", "img", /*readonly*/
false, "Path to image file");
virtual bool on_param_changed(parameter_c *param) override;
// parameter_bool_c writeprotect = parameter_bool_c(this, "writeprotect", "wp", /*readonly*/false, "Medium is write protected, different reasons") ;
bool file_readonly;
bool file_open(std::string imagefname, bool create);
bool file_is_open(void);
bool file_readonly;bool file_open(std::string imagefname, bool create);bool file_is_open(
void);
void file_read(uint8_t *buffer, uint64_t position, unsigned len);
void file_write(uint8_t *buffer, uint64_t position, unsigned len);
uint64_t file_size(void);
void file_close(void);
storagedrive_c(storagecontroller_c *controller);
};
class storagedrive_selftest_c: public storagedrive_c {
private:
const char *imagefname;
unsigned block_size;
unsigned block_count;
uint8_t *block_buffer;
void block_buffer_fill(unsigned block_number);
void block_buffer_check(unsigned block_number);
public:
storagedrive_selftest_c(const char *imagefname, unsigned block_size, unsigned block_count) :
storagedrive_c(NULL) {
assert((block_size % 4) == 0); // whole uint32s
this->imagefname = imagefname;
this->block_size = block_size;
this->block_count = block_count;
this->block_buffer = (uint8_t *) malloc(block_size);
}
~storagedrive_selftest_c() {
free(block_buffer);
}
// fill abstracts
virtual void on_power_changed(void) {
}
virtual void on_init_changed(void) {
}
virtual void worker(void) {
}
void test(void);
};
#endif

172
10.01_base/2_src/arm/unibus.cpp
View File

@@ -1,28 +1,28 @@
/* unibus.cpp: utilities to handle UNIBUS functions
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
*/
12-nov-2018 JH entered beta phase
*/
#define _UNIBUS_CPP_
@@ -33,6 +33,7 @@
#include <time.h>
#include <assert.h>
#include "pru.hpp"
#include "logger.hpp"
#include "gpios.hpp"
#include "bitcalc.h"
@@ -46,7 +47,6 @@ unibus_c *unibus;
unibus_c::unibus_c() {
log_label = "UNIBUS";
emulation_logic_started = false;
dma_bandwidth_percent = 50;
dma_wordcount = MAX_DMA_WORDCOUNT;
}
@@ -96,24 +96,19 @@ void unibus_c::init(void) {
timeout.wait_ms(duration_ms);
buslatches_setval(7, BIT(3), 0);
*/
if (arbitration_active)
mailbox_execute(ARM2PRU_INITPULSE, ARM2PRU_EMULATION);
else
mailbox_execute(ARM2PRU_INITPULSE, ARM2PRU_NONE);
mailbox_execute(ARM2PRU_INITPULSE, ARM2PRU_NONE);
}
/* Simulate a power cycle
*/
void unibus_c::powercycle(void) {
if (arbitration_active)
mailbox_execute(ARM2PRU_POWERCYCLE, ARM2PRU_EMULATION);
else
mailbox_execute(ARM2PRU_POWERCYCLE, ARM2PRU_NONE);
mailbox_execute(ARM2PRU_POWERCYCLE, ARM2PRU_NONE);
}
// do an UNIBUS INTR transaction with arbitration
// do an UNIBUS INTR transaction with Arbitration by PDP-11 CPU
// todo: ARBITRATOR_MASTER?
void unibus_c::interrupt(uint8_t priority, uint16_t vector) {
assert(emulation_logic_started);
assert(pru->prucode_id == pru_c::PRUCODE_UNIBUS);
switch (priority) {
case 4:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B4;
@@ -134,26 +129,45 @@ void unibus_c::interrupt(uint8_t priority, uint16_t vector) {
mailbox->intr.vector = vector;
// mail last infinite, if processor priority above "priority"
// timeout ??
mailbox_execute(ARM2PRU_INTR, ARM2PRU_EMULATION);
mailbox_execute(ARM2PRU_INTR, ARM2PRU_NONE);
}
// do a DMA transaction with or without abritration (arbitration_active)
// do a DMA transaction with or without abritration (arbitration_client)
// mailbox.dma.words already filled
// if result = timeout: =
// 0 = bus time, error address = mailbox->dma.cur_addr
// 1 = all transfered
bool unibus_c::dma(uint8_t control, uint32_t startaddr, unsigned blocksize) {
bool unibus_c::dma(enum unibus_c::arbitration_mode_enum arbitration_mode, uint8_t control,
uint32_t startaddr, unsigned blocksize) {
uint64_t dmatime_ns, totaltime_ns;
assert(!arbitration_active || emulation_logic_started);
uint8_t dma_opcode;
// can access bus with DMA when there's a Bus Arbitrator
assert(pru->prucode_id == pru_c::PRUCODE_UNIBUS);
// TODO: assert pru->prucode_features & (PRUCODE_FEATURE_DMA) ???
// TODO: Arbitration Master waits for SACK, 11/34 blocks?
mailbox->dma.startaddr = startaddr;
mailbox->dma.control = control;
mailbox->dma.wordcount = blocksize;
timeout.start(0); // no timeout, just running timer
if (arbitration_active)
// wait until _EMULATION again
mailbox_execute(ARM2PRU_DMA, ARM2PRU_EMULATION);
else
mailbox_execute(ARM2PRU_DMA, ARM2PRU_NONE);
switch (arbitration_mode) {
case unibus_c::ARBITRATION_MODE_NONE:
dma_opcode = ARM2PRU_DMA_ARB_NONE;
break;
case unibus_c::ARBITRATION_MODE_CLIENT:
dma_opcode = ARM2PRU_DMA_ARB_CLIENT;
break;
case unibus_c::ARBITRATION_MODE_MASTER:
dma_opcode = ARM2PRU_DMA_ARB_MASTER;
break;
default:
FATAL("Illegal arbitration_mode");
}
// wait until PRU ready
mailbox_execute(dma_opcode, ARM2PRU_NONE);
dmatime_ns = timeout.elapsed_ns();
// wait before next transaction, to reduce Unibus bandwidth
// calc required total time for DMA time + wait
@@ -174,18 +188,18 @@ bool unibus_c::dma(uint8_t control, uint32_t startaddr, unsigned blocksize) {
* return 0: no memory found at all
* arbitration_active: if 1, perform NPR/NPG/SACK arbitration before mem accesses
*/
uint32_t unibus_c::test_sizer(void) {
uint32_t unibus_c::test_sizer(enum unibus_c::arbitration_mode_enum arbitration_mode) {
// tests chunks of 128 word
bool timeout;
unsigned addr = 0;
assert(!arbitration_active || emulation_logic_started);
//SET_DEBUG_PIN0(0) ;
do {
// printf("unibus_test_sizer(): %06o..%06o\n", addr, addr+2*unibus_dma_wordcount-2) ;
timeout = !dma(UNIBUS_CONTROL_DATI, addr, dma_wordcount);
timeout = !dma(arbitration_mode, UNIBUS_CONTROL_DATI, addr, dma_wordcount);
addr += 2 * dma_wordcount; // prep for next round
} while (!timeout);
//SET_DEBUG_PIN0(1) ; // signal end
//SET_DEBUG_PIN0(0) ;
return mailbox->dma.cur_addr; // first non implemented address
}
@@ -198,13 +212,12 @@ uint32_t unibus_c::test_sizer(void) {
// all words from start_addr to including end_addr
//
// DMA blocksize can be choosen arbitrarily
// arbitration_active: if 1, perform NPR/NPG/SACK arbitration before mem accesses
void unibus_c::mem_write(uint16_t *words, unsigned start_addr, unsigned end_addr,
unsigned block_wordcount,
void unibus_c::mem_write(enum unibus_c::arbitration_mode_enum arbitration_mode, uint16_t *words,
unsigned start_addr, unsigned end_addr, unsigned block_wordcount,
bool *timeout) {
unsigned block_start_addr = 0;
unsigned n;
assert(!arbitration_active || emulation_logic_started);
assert(pru->prucode_id == pru_c::PRUCODE_UNIBUS);
assert(block_wordcount <= MAX_DMA_WORDCOUNT);
*timeout = 0;
for (block_start_addr = start_addr; !*timeout && block_start_addr <= end_addr;
@@ -220,7 +233,8 @@ void unibus_c::mem_write(uint16_t *words, unsigned start_addr, unsigned end_addr
cur_addr = block_start_addr + 2 * n;
mailbox->dma.words[n] = words[cur_addr / 2];
}
*/*timeout = !dma(UNIBUS_CONTROL_DATO, block_start_addr, block_wordcount);
*/*timeout = !dma(arbitration_mode, UNIBUS_CONTROL_DATO, block_start_addr,
block_wordcount);
if (*timeout) {
printf("\nWrite timeout @ 0%6o\n", mailbox->dma.cur_addr);
return;
@@ -232,13 +246,12 @@ void unibus_c::mem_write(uint16_t *words, unsigned start_addr, unsigned end_addr
// all words from start_addr to including end_addr
// DMA blocksize can be choosen arbitrarily
// arbitration_active: if 1, perform NPR/NPG/SACK arbitration before mem accesses
void unibus_c::mem_read(uint16_t *words, uint32_t start_addr, uint32_t end_addr,
unsigned block_wordcount,
void unibus_c::mem_read(enum unibus_c::arbitration_mode_enum arbitration_mode, uint16_t *words,
uint32_t start_addr, uint32_t end_addr, unsigned block_wordcount,
bool *timeout) {
unsigned block_start_addr = 0;
unsigned n;
assert(!arbitration_active || emulation_logic_started);
assert(pru->prucode_id == pru_c::PRUCODE_UNIBUS);
assert(block_wordcount <= MAX_DMA_WORDCOUNT);
*timeout = 0;
@@ -248,7 +261,8 @@ void unibus_c::mem_read(uint16_t *words, uint32_t start_addr, uint32_t end_addr,
n = (end_addr - block_start_addr) / 2 + 1; // words left until memend
if (n < block_wordcount)
block_wordcount = n; //trunc last buffer
*timeout = !dma(UNIBUS_CONTROL_DATI, block_start_addr, block_wordcount);
*timeout = !dma(arbitration_mode, UNIBUS_CONTROL_DATI, block_start_addr,
block_wordcount);
if (*timeout) {
printf("\nRead timeout @ 0%6o\n", mailbox->dma.cur_addr);
return;
@@ -264,7 +278,8 @@ void unibus_c::mem_read(uint16_t *words, uint32_t start_addr, uint32_t end_addr,
}
// arbitration_active: if 1, perform NPR/NPG/SACK arbitration before mem accesses
void unibus_c::test_mem(uint32_t start_addr, uint32_t end_addr, unsigned mode) {
void unibus_c::test_mem(enum unibus_c::arbitration_mode_enum arbitration_mode,
uint32_t start_addr, uint32_t end_addr, unsigned mode) {
#define MAX_ERROR_COUNT 8
progress_c progress = progress_c(80);
bool timeout = 0, mismatch = 0;
@@ -272,7 +287,7 @@ void unibus_c::test_mem(uint32_t start_addr, uint32_t end_addr, unsigned mode) {
uint32_t cur_test_addr;
unsigned block_wordcount;
assert(!arbitration_active || emulation_logic_started);
assert(pru->prucode_id == pru_c::PRUCODE_UNIBUS);
// Setup ^C catcher
SIGINTcatchnext();
@@ -284,19 +299,25 @@ void unibus_c::test_mem(uint32_t start_addr, uint32_t end_addr, unsigned mode) {
/**** 2. Write memory ****/
progress.put("W"); //info : full memory write
block_wordcount = 113; // something queer
mem_write(testwords, start_addr, end_addr, block_wordcount, &timeout);
mem_write(arbitration_mode, testwords, start_addr, end_addr, block_wordcount, &timeout);
/**** 3. read until ^C ****/
while (!SIGINTreceived && !timeout && !mismatch_count) {
progress.put("R");
block_wordcount = 67; // something queer
// read back into unibus_membuffer[]
mem_read(membuffer->data.words, start_addr, end_addr, block_wordcount, &timeout);
mem_read(arbitration_mode, membuffer->data.words, start_addr, end_addr,
block_wordcount, &timeout);
// compare
SET_DEBUG_PIN0(0) ;
for (mismatch_count = 0, cur_test_addr = start_addr; cur_test_addr <= end_addr;
cur_test_addr += 2) {
uint16_t cur_mem_val = membuffer->data.words[cur_test_addr / 2];
mismatch = (testwords[cur_test_addr / 2] != cur_mem_val);
if (mismatch) {
SET_DEBUG_PIN0(1) ; // trigger
SET_DEBUG_PIN0(0) ;
}
if (mismatch && ++mismatch_count <= MAX_ERROR_COUNT) // print only first errors
printf(
"\nMemory mismatch #%d at %06o: expected %06o, found %06o, diff mask = %06o. ",
@@ -313,7 +334,8 @@ void unibus_c::test_mem(uint32_t start_addr, uint32_t end_addr, unsigned mode) {
testwords[cur_test_addr / 2] = random24() & 0xffff;
progress.put("W"); //info : full memory write
block_wordcount = 97; // something queer
mem_write(testwords, start_addr, end_addr, block_wordcount, &timeout);
mem_write(arbitration_mode, testwords, start_addr, end_addr, block_wordcount,
&timeout);
if (SIGINTreceived || timeout)
break; // leave loop
@@ -322,12 +344,18 @@ void unibus_c::test_mem(uint32_t start_addr, uint32_t end_addr, unsigned mode) {
progress.put("R"); //info : full memory write
block_wordcount = 111; // something queer
// read back into unibus_membuffer[]
mem_read(membuffer->data.words, start_addr, end_addr, block_wordcount, &timeout);
mem_read(arbitration_mode, membuffer->data.words, start_addr, end_addr,
block_wordcount, &timeout);
// compare
SET_DEBUG_PIN0(0) ;
for (mismatch_count = 0, cur_test_addr = start_addr; cur_test_addr <= end_addr;
cur_test_addr += 2) {
uint16_t cur_mem_val = membuffer->data.words[cur_test_addr / 2];
mismatch = (testwords[cur_test_addr / 2] != cur_mem_val);
if (mismatch) {
SET_DEBUG_PIN0(1) ; // trigger
SET_DEBUG_PIN0(0) ;
}
if (mismatch && ++mismatch_count <= MAX_ERROR_COUNT) // print only first errors
printf(
"\nMemory mismatch at %06o: expected %06o, found %06o, diff mask = %06o. ",
@@ -383,29 +411,3 @@ void unibus_c::savetofile(char *fname, uint16_t *words, unsigned bytecount) {
}
#endif
/* start full UNIBUS master/slave logic on PRU
* PRU is active UNIBUS node now.
* - evaluates NPG/BG* lines and forwards them.
* - watches for DATI/DATO access to emulated device registers,
* generates events to unibusadapter_c.
* - memory is emulated from startaddr to endaddr.
* - Memory DATI/DATZO access done with NPR/NPG/SACK
* - INTR possible
*/
void unibus_c::emulation_logic_start() {
// set PRU in ARM2PRU_EMULATION loop
assert(!emulation_logic_started);
__sync_synchronize();
mailbox->arm2pru_req = ARM2PRU_EMULATION; // go!
emulation_logic_started = true;
}
/* stop execution of full master/slave logic
*/
void unibus_c::emulation_logic_stop() {
assert(emulation_logic_started);
mailbox_execute(ARM2PRU_EMULATION_STOP, ARM2PRU_NONE);
emulation_logic_started = false;
}

424
10.01_base/2_src/arm/unibusadapter.cpp
View File

@@ -50,6 +50,7 @@
#include <string.h>
#include <pthread.h>
#include <assert.h>
#include <queue>
// TEST
//#include <unistd.h> // sleep()
@@ -66,11 +67,59 @@ using namespace std;
#include "iopageregister.h"
#include "unibusadapter.hpp"
dma_request_c::dma_request_c(
uint8_t unibus_control,
uint32_t unibus_addr,
uint16_t* buffer,
uint32_t wordcount) :
_unibus_control(unibus_control),
_unibus_start_addr(unibus_addr),
_unibus_end_addr(0),
_buffer(buffer),
_wordcount(wordcount),
_isComplete(false),
_success(false)
{
}
dma_request_c::~dma_request_c()
{
}
irq_request_c::irq_request_c(
unsigned level,
unsigned vector) :
_level(level),
_vector(vector),
_isComplete(false)
{
}
irq_request_c::~irq_request_c()
{
}
void* bus_worker(
void *context)
{
unibusadapter_c* bus = reinterpret_cast<unibusadapter_c*>(context);
bus->dma_worker();
return nullptr;
}
unibusadapter_c *unibusadapter; // another Singleton
// is registered in device_c.list<devices> ... order of static constructor calls ???
unibusadapter_c::unibusadapter_c() :
device_c() {
device_c(),
_busWakeup_cond(PTHREAD_COND_INITIALIZER),
_requestFinished_cond(PTHREAD_COND_INITIALIZER),
_busWorker_mutex(PTHREAD_MUTEX_INITIALIZER)
{
unsigned i;
log_label = "UNAPT";
@@ -82,14 +131,33 @@ unibusadapter_c::unibusadapter_c() :
line_INIT = false;
line_DCLO = false;
//
// Start bus worker thread
//
pthread_attr_t attribs;
pthread_attr_init(&attribs);
int status = pthread_create(
&_busWorker_pthread,
&attribs,
&bus_worker,
reinterpret_cast<void*>(this));
if (status != 0)
{
FATAL("Failed to start unibus worker thread. Status 0x%x", status);
}
}
bool unibusadapter_c::on_param_changed(parameter_c *param) {
UNUSED(param);
return true ;
}
void unibusadapter_c::on_power_changed(void) {
void unibusadapter_c::on_power_changed(void)
{
}
void unibusadapter_c::on_init_changed(void) {
@@ -106,6 +174,10 @@ void unibusadapter_c::worker_init_event() {
device->init_asserted = line_INIT;
device->on_init_changed();
}
// Clear bus request queues
rundown_bus_requests();
}
void unibusadapter_c::worker_power_event() {
@@ -118,6 +190,9 @@ void unibusadapter_c::worker_power_event() {
device->power_down = line_DCLO;
device->on_power_changed();
}
// Clear bus request queues
rundown_bus_requests();
}
// process DATI/DATO access to active device registers
@@ -441,7 +516,9 @@ void unibusadapter_c::unregister_device(unibusdevice_c& device) {
// false: UNIBUS DMA or INTR pending or in progress
// true: new DMA or INTR may be started
bool unibusadapter_c::request_DMA_active(const char *error_info) {
if (mailbox->arm2pru_req == ARM2PRU_DMA) {
if (mailbox->arm2pru_req == ARM2PRU_DMA_ARB_NONE
|| mailbox->arm2pru_req == ARM2PRU_DMA_ARB_CLIENT
|| mailbox->arm2pru_req == ARM2PRU_DMA_ARB_MASTER) {
if (error_info)
ERROR("%s: DMA requests active!", error_info);
return true;
@@ -463,110 +540,279 @@ bool unibusadapter_c::request_INTR_active(const char *error_info) {
return false;
}
// request a DMA cycle.
// Request a DMA cycle from Arbitrator.
// unibus_control = UNIBUS_CONTROL_DATI or _DATO
void unibusadapter_c::request_DMA(unibusdevice_c *device, uint8_t unibus_control,
uint32_t unibus_addr, uint16_t *buffer, unsigned wordcount) {
// TODO: if another DMA or INTR is active: put request in queue
UNUSED(device);
if (request_DMA_active(__func__) || request_INTR_active(__func__))
return;
// unibus_end_addr = last accessed address (success or timeout) and timeout condition
// result: false on UNIBUS timeout
bool unibusadapter_c::request_client_DMA(
uint8_t unibus_control,
uint32_t unibus_addr,
uint16_t *buffer,
uint32_t wordcount,
uint32_t *unibus_end_addr) {
mailbox->dma.startaddr = unibus_addr;
mailbox->dma.control = unibus_control;
mailbox->dma.wordcount = wordcount;
//
// Acquire bus mutex; append new request to queue.
// bus worker will wake and service the request in due time.
//
dma_request_c request(
unibus_control,
unibus_addr,
buffer,
wordcount);
// save params of current transaction
cur_DMA_unibus_control = unibus_control;
cur_DMA_buffer = buffer;
cur_DMA_wordcount = wordcount;
pthread_mutex_lock(&_busWorker_mutex);
_dmaRequests.push(&request);
pthread_cond_signal(&_busWakeup_cond);
pthread_mutex_unlock(&_busWorker_mutex);
if (unibus_control == UNIBUS_CONTROL_DATO) {
// copy data into mailbox->DMA buffer
memcpy((void*) mailbox->dma.words, buffer, 2 * wordcount);
}
DEBUG("DMA start: %s @ %06o, len=%d", unibus->control2text(unibus_control), unibus_addr,
wordcount);
// start!
mailbox->arm2pru_req = ARM2PRU_DMA;
// PRU now changes state
}
void unibusadapter_c::request_INTR(unibusdevice_c *device, unsigned level, unsigned vector) {
// TODO: if another DMA or INTR is active: put request in queue
UNUSED(device);
// it is not an error if the INTR (at same level) is still pending
// a device may re-raise its interrupt, an interrupt may remain pending for years.
if (request_DMA_active(__func__))
return;
if (request_INTR_active(NULL))
return;
switch (level) {
case 4:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B4;
break;
case 5:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B5;
break;
case 6:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B6;
break;
case 7:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B7;
break;
default:
ERROR("Request_INTR(): Illegal priority %u, aborting", level);
return;
//
// Wait for request to finish.
//
pthread_mutex_lock(&_busWorker_mutex);
while (!request.IsComplete())
{
pthread_cond_wait(&_requestFinished_cond, &_busWorker_mutex);
}
mailbox->intr.vector = vector;
pthread_mutex_unlock(&_busWorker_mutex);
// start!
mailbox->arm2pru_req = ARM2PRU_INTR;
// PRU now changes state
if (unibus_end_addr)
*unibus_end_addr = request.GetUnibusEndAddr() ;
return request.GetSuccess() ;
}
// device wants to know state of its requests
// also checks for completion if the single current DMA or INTR.
// to be called by device.worker()
// result: false = not yet finished, true = complete,
// error: return NXM status
bool unibusadapter_c::complete_DMA(unibusdevice_c *device, uint32_t *unibus_end_addr,
bool *error) {
// TODO: access correct request in queue
UNUSED(device);
void unibusadapter_c::dma_worker()
{
//worker_init_realtime_priority(rt_device);
while(true)
{
dma_request_c* dmaReq = nullptr;
irq_request_c* irqReq = nullptr;
//
// Wait for the next request.
//
pthread_mutex_lock(&_busWorker_mutex);
while(_dmaRequests.empty() && _irqRequests.empty())
{
pthread_cond_wait(
&_busWakeup_cond,
&_busWorker_mutex);
}
// rely on RL11 to check for completion and sorting DMA/INTR requests.
if (request_DMA_active(NULL))
return false;
//
// We have a request: prioritize IRQ over DMA, dequeue from the requisite
// queue and get to work.
//
if (!_irqRequests.empty())
{
irqReq = _irqRequests.front();
_irqRequests.pop();
}
else
{
dmaReq = _dmaRequests.front();
_dmaRequests.pop();
}
pthread_mutex_unlock(&_busWorker_mutex);
if (cur_DMA_unibus_control == UNIBUS_CONTROL_DATI) {
// data were read
// copy result cur_DMA_wordcount from mailbox->DMA bufuffer to cur_DMA_buffer
memcpy(cur_DMA_buffer, (void *) mailbox->dma.words, 2 * cur_DMA_wordcount);
// Sanity check: Should be no active DMA or interrupt requests on the PRU.
assert (!request_DMA_active(nullptr) && !request_INTR_active(nullptr));
if (dmaReq)
{
// We do the DMA transfer in chunks so we can handle arbitrary buffer sizes.
// (the PRU mailbox has limited space available.)
// Configure the DMA transfer.
uint32_t maxTransferSize = 512;
uint32_t wordCount = dmaReq->GetWordCount();
uint32_t unibusAddr = dmaReq->GetUnibusStartAddr();
uint32_t bufferOffset = 0;
while (wordCount > 0)
{
uint32_t chunkSize = std::min(maxTransferSize, wordCount);
mailbox->dma.startaddr = unibusAddr + bufferOffset * 2;
mailbox->dma.control = dmaReq->GetUnibusControl();
mailbox->dma.wordcount = chunkSize;
// Copy outgoing data into maibox DMA buffer
if (dmaReq->GetUnibusControl() == UNIBUS_CONTROL_DATO)
{
memcpy(
(void*)mailbox->dma.words,
dmaReq->GetBuffer() + bufferOffset,
2 * chunkSize);
}
//
// Start the PRU:
mailbox->arm2pru_req = ARM2PRU_DMA_ARB_CLIENT;
//
// Wait for the transfer to complete.
// TODO: we're polling the mailbox; is there a more efficient way to do this?
timeout_c timeout;
int retries = 0;
while (request_DMA_active(nullptr) && retries < 10000)
{
timeout.wait_us(50);
retries++;
}
//
// TODO: this should not be necessary. There are rare occasions
// where it appears that the PRU dma transfer is interrupted
// but never clears the DMA active flag, so we hang in the loop above
// forever.
// Nothing to do in that case but give up.
// And log the issue. Should get to the root of this..
//
if (retries == 10000)
{
ERROR("dma timeout");
}
if (dmaReq->GetUnibusControl() == UNIBUS_CONTROL_DATI)
{
// Copy data read from mailbox to user's buffer.
memcpy(
dmaReq->GetBuffer() + bufferOffset,
(void *)mailbox->dma.words,
2 * chunkSize);
}
wordCount -= chunkSize;
bufferOffset += chunkSize;
}
dmaReq->SetUnibusEndAddr(mailbox->dma.cur_addr);
dmaReq->SetSuccess(mailbox->dma.cur_status == DMA_STATE_READY);
// no success: UnibusEndAddr is first failed address
assert(dmaReq->GetUnibusStartAddr() + dmaReq->GetWordCount() * 2 ==
mailbox->dma.cur_addr + 2);
//
// Signal that the request is complete.
//
pthread_mutex_lock(&_busWorker_mutex);
dmaReq->SetComplete();
pthread_cond_signal(&_requestFinished_cond);
pthread_mutex_unlock(&_busWorker_mutex);
}
else
{
// Handle interrupt request
switch(irqReq->GetInterruptLevel())
{
case 4:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B4;
break;
case 5:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B5;
break;
case 6:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B6;
break;
case 7:
mailbox->intr.priority_bit = ARBITRATION_PRIORITY_BIT_B7;
break;
default:
ERROR("Request_INTR(): Illegal priority %u, aborting", irqReq->GetInterruptLevel());
return;
}
mailbox->intr.vector = irqReq->GetVector();
// start!
mailbox->arm2pru_req = ARM2PRU_INTR;
// PRU now changes state
// Signal that the request has been raised.
pthread_mutex_lock(&_busWorker_mutex);
irqReq->SetComplete();
pthread_cond_signal(&_requestFinished_cond);
pthread_mutex_unlock(&_busWorker_mutex);
// Wait for the transfer to complete.
// TODO: we're polling the mailbox; is there a more efficient way to
// do this? (as w/dma)
timeout_c timeout;
while(request_INTR_active(nullptr))
{
timeout.wait_us(50);
}
}
}
*unibus_end_addr = mailbox->dma.cur_addr;
*error = mailbox->dma.cur_status != DMA_STATE_READY;
DEBUG("DMA ready: %s @ %06o..%06o, wordcount %d, data=%06o, %06o, ... %s",
unibus->control2text(mailbox->dma.control), mailbox->dma.startaddr,
mailbox->dma.cur_addr, mailbox->dma.wordcount, mailbox->dma.words[0],
mailbox->dma.words[1], *error ? "TIMEOUT" : "OK");
return true;
}
// result: false = not yet finished, true = complete,
bool unibusadapter_c::complete_INTR(unibusdevice_c *device) {
// TODO: access correct request in queue
UNUSED(device);
void unibusadapter_c::rundown_bus_requests()
{
//
// Cancel all pending DMA and IRQ requests, freeing threads waiting
// on completion.
//
pthread_mutex_lock(&_busWorker_mutex);
while (!_dmaRequests.empty())
{
dma_request_c* dmaReq = _dmaRequests.front();
dmaReq->SetSuccess(false);
dmaReq->SetComplete();
pthread_cond_signal(&_requestFinished_cond);
_dmaRequests.pop();
}
while (!_irqRequests.empty())
{
irq_request_c* irqReq = _irqRequests.front();
irqReq->SetComplete();
pthread_cond_signal(&_requestFinished_cond);
_irqRequests.pop();
}
pthread_mutex_unlock(&_busWorker_mutex);
// rely on RL11 to check for completion and sorting DMA/INTR requests.
return request_INTR_active(NULL);
}
void unibusadapter_c::request_INTR(uint32_t level, uint32_t vector) {
//
// Acquire bus mutex; append new request to queue.
// bus worker will wake and service the request in due time.
//
irq_request_c request(
level,
vector);
pthread_mutex_lock(&_busWorker_mutex);
_irqRequests.push(&request);
pthread_cond_signal(&_busWakeup_cond);
pthread_mutex_unlock(&_busWorker_mutex);
//
// Wait for request to finish.
//
pthread_mutex_lock(&_busWorker_mutex);
while (!request.IsComplete())
{
pthread_cond_wait(&_requestFinished_cond, &_busWorker_mutex);
}
pthread_mutex_unlock(&_busWorker_mutex);
//
// And we're done.
//
}
// debugging: print PRU sharead regsster map

84
10.01_base/2_src/arm/unibusadapter.hpp
View File

@@ -28,17 +28,71 @@
#define _UNIBUSADAPTER_HPP_
#include <thread>
#include <queue>
#include "iopageregister.h"
#include "unibusdevice.hpp"
class dma_request_c
{
public:
dma_request_c(
uint8_t unibus_control,
uint32_t unibus_addr,
uint16_t *buffer,
uint32_t wordcount);
~dma_request_c();
uint8_t GetUnibusControl() { return _unibus_control; }
uint32_t GetUnibusStartAddr() { return _unibus_start_addr; }
uint16_t* GetBuffer() { return _buffer; }
uint32_t GetWordCount() { return _wordcount; }
uint32_t GetUnibusEndAddr() { return _unibus_end_addr; }
void SetUnibusEndAddr(uint32_t end) { _unibus_end_addr = end; }
bool IsComplete() { return _isComplete; }
bool GetSuccess() { return _success; }
void SetComplete() { _isComplete = true; }
void SetSuccess(bool success) { _success = success; }
private:
uint8_t _unibus_control;
uint32_t _unibus_start_addr;
uint32_t _unibus_end_addr;
uint16_t* _buffer;
uint32_t _wordcount;
bool _isComplete;
bool _success;
};
class irq_request_c
{
public:
irq_request_c(
uint32_t level,
uint32_t vector);
~irq_request_c();
uint32_t GetInterruptLevel() { return _level; }
uint32_t GetVector() { return _vector; }
bool IsComplete() { return _isComplete; }
void SetComplete() { _isComplete = true; }
private:
uint32_t _level;
uint32_t _vector;
bool _isComplete;
};
// is a device_c. need a thread (but no params)
class unibusadapter_c: public device_c {
private:
// save params of current DMA transaction
volatile uint8_t cur_DMA_unibus_control; // DATI? DATO?
uint16_t *cur_DMA_buffer;
volatile unsigned cur_DMA_wordcount;
public:
unibusadapter_c();
@@ -59,21 +113,29 @@ public:
void worker_power_event(void) ;
void worker_deviceregister_event(void) ;
void worker(void) override; // background worker function
void dma_worker(void); // background DMA worker
bool register_device(unibusdevice_c& device);
void unregister_device(unibusdevice_c& device);
bool request_DMA_active(const char *error_info) ;
bool request_INTR_active(const char *error_info) ;
void request_DMA(unibusdevice_c *device, uint8_t unibus_control, uint32_t unibus_addr,
uint16_t *buffer, unsigned wordcount);
void request_INTR(unibusdevice_c *device, unsigned level, unsigned vector);
bool complete_DMA(unibusdevice_c *device, uint32_t *unibus_end_addr, bool *error);
bool complete_INTR(unibusdevice_c *device);
bool request_client_DMA(uint8_t unibus_control, uint32_t unibus_addr,
uint16_t *buffer, uint32_t wordcount, uint32_t *unibus_end_addr);
void request_INTR(uint32_t level, uint32_t vector);
void rundown_bus_requests(void);
void print_shared_register_map(void);
private:
std::queue<dma_request_c*> _dmaRequests;
std::queue<irq_request_c*> _irqRequests;
pthread_t _busWorker_pthread;
pthread_cond_t _busWakeup_cond;
pthread_cond_t _requestFinished_cond;
pthread_mutex_t _busWorker_mutex;
};
extern unibusadapter_c *unibusadapter; // another Singleton

2
10.01_base/2_src/arm/unibusdevice.cpp
View File

@@ -135,7 +135,7 @@ void unibusdevice_c::reset_unibus_registers() {
// set an UNIBUS interrupt condition with intr_vector and intr_level
void unibusdevice_c::interrupt(void) {
// delegate to unibusadapter_c
unibusadapter->request_INTR(this, intr_level.value, intr_vector.value);
unibusadapter->request_INTR(intr_level.value, intr_vector.value);
// WARNING("unibusdevice_c::interrupt() TODO: generated interrupt!");
}

15
10.01_base/2_src/arm/utils.cpp
View File

@@ -34,6 +34,7 @@
#include <stdbool.h>
#include <signal.h>
#include <time.h>
#include <limits.h>
#include <sys/time.h>
#include <sys/stat.h>
@@ -162,6 +163,20 @@ bool fileExists(const std::string& filename) {
return false;
}
// Generates "perror()" printout,
// msgfmt must have one "%s" field for absolute filename
char *fileErrorText(const char *msgfmt, const char *fname) {
static char linebuff[PATH_MAX +100];
char abspath[PATH_MAX] ;
realpath(fname, abspath);
sprintf(linebuff, msgfmt, abspath);
strcat(linebuff, ": ") ;
strcat (linebuff, strerror(errno)) ;
// perror(linebuff);
return linebuff ;
}
// add a number of microseconds to a time
struct timespec timespec_add_us(struct timespec ts, unsigned us) {
ts.tv_nsec += us * 1000;

2
10.01_base/2_src/arm/utils.hpp
View File

@@ -93,6 +93,8 @@ char *cur_time_text(void) ;
bool fileExists(const std::string& filename) ;
char * fileErrorText(const char *msgfmt, const char *fname) ;
//ool caseInsCompare(const std::string& s1, const std::string& s2) ;

81
10.01_base/2_src/pru0/Makefile
View File

@@ -25,9 +25,8 @@ endef
$(error $(ERROR_BODY))
endif
PRU_NUM=0
PROJ_NAME=pru$(PRU_NUM)
GEN_DIR=$(abspath ../../4_deploy)
PROJ_NAME=pru0
OBJ_DIR=$(abspath ../../4_deploy)
SHARED_DIR=$(abspath ../shared)
MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
CURRENT_DIR := $(notdir $(patsubst %/,%,$(dir $(MKFILE_PATH))))
@@ -41,75 +40,85 @@ STACK_SIZE=0x100
HEAP_SIZE=0x100
#Common compiler and linker flags (Defined in 'PRU Optimizing C/C++ Compiler User's Guide)
CFLAGS=-v3 -O3 --display_error_number --endian=little --hardware_mac=on --obj_directory=$(GEN_DIR) --pp_directory=$(GEN_DIR) -ppd -ppa \
CFLAGS=-v3 -O3 --display_error_number --endian=little --hardware_mac=on --obj_directory=$(OBJ_DIR) --pp_directory=$(OBJ_DIR) -ppd -ppa \
--c_src_interlist --optimizer_interlist
#Linker flags (Defined in 'PRU Optimizing C/C++ Compiler User's Guide)
LFLAGS=--reread_libs --warn_sections --stack_size=$(STACK_SIZE) --heap_size=$(HEAP_SIZE)
PRU_CODE=pru$(PRU_NUM)_config.c
TARGET=$(GEN_DIR)/$(PROJ_NAME).out
MAP=$(GEN_DIR)/$(PROJ_NAME).map
SOURCES=$(wildcard *.c)
# extension is ".asmsrc", not ".asm", do distinguish from compiler-generated .asm files.
SOURCES_ASM=$(wildcard *.asmsrc)
#Using .object instead of .obj in order to not conflict with the CCS build process
OBJECTS=$(patsubst %,$(GEN_DIR)/%,$(SOURCES:.c=.object))
OBJECTS_ASM=$(patsubst %,$(GEN_DIR)/%,$(SOURCES_ASM:.asmsrc=.asmobject))
OBJECTS_ALL=$(patsubst %,$(OBJ_DIR)/%,$(SOURCES:.c=.object))
OBJECTS_ASM=$(patsubst %,$(OBJ_DIR)/%,$(SOURCES_ASM:.asmsrc=.asmobject))
#all: $(TARGET)
# only interested on the image as C-array
all: $(GEN_DIR)/$(PRU_CODE)
# all .object files with exceptions of the *main*
OBJECTS_COMMON= \
$(OBJ_DIR)/pru0_pru_mailbox.object
# rule to print a variable.
# use: make print-VARIALBE
print-% : ; @echo $* = $($*)
# Invokes the linker (-z flag) to make the .out file
$(TARGET): $(OBJECTS) $(OBJECTS_ASM) $(LINKER_COMMAND_FILE)
# only interested on the image as C-array.
# Chained builds, so keep *.objects, else recompile.
all: $(OBJECTS_ALL) \
$(OBJ_DIR)/pru0_code_all.out \
$(OBJ_DIR)/pru0_code_all_array.c
# Rule to generate several linked binaries from several main*.c,
# then several C_array files from the linked binary.
# arrayfile <codevariant>_code.c depends on all objects and <codevariant>_main.c
# Example: pru1_main_test.c => obj_dir/pru1_code_test.c
# call with "<path>/make target_pru1_test_code.c"
$(OBJ_DIR)/pru0_code_%.out : $(OBJ_DIR)/pru0_main_%.object $(OBJECTS_COMMON) $(OBJECTS_ASM) $(LINKER_COMMAND_FILE)
@echo ''
@echo 'Building target: $@'
@echo 'Building binary $@'
@echo 'Invoking: PRU Linker'
$(PRU_CGT)/bin/clpru $(CFLAGS) -z -i$(PRU_CGT)/lib -i$(PRU_CGT)/include $(LFLAGS) -o $(TARGET) $(OBJECTS) $(OBJECTS_ASM) -m$(MAP) $(LINKER_COMMAND_FILE) --library=libc.a $(LIBS)
@echo 'Finished building target: $@'
$(PRU_CGT)/bin/clpru $(CFLAGS) -z -i$(PRU_CGT)/lib -i$(PRU_CGT)/include $(LFLAGS) -o $@ -m$@.map $^ --library=libc.a $(LIBS)
@echo 'Finished building $@'
# --outfile=$(GEN_DIR)/$(PROJ_NAME)_imagearrays.c
# the rule for .out file generates the C-array too.
$(GEN_DIR)/$(PRU_CODE): $(TARGET)
# Rule to generate several C-array hex dumps from linked binaries
# hexpru appends "_array" to the base file name
$(OBJ_DIR)/pru0_code_%_array.c : $(OBJ_DIR)/pru0_code_%.out
@echo 'Generating C-arrays containing binary images with PRU code.'
$(PRU_CGT)/bin/hexpru --array $(TARGET)
@echo 'Adding entry addresses to PRU config C source file'
$(SHARED_DIR)/update_pru_config.sh $(PRU_NUM) $(PROJ_NAME)_array.c $(GEN_DIR)/$(PROJ_NAME)_config $(GEN_DIR)/$(PROJ_NAME).map
@rm $(PROJ_NAME)_array.c
( \
cd $(OBJ_DIR) ; \
$(PRU_CGT)/bin/hexpru --array $< ; \
)
# Invokes the compiler on all c files in the directory to create the object files
$(GEN_DIR)/%.object: %.c
@mkdir -p $(GEN_DIR)
$(OBJ_DIR)/%.object: %.c
@mkdir -p $(OBJ_DIR)
@echo ''
@echo 'Building file: $<'
@echo 'Invoking: PRU Compiler'
$(PRU_CGT)/bin/clpru --include_path=$(PRU_CGT)/include $(INCLUDE) $(CFLAGS) -fe $@ $<
@echo Produce assembler listing
$(PRU_CGT)/bin/clpru --include_path=$(PRU_CGT)/include $(INCLUDE) $(CFLAGS) --absolute_listing -fe $@ $<
mv *.asm $(GEN_DIR)
mv *.asm $(OBJ_DIR)
# Invokes the compiler on all asm files in the directory to create the object files
$(GEN_DIR)/%.asmobject: %.asmsrc
#$(GEN_DIR)/pru1_pru0_datout.o: pru1_pru0_datout.asmsrc
@mkdir -p $(GEN_DIR)
$(OBJ_DIR)/%.asmobject: %.asmsrc
#$(OBJ_DIR)/pru1_pru0_datout.o: pru1_pru0_datout.asmsrc
@mkdir -p $(OBJ_DIR)
@echo ''
@echo 'Building file: $<'
@echo 'Invoking: PRU Compiler'
$(PRU_CGT)/bin/clpru --asm_listing --asm_file=$^ --output_file=$@
-mv *.lst $(GEN_DIR)
-mv *.lst $(OBJ_DIR)
.PHONY: all clean
# Remove the $(GEN_DIR) directory
# Remove the $(OBJ_DIR) directory
clean:
@echo Removing $(PROJ_NAME)'*.*' files in the "$(GEN_DIR)" directory
@rm -f $(GEN_DIR)/$(PROJ_NAME)*.*
@echo Removing all $(PROJ_NAME)'*' files in the "$(OBJ_DIR)" directory
@rm -f $(OBJ_DIR)/$(PROJ_NAME)*.*
# Includes the dependencies that the compiler creates (-ppd and -ppa flags)
-include $(OBJECTS:%.object=%.pp)
-include $(OBJECTS_ALL:%.object=%.pp)

4
10.01_base/2_src/pru0/pru0_array.h
View File

@@ -1,4 +0,0 @@
const uint32_t pru0_image_0[23];
const uint8_t pru0_image_1[20];

56
10.01_base/2_src/pru0/pru0_main.c
View File

@@ -1,56 +0,0 @@
/* pru0_main.c: endless loop, writes outputs on R30 from mailbox (C solution)
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
from d:\RetroCmp\dec\pdp11\UniBone\91_3rd_party\pru-c-compile\pru-software-support-package\examples\am335x\PRU_gpioToggle\
*/
#include <stdint.h>
#include <pru_cfg.h>
#include "resource_table_empty.h"
#include "pru_pru_mailbox.h"
volatile register uint32_t __R30;
volatile register uint32_t __R31;
void main(void) {
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
// loop forever
void pru0_dataout(void) ;
pru0_dataout() ;
#ifdef USED
// old code using shared RAM mailbox, not reached
while(1) {
__R30 = pru_pru_mailbox.pru0_r30 ;
}
#endif
}

110
10.01_base/2_src/pru1/Makefile
View File

@@ -25,9 +25,8 @@ endef
$(error $(ERROR_BODY))
endif
PRU_NUM=1
PROJ_NAME=pru$(PRU_NUM)
GEN_DIR=$(abspath ../../4_deploy)
PROJ_NAME=pru1
OBJ_DIR=$(abspath ../../4_deploy)
SHARED_DIR=$(abspath ../shared)
MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
CURRENT_DIR := $(notdir $(patsubst %/,%,$(dir $(MKFILE_PATH))))
@@ -47,75 +46,102 @@ CFLAGS_OPTIMIZER=--opt_level=3 --opt_for_speed=5 --auto_inline --c_src_interli
#CFLAGS_OPTIMIZER=--opt_level=3 --auto_inline --c_src_interlist --optimizer_interlist --gen_opt_info=2
#Common compiler and linker flags (Defined in 'PRU Optimizing C/C++ Compiler User's Guide)
CFLAGS=-v3 $(CFLAGS_OPTIMIZER) \
--display_error_number --endian=little --hardware_mac=on --obj_directory=$(GEN_DIR) --pp_directory=$(GEN_DIR) -ppd -ppa
--display_error_number --endian=little --hardware_mac=on --obj_directory=$(OBJ_DIR) --pp_directory=$(OBJ_DIR) -ppd -ppa
#Linker flags (Defined in 'PRU Optimizing C/C++ Compiler User's Guide)
LFLAGS=--reread_libs --warn_sections --stack_size=$(STACK_SIZE) --heap_size=$(HEAP_SIZE)
PRU_CODE=pru1_config.c
TARGET=$(GEN_DIR)/$(PROJ_NAME).out
MAP=$(GEN_DIR)/$(PROJ_NAME).map
#
SOURCES=$(wildcard *.c)
HEADERS=$(wildcard *.h)
# extension is ".asmsrc", not ".asm", do distinguish from compiler-generated .asm files.
SOURCES_ASM=$(wildcard *.asmsrc)
#Using .object instead of .obj in order to not conflict with the CCS build process
OBJECTS=$(patsubst %,$(GEN_DIR)/%,$(SOURCES:.c=.object))
OBJECTS_ASM=$(patsubst %,$(GEN_DIR)/%,$(SOURCES_ASM:.asmsrc=.asmobject))
#SOURCES_ASM=$(wildcard *.asmsrc)
#OBJECTS_ASM=$(patsubst %,$(OBJ_DIR)/%,$(SOURCES_ASM:.asmsrc=.asmobject))
#all: $(TARGET)
# only interested on the image as C-array
all: $(GEN_DIR)/$(PRU_CODE)
# Using .object instead of .obj in order to not conflict with the CCS build process
OBJECTS_ALL=$(patsubst %,$(OBJ_DIR)/%,$(SOURCES:.c=.object))
# all .object files with exceptions of the *main*
OBJECTS_COMMON= \
$(OBJ_DIR)/pru1_arm_mailbox.object \
$(OBJ_DIR)/pru1_buslatches.object \
$(OBJ_DIR)/pru1_ddrmem.object \
$(OBJ_DIR)/pru1_iopageregisters.object \
$(OBJ_DIR)/pru1_pru_mailbox.object \
$(OBJ_DIR)/pru1_statemachine_arbitration.object \
$(OBJ_DIR)/pru1_statemachine_dma.object \
$(OBJ_DIR)/pru1_statemachine_init.object \
$(OBJ_DIR)/pru1_statemachine_intr.object \
$(OBJ_DIR)/pru1_statemachine_powercycle.object \
$(OBJ_DIR)/pru1_statemachine_slave.object \
$(OBJ_DIR)/pru1_utils.object
# Invokes the linker (-z flag) to make the .out file
$(TARGET): $(OBJECTS) $(OBJECTS_ASM) $(LINKER_COMMAND_FILE)
# rule to print a variable.
# use: make print-VARIALBE
print-% : ; @echo $* = $($*)
# only interested on the image as C-array.
# Chained builds, so keep *.objects, else recompile.
all: $(OBJECTS_ALL) \
$(OBJ_DIR)/pru1_code_unibus.out $(OBJ_DIR)/pru1_code_unibus_array.c \
$(OBJ_DIR)/pru1_code_test.out $(OBJ_DIR)/pru1_code_test_array.c
#all: $(OBJECTS_ALL) $(OBJ_DIR)/pru1_code_test_array.c
# Rule to generate several linked binaries from several main*.c,
# then several C_array files from the linked binary.
# arrayfile <codevariant>_code.c depends on all objects and <codevariant>_main.c
# Example: pru1_main_test.c => obj_dir/pru1_code_test.c
# call with "<path>/make target_pru1_test_code.c"
$(OBJ_DIR)/pru1_code_%.out : $(OBJ_DIR)/pru1_main_%.object $(OBJECTS_COMMON) $(OBJECTS_ASM) $(LINKER_COMMAND_FILE)
@echo ''
@echo 'Building target: $@'
@echo 'Building binary $@'
@echo 'Invoking: PRU Linker'
$(PRU_CGT)/bin/clpru $(CFLAGS) -z -i$(PRU_CGT)/lib -i$(PRU_CGT)/include $(LFLAGS) -o $(TARGET) $(OBJECTS) $(OBJECTS_ASM) -m$(MAP) $(LINKER_COMMAND_FILE) --library=libc.a $(LIBS)
@echo 'Finished building target: $@'
$(PRU_CGT)/bin/clpru $(CFLAGS) -z -i$(PRU_CGT)/lib -i$(PRU_CGT)/include $(LFLAGS) -o $@ -m$@.map $^ --library=libc.a $(LIBS)
@echo 'Finished building $@'
# --outfile=$(GEN_DIR)/$(PROJ_NAME)_imagearrays.c
# the rule for .out file generates the C-array too.
$(GEN_DIR)/$(PRU_CODE): $(TARGET)
# Rule to generate several C-array hex dumps from linked binaries
# hexpru appends "_array" to the base file name
$(OBJ_DIR)/pru1_code_%_array.c : $(OBJ_DIR)/pru1_code_%.out
@echo 'Generating C-arrays containing binary images with PRU code.'
$(PRU_CGT)/bin/hexpru --array $(TARGET)
@echo 'Adding entry addresses to PRU config C source file'
$(SHARED_DIR)/update_pru_config.sh $(PRU_NUM) $(PROJ_NAME)_array.c $(GEN_DIR)/$(PROJ_NAME)_config $(GEN_DIR)/$(PROJ_NAME).map
@rm $(PROJ_NAME)_array.c
( \
cd $(OBJ_DIR) ; \
$(PRU_CGT)/bin/hexpru --array $< ; \
)
# Invokes the compiler on all c files in the directory to create the object files
$(GEN_DIR)/%.object: %.c
@mkdir -p $(GEN_DIR)
$(OBJ_DIR)/%.object: %.c
@mkdir -p $(OBJ_DIR)
@echo ''
@echo 'Building file: $<'
@echo 'Building file: $@'
@echo 'Invoking: PRU Compiler'
$(PRU_CGT)/bin/clpru --include_path=$(PRU_CGT)/include $(INCLUDE) $(CFLAGS) --output_file=$@ $<
@echo Produce assembler listing
$(PRU_CGT)/bin/clpru --include_path=$(PRU_CGT)/include $(INCLUDE) $(CFLAGS) --absolute_listing --output_file=$@ $<
-mv *.asm $(GEN_DIR)
-mv *.asm $(OBJ_DIR)
# Invokes the compiler on all asm files in the directory to create the object files
$(GEN_DIR)/%.asmobject: %.asmsrc
@mkdir -p $(GEN_DIR)
@echo ''
@echo 'Building file: $<'
@echo 'Invoking: PRU Compiler'
$(PRU_CGT)/bin/clpru --asm_listing --asm_file=$^ --output_file=$@
-mv *.lst $(GEN_DIR)
#$(OBJ_DIR)/%.asmobject: %.asmsrc
# @mkdir -p $(OBJ_DIR)
# @echo ''
# @echo 'Building file: $<'
# @echo 'Invoking: PRU Compiler'
# $(PRU_CGT)/bin/clpru --asm_listing --asm_file=$^ --output_file=$@
# -mv *.lst $(OBJ_DIR)
.PHONY: all clean
# Remove the $(GEN_DIR) directory
# Remove the $(OBJ_DIR) directory
clean:
@echo Removing $(PROJ_NAME)'*.*' files in the "$(GEN_DIR)" directory
@rm -f $(GEN_DIR)/$(PROJ_NAME)*.*
@echo Removing all $(PROJ_NAME)* files in the "$(OBJ_DIR)" directory
@rm -f $(OBJ_DIR)/$(PROJ_NAME)*
# Includes the dependencies that the compiler creates (-ppd and -ppa flags)
-include $(OBJECTS:%.object=%.pp)
-include $(OBJECTS_ALL:%.object=%.pp)

4
10.01_base/2_src/pru1/pru1_array.h
View File

@@ -1,4 +0,0 @@
const uint32_t pru1_image_0[2048];
const uint8_t pru1_image_1[20];

386
10.01_base/2_src/pru1/pru1_buslatches.c
View File

@@ -1,34 +1,35 @@
/* pru1_buslatches.c: PRU function to access to multiplex signal registers
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
*/
12-nov-2018 JH entered beta phase
*/
#define _BUSLATCHES_C_
#include <stdlib.h>
#include <stdint.h>
#include "tuning.h"
#include "pru1_utils.h"
#include "mailbox.h"
@@ -40,21 +41,98 @@ volatile register uint32_t __R31;
buslatches_t buslatches;
// set register signals to standard
/* central function instead of macros eliminates
optimizer influence.
*/
void buslatches_setbits_helper(uint32_t val /* R14 */, uint32_t reg_sel /* R15 */,
uint8_t *cur_reg_val /* R16 */) {
/*
; See Compiler 2.2 Guide, Chapter 6.6
XFR val to PRU0 in R14
code loop on PRU00: 15ns
; loop:
; xin 14,&r14,4
; mov r30,r14
; br loop
Device ID 14 = "other PRU"
Timing data path:
15ns PRU0 loop
+ 10ns 74LS377 setup (only +5ns for 74AHCT377)
+ 5ns wires
=> 30ns
Timing register select & strobe:
10ns setup time for 74ac138 (worst)
5ns wires
=> 15ns
With optimized circuitry (PCB 2018-12, adapted terminators, 74AHC138):
Both BBB and BBG can reach
setbits: __delay_cycles(3)
setyte: __delay_cycles(5)
*/
/* On optimized PCBs, speed is better if R30 (REGSEL) is set
BEFORE DATOUT is put to PRU0.
However on non-optimized boards this leads to instabilities ...
so software must remain at "REGSEL after DATOUT".
*/
//__R30 = (reg_sel << 8);
// 14 = device id of other PRU
// 14 = to R14
__xout(14, 14, 0, val);
// generates 2 cycles, additional NOP
// select is PRU1_<8:10>
// WRITE is PRU1_11, set L to prepare L->H pulse
__R30 = (reg_sel << 8);
*cur_reg_val = val; // remember register state
// compiles to SBBO &... : 2 cycles ?
// => 30ns - 3 cycles for code + 1 reserve
// wait 25ns for PRU0 datout and 74LS377 setup time
__delay_cycles(BUSLATCHES_SETBITS_DELAY);
// E0 at 74LS377 reached
// strobe WRITE L->H, latch data and WRITE back to idle.
// keep reg_sel, 74LS377 has "holdtime" of 5ns, the AC138 guarantees only 1 ns.
__R30 |= (1 << 11);
}
void buslatches_setbyte_helper(uint32_t val /*R14*/, uint32_t reg_sel /* R15 */) {
// timing see above
//__R30 = (reg_sel << 8);
__xout(14, 14, 0, val);
// 2 cycles, generates additional NOP
// __asm(" xout 14,&r14,4") ;
__R30 = (reg_sel << 8);
// => 30ns - 2 cycle2 for code + 1 reserve
// wait 30ns for PRU0 datout and 74LS377 setup time
__delay_cycles(7); // Test
// __delay_cycles(6); // Standard
//__delay_cycles(5) ; // possible on optimized PCB
__R30 |= (1 << 11);
}
// set register signals to standard:
// all outputs to "inactive"
// init state
// UNIBUS lines all H / only BR4567, NPR_OUT auf LOW
void buslatches_reset() {
// unsigned i;
// chips are all 8bit width, but not all input/outputs are
// connected to bidirektional terminated UNIBUS lines.
// connected to bidirectional terminated UNIBUS lines.
// see PCB schematic!
// invalidate cached register_state
// buslatches.cur_reg_sel = 0xff; // invalid
// buslatches.cur_reg_write = 1 ; // idle level is H
// init all outputs: UNIBUS lines now all H = inactive
// init all outputs and register caches:
// UNIBUS lines now all H = inactive
buslatches_setbits(0, 0xff, 0x1f); // BG,NPG OUT: inactive = driver H = UNIBUS L
buslatches_setbits(1, 0xff, 0x00); // all other: inactive = driver L = UNIBUS H
@@ -64,41 +142,158 @@ void buslatches_reset() {
buslatches_setbyte(5, 0x00);
buslatches_setbyte(6, 0x00);
buslatches_setbits(7, 0xff, 0x00);
// standard position: select register 4 with MSYN/SSYM
// buslatches_setval(4, 0xff, 0x00);
}
#ifdef USED
/*
* read the REG_DATIN[0..7] pins
*/
uint8_t _buslatches_getval(uint8_t reg_sel) {
// assert(reg_sel < 8);
// assert: REG_WRITE always L
// Test burst of 8 bus latch accesses in read/write mix in max speed
// input/output from mailbox.buslatch_exerciser
// Register access sequence given by addr[] list
// Does not test fast write-after-read
void buslatches_exerciser() {
// Max speed:
// - unroll the test loops
// - copy volatile indexed array data to local registers
uint8_t addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7;
uint8_t val0, val1, val2, val3, val4, val5, val6, val7;
addr0 = mailbox.buslatch_exerciser.addr[0];
addr1 = mailbox.buslatch_exerciser.addr[1];
addr2 = mailbox.buslatch_exerciser.addr[2];
addr3 = mailbox.buslatch_exerciser.addr[3];
addr4 = mailbox.buslatch_exerciser.addr[4];
addr5 = mailbox.buslatch_exerciser.addr[5];
addr6 = mailbox.buslatch_exerciser.addr[6];
addr7 = mailbox.buslatch_exerciser.addr[7];
val0 = mailbox.buslatch_exerciser.writeval[0];
val1 = mailbox.buslatch_exerciser.writeval[1];
val2 = mailbox.buslatch_exerciser.writeval[2];
val3 = mailbox.buslatch_exerciser.writeval[3];
val4 = mailbox.buslatch_exerciser.writeval[4];
val5 = mailbox.buslatch_exerciser.writeval[5];
val6 = mailbox.buslatch_exerciser.writeval[6];
val7 = mailbox.buslatch_exerciser.writeval[7];
// Always one of the input latches is driving the GPIOs
// see MAILBOX_BUSLATCH_EXERCISER_PATTERN_COUNT
if (buslatches.cur_reg_sel != reg_sel) {
// repeated read to same address, or read after write,
// don't need register setup and latch delay
// select is PRU1_<8:10>
// WRITE is PRU1_11, always H
__R30 = (reg_sel << 8) | (1 << 11);
buslatches.cur_reg_sel = reg_sel;
// setup time for 74ac138: worst 10ns
// setup time for 74LV541: 40ns at 3.3V
// (setup time for 74lcx244: < 10ns !)
// -> 8 cycles need, 2 already passed
// Timing by code execution DANGEROUS if optimizer re-arranges!
__delay_cycles(9);// 6 calculated, but not enough !!!!
switch (mailbox.buslatch_exerciser.pattern % MAILBOX_BUSLATCH_EXERCISER_PATTERN_COUNT) {
// now high-speed parts
case 0: // byte accesses, UNIBUS signals
buslatches_setbyte(addr0,val0)
;
buslatches_setbyte(addr1,val1)
;
buslatches_setbyte(addr2,val2)
;
buslatches_setbyte(addr3,val3)
;
buslatches_setbyte(addr4,val4)
;
buslatches_setbyte(addr5,val5)
;
buslatches_setbyte(addr6,val6)
;
buslatches_setbyte(addr7,val7)
;
// here a read-after-write transition
val0 = buslatches_getbyte(addr0);
val1 = buslatches_getbyte(addr1);
val2 = buslatches_getbyte(addr2);
val3 = buslatches_getbyte(addr3);
val4 = buslatches_getbyte(addr4);
val5 = buslatches_getbyte(addr5);
val6 = buslatches_getbyte(addr6);
val7 = buslatches_getbyte(addr7);
break;
case 1: // bit accesses, UNIBUS signals
buslatches_setbits(addr0, 0xff, val0)
;
buslatches_setbits(addr1, 0xff, val1)
;
buslatches_setbits(addr2, 0xff, val2)
;
buslatches_setbits(addr3, 0xff, val3)
;
buslatches_setbits(addr4, 0xff, val4)
;
buslatches_setbits(addr5, 0xff, val5)
;
buslatches_setbits(addr6, 0xff, val6)
;
buslatches_setbits(addr7, 0xff, val7)
;
val0 = buslatches_getbyte(addr0);
val1 = buslatches_getbyte(addr1);
val2 = buslatches_getbyte(addr2);
val3 = buslatches_getbyte(addr3);
val4 = buslatches_getbyte(addr4);
val5 = buslatches_getbyte(addr5);
val6 = buslatches_getbyte(addr6);
val7 = buslatches_getbyte(addr7);
break;
case 2: // fast alteration of bit and byte accesses, r/w sequential
// pattern: byte byte bit byte byte bit bit bit
buslatches_setbyte(addr0, val0)
;
buslatches_setbyte(addr1, val1)
;
buslatches_setbits(addr2, 0xff, val2)
;
buslatches_setbyte(addr3, val3)
;
buslatches_setbyte(addr4, val4)
;
buslatches_setbits(addr5, 0xff, val5)
;
buslatches_setbits(addr6, 0xff, val6)
;
buslatches_setbits(addr7, 0xff, val7)
;
val0 = buslatches_getbyte(addr0);
val1 = buslatches_getbyte(addr1);
val2 = buslatches_getbyte(addr2);
val3 = buslatches_getbyte(addr3);
val4 = buslatches_getbyte(addr4);
val5 = buslatches_getbyte(addr5);
val6 = buslatches_getbyte(addr6);
val7 = buslatches_getbyte(addr7);
break;
case 3: // fast alteration of write and read
// pattern: w w w w r w r w r w r w r r r r
// i i y y i y i y
buslatches_setbits(addr0, 0xff, val0)
;
buslatches_setbits(addr1, 0xff, val1)
;
buslatches_setbyte(addr2, val2)
;
buslatches_setbyte(addr3, val3)
;
val0 = buslatches_getbyte(addr0);
buslatches_setbits(addr4, 0xff, val4)
;
val1 = buslatches_getbyte(addr1);
buslatches_setbyte(addr5, val5)
;
val2 = buslatches_getbyte(addr2);
buslatches_setbits(addr6, 0xff, val6)
;
val3 = buslatches_getbyte(addr3);
buslatches_setbyte(addr7, val7)
;
val4 = buslatches_getbyte(addr4);
val5 = buslatches_getbyte(addr5);
val6 = buslatches_getbyte(addr6);
val7 = buslatches_getbyte(addr7);
break;
}
// input latches now switch, value at PRU1_<0:7>
return __R31 & 0xff;
// write back read values
mailbox.buslatch_exerciser.readval[0] = val0;
mailbox.buslatch_exerciser.readval[1] = val1;
mailbox.buslatch_exerciser.readval[2] = val2;
mailbox.buslatch_exerciser.readval[3] = val3;
mailbox.buslatch_exerciser.readval[4] = val4;
mailbox.buslatch_exerciser.readval[5] = val5;
mailbox.buslatch_exerciser.readval[6] = val6;
mailbox.buslatch_exerciser.readval[7] = val7;
}
#endif
#ifdef USED
// transfers a value in r14 to PRU0
@@ -116,46 +311,6 @@ void pru1_pru0_dataout(uint32_t val) {
}
#endif
#ifdef USED
/*
* write the REG_DATOUT[0..7] pins into one latch
* only bits "bitmask" are written
* cllaed with literal values for reg_sel and bitmask
* verify inlining! (--auto_inline=)
*/
void _buslatches_setval(uint8_t reg_sel, uint8_t bitmask, uint8_t val) {
// assert(reg_sel < 8);
// merge new value with existing latch content
val = (buslatches.cur_reg_val[reg_sel] & ~bitmask) | (val & bitmask);
// set data. outputs on PRU0_<0:7>
// critical timing: PRU0 code may need 35 ns, so set it first
pru_pru_mailbox.pru0_r30 = val;// signal PRU0
// select is PRU1_<8:10>
__R30 = (reg_sel << 8);
// WRITE is PRU1_11, set L to prepare L->H pulse
// No optimization for unchanged reg_select here:
// We still have to wait for PRU0 outputting data
buslatches.cur_reg_sel = reg_sel;
// setup time for 74ac138: worst 10ns
// add another 10ns, security for PRU0 delay
// worst case is PRU0 loop: 40ns, here 3 cycles passed. can be trimmed down?
__delay_cycles(5);
// E0 at 74LS377 reached
// strobe WRITE L->H, latch data and WRITE back to idle
__R30 = (reg_sel << 8) | (1 << 11);
buslatches.cur_reg_val[reg_sel] = val;// remember state
}
#endif
/* Emulate a power cycle with ACLO/DCLO patterns
*/
void buslatches_powercycle() {
@@ -184,6 +339,13 @@ volatile register uint32_t __R31;
// #define TEST_CROSSTALK
// #define TEST_WRITE_READ_VERIFY
// 8 OK?
#define buslatches_test_get(reg_sel,resvar) do { \
__R30 = ((reg_sel) << 8) | (1 << 11) ; \
__delay_cycles(10) ; \
resvar = __R31 & 0xff ; \
} while(0)
void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d) {
// be sure the PRU1 GPI are in "Direct Input Mode"
@@ -195,7 +357,7 @@ void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d) {
#ifdef TEST_66MHZ
while (1) {
__R30 |= (1 << 12); // set PRU1.12
__R30 &= ~(1 << 12); // clear PRU1.12
__R30 &= ~(1 << 12);// clear PRU1.12
}
#endif
@@ -206,17 +368,17 @@ void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d) {
while (1) {
__R30 |= (1 << 12); // set PRU1.12
while (!(__R31 & 0x80))
;// wait until readback on DATAIN7
; // wait until readback on DATAIN7
__R30 &= ~(1 << 12);// clear PRU1.12
__R30 &= ~(1 << 12); // clear PRU1.12
while (__R31 & 0x80)
;// wait until readback on DATAIN7
; // wait until readback on DATAIN7
}
#endif
#ifdef TEST_CROSSTALK
// const pattern of 00 ff 00 ff on latch inputs.
// register selct causes fast switch of all 8 DATAIN.
// register selcet causes fast switch of all 8 DATAIN.
// Crosstalk on logic analyzers?
a = c = 0x00;
b = d = 0xff;
@@ -233,17 +395,17 @@ void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d) {
while (mailbox.arm2pru_req == ARM2PRU_BUSLATCH_TEST) {
uint8_t resvar;
// echo DATA0 read only
buslatches_get2(2,resvar);
DEBUG_PIN_SET(buslatches_get(2) != a);
buslatches_test_get(2,resvar);
DEBUG_PIN_SET(buslatches_getbyte(2) != a);
// buslatches_debug_set(resvar & 1);
buslatches_get2(3,resvar);
DEBUG_PIN_SET(buslatches_get(3) != b);
buslatches_test_get(3,resvar);
DEBUG_PIN_SET(buslatches_getbyte(3) != b);
//buslatches_debug_set(resvar & 1);
buslatches_get2(5,resvar);
DEBUG_PIN_SET(buslatches_get(5) != c);
buslatches_test_get(5,resvar);
DEBUG_PIN_SET(buslatches_getbyte(5) != c);
//buslatches_debug_set(resvar & 1);
buslatches_get2(6,resvar);
DEBUG_PIN_SET(buslatches_get(6) != d);
buslatches_test_get(6,resvar);
DEBUG_PIN_SET(buslatches_getbyte(6) != d);
//buslatches_debug_set(resvar & 1);
}
#endif
@@ -260,16 +422,16 @@ void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d) {
;
buslatches_setbyte(5, c)
;
if (buslatches_get(2) != a)
if (buslatches_getbyte(2) != a)
DEBUG_PIN_PULSE_100NS
;// show error flag. cleared by next reg_sel
buslatches_setbyte(6, d)
;
if (buslatches_get(3) != b)
if (buslatches_getbyte(3) != b)
DEBUG_PIN_PULSE_100NS;
if (buslatches_get(5) != c)
if (buslatches_getbyte(5) != c)
DEBUG_PIN_PULSE_100NS;
if (buslatches_get(6) != d)
if (buslatches_getbyte(6) != d)
DEBUG_PIN_PULSE_100NS;
a++;
b++;

188
10.01_base/2_src/pru1/pru1_buslatches.h
View File

@@ -1,33 +1,34 @@
/* pru1_buslatches.h: PRU function to access to multiplex signal registers
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
*/
12-nov-2018 JH entered beta phase
*/
#ifndef _BUSLATCH_H_
#define _BUSLATCH_H_
#include <stdint.h>
#include "tuning.h"
#include "pru_pru_mailbox.h"
typedef struct {
@@ -47,7 +48,6 @@ typedef struct {
extern buslatches_t buslatches;
#endif
/*
* Read timing:
* 5ns on PRU to ouptput 0/1 level
@@ -56,137 +56,85 @@ extern buslatches_t buslatches;
* 5ns for changing edge voltage level of DATIN signals
* 5ns for PRU to sync with DATIN signals
*
* timing verifyed with buslatches_test()!
* 74LV541: delay(10)
* 74LVTH541: delay()
* Timing verified with buslatches_test().
*
* With optimized circuitry (PCB 2018-12, adapted terminators, 74AHC138):
* BBB can reach __delay_cycles(8)
* BBG can reach *ALMOST* __delay_cycles(9)
* */
#define buslatches_get(reg_sel) ( \
( __R30 = ((reg_sel) << 8) | (1 << 11), \
__delay_cycles(10) \
), \
(__R31 & 0xff) \
#define buslatches_getbyte(reg_sel) ( \
( __R30 = ((reg_sel) << 8) | (1 << 11), \
__delay_cycles(BUSLATCHES_GETBYTE_DELAY) \
), \
(__R31 & 0xff) \
)
// 8 OK?
#define buslatches_get2(reg_sel,resvar) do { \
__R30 = ((reg_sel) << 8) | (1 << 11) ; \
__delay_cycles(10) ; \
resvar = __R31 & 0xff ; \
} while(0)
// identify register which must be set byte-wise
#define BUSLATCH_REG_IS_BYTE(reg_sel) ( \
((reg_sel) == 2) || ((reg_sel) == 3) || ((reg_sel) == 6) || ((reg_sel) == 7) \
#define BUSLATCHES_REG_IS_BYTE(reg_sel) ( \
((reg_sel) == 2) || ((reg_sel) == 3) || ((reg_sel) == 5) || ((reg_sel) == 6) \
)
/*******************************************************************************
Timing write latches 74xx377
1 char = 5ns
lower letter = program event
Upper letter = circuit event
1 char = 5ns
lower letter = program event
Upper letter = circuit event
Circuit timing 74HCT377: (74LS a few percent faster)
---------------------------------------------------
Reference = Clock L->H = E
A-E = Setup E* = 22 ns (typ. 12)
C-E = Setup Data = 12 ns (typ. 4)
D-E = pulsewidth = 20ns (typ. 8)
E-B = setup E* = 22 ns (typ 12) deselect
Circuit timing 74HCT377: (74LS a few percent faster)
---------------------------------------------------
Reference = Clock L->H = E
A-E = Setup E* = 22 ns (typ. 12)
C-E = Setup Data = 12 ns (typ. 4)
D-E = pulsewidth = 20ns (typ. 8)
E-B = setup E* = 22 ns (typ 12) deselect
a A b B
(A-B)Select E* ------______--
c C
(C) Data XXXXXXXX--XXXX
dD eE
(D+E) Strobe CP ---____---
a A b B
(A-B)Select E* ------______--
c C
(C) Data XXXXXXXX--XXXX
dD eE
(D+E) Strobe CP ---____---
=> ac -> d = 10ns (minimal)
d -> be = 15ns
=> ac -> d = 10ns (minimal)
d -> be = 15ns
Delay program-circuit
Delay program-circuit
a-A: 5 + 10 ns (PRU + 3:8 74ac138)
b-B = a-A
c-D: 25ns (pru1_buslatches_pru0_datout.asmsrc)
d-D: 5ns
e-E: 5ns
*******************************************************************************/
#define REGWRITE_SETUP_CYCLES 6 /* errors with 3 */
a-A: 5 + 10 ns (PRU + 3:8 74ac138)
b-B = a-A
c-D: 25ns (pru1_buslatches_pru0_datout.asmsrc)
d-D: 5ns
e-E: 5ns
*******************************************************************************/
#define buslatches_setbits(reg_sel,bitmask,val) do { \
uint8_t _tmpval ; \
/* assert(reg_sel < 8); */\
\
/* merge new value with existing latch content */\
_tmpval = (buslatches.cur_reg_val[reg_sel] & ~(bitmask)) | ((val) & (bitmask)); \
\
/* set data. outputs on PRU0_<0:7> */\
/* TODO: OPTIMIZE THIS. regsel first? PRU0 first? Signal quality? */\
/* critical timing: PRU0 code may need 25 ns, so set it first */\
/*pru_pru_mailbox.pru0_r30 = _tmpval; signal PRU0 */\
buslatches_pru0_dataout(_tmpval) ; \
\
/* select is PRU1_<8:10> */\
/* WRITE is PRU1_11, set L to prepare L->H pulse */\
__R30 = (reg_sel << 8); \
\
/* setup time for 74ac138: worst 10ns */\
/* add another 10ns, security for PRU0 delay */\
/* worst case is PRU0 loop: 40ns, here 5 cycles passed. */\
buslatches.cur_reg_val[reg_sel] = _tmpval; /* remember state */ \
\
__delay_cycles(REGWRITE_SETUP_CYCLES-2); /* errors with 3 */ \
/* "-2": extra time for "cur_regval =" */ \
/* E0 at 74LS377 reached */ \
\
/* strobe WRITE L->H, latch data and WRITE back to idle */\
__R30 = (reg_sel << 8) | (1 << 11); \
\
buslatches_setbits_helper( \
/*val=*/(buslatches.cur_reg_val[reg_sel] & ~(bitmask)) | ((val) & (bitmask)), \
reg_sel, &buslatches.cur_reg_val[reg_sel] ) ; \
} while(0)
void buslatches_setbits_helper(uint32_t val /*R14*/, uint32_t reg_sel /* R15 */,
uint8_t *cur_reg_val /* R16 */);
// set a register as byte.
// no value caching, so register may never be accessed bitwise
// only to be used for 2 (addr0..7), 3 (adr 8..15), 5 (data0..7), 6(data 8..15)
#define buslatches_setbyte(reg_sel,val) do { \
/* set data. outputs on PRU0_<0:7> */\
/* TODO: OPTIMIZE THIS. regsel first? PRU0 first? Signal quality? */\
/* critical timing: PRU0 code may need 35 ns, so set it first */\
/*pru_pru_mailbox.pru0_r30 = _tmpval; signal PRU0 */\
buslatches_pru0_dataout(val) ; \
\
/* select is PRU1_<8:10> */\
/* WRITE is PRU1_11, set L to prepare L->H pulse */\
__R30 = ((reg_sel) << 8); \
\
/* setup time for 74ac138: worst 10ns */\
/* add another 10ns, security for PRU0 delay */\
/* worst case is PRU0 loop: 25ns, here 5 cycles passed. */\
__delay_cycles(REGWRITE_SETUP_CYCLES); /* errors with 3 */ \
/* E0 at 74LS377 reached */ \
\
/* strobe WRITE L->H, latch data and WRITE back to idle */\
__R30 = ((reg_sel) << 8) | (1 << 11); \
\
} while(0)
buslatches_setbyte_helper(val,reg_sel) ; \
} while(0)
void buslatches_setbyte_helper(uint32_t val /*R14*/, uint32_t reg_sel /* R15 */);
void buslatches_reset(void);
// real subroutines, for debugging
uint8_t _buslatches_getval(uint8_t reg_sel);
void _buslatches_setval(uint8_t reg_sel, uint8_t bitmask, uint8_t val);
// extern "C" {
void buslatches_pru0_dataout(uint32_t val) ;
void buslatches_powercycle(void);
void buslatches_test(uint8_t a, uint8_t b,uint8_t c, uint8_t d) ;
void buslatches_exerciser(void) ;
void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d);
#endif

51
10.01_base/2_src/pru1/pru1_buslatches_pru0_datout.asmsrc
View File

@@ -1,51 +0,0 @@
; pru1_buslatches_pru0_datout.asmsrc: transfer R14 to PRU0 over XFR
;
; Copyright (c) 2018, Joerg Hoppe
; j_hoppe@t-online.de, www.retrocmp.com
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
; JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;
;
; 12-nov-2018 JH entered beta phase
;
;
; Assembler function, which transfers r14 to PRU0
; PRU0 writes this then to DATAOUT pins
;
; to be declared in C as
; extern "C" {
; void pru1_pru0_dataout(uint32_t val) ;
; }
; See Compiler 2.2 Guide, Chapter 6.6
.global buslatches_pru0_dataout
; a 32bit parameter is received in r14
; 10 ns delay
buslatches_pru0_dataout:
; do nothing at first
; Device ID 14 = "other PRU"
xout 14,&r14,4
jmp r3.w2 ; return address
; loop on pru0: 15ns
; loop:
; xin 14,&r14,4
; mov
; br loop

323
10.01_base/2_src/pru1/pru1_main.c
View File

@@ -1,323 +0,0 @@
/* pru1_main.c: main loop with mailbox cmd interface
Copyright (c) 2018, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
12-nov-2018 JH entered beta phase
from d:\RetroCmp\dec\pdp11\UniBone\91_3rd_party\pru-c-compile\pru-software-support-package\examples\am335x\PRU_gpioToggle
Test GPIO, shared mem and interrupt
a) waits until ARM writes a value to mailbox.arm2pru_req
b) ACKs the value in mailbox.arm2pru_resp, clears arm2pru_req
c) toggles 1 mio times GPIO, with delay as set by ARM
d) signal EVENT0
e) goto a
*/
#include <stdint.h>
#include <stdbool.h>
#include <pru_cfg.h>
#include "resource_table_empty.h"
#include "pru1_utils.h"
#include "pru_pru_mailbox.h"
#include "mailbox.h"
#include "ddrmem.h"
#include "iopageregister.h"
#include "pru1_buslatches.h"
#include "pru1_statemachine_arbitration.h"
#include "pru1_statemachine_dma.h"
#include "pru1_statemachine_intr.h"
#include "pru1_statemachine_slave.h"
#include "pru1_statemachine_init.h"
#include "pru1_statemachine_powercycle.h"
/* start parallel emulation of all devices,
* Process __DMA and _INTR bus master operations
*
* ! Several state machines (DMA, Powercycle, INIT,) use the same global timeout.
* ! Never execute these in parallel !
*/
static void state_emulation() {
bool ready = false;
buslatches_reset(); // all deasserted
// Reset PDP-11 with power-cycle simulation.
// Necessary, as until now NPR/NPG/BG/BR/SACK lines were "unconnected"
buslatches_powercycle();
__delay_cycles(MILLISECS(100));
// execute 2x, because M9312 boot ROMs need this
// __delay_cycles(MILLISECS(250));
// buslatches_powercycle();
ready = false;
// buslatches_pulse_debug ;
// base operation: accept and execute slave cycles
sm_slave_start();
while (!ready) {
// do all states of an access, start when MSYN found.
// slave cycles may trigger events to ARM, which changes "active" registers
// and issues interrupts
while (!sm_slave.state())
; // execute complete slave cycle, then check NPR/INTR
// update state of init lines
// INIT never asserted in the midst of a transaction, bit 3,4,5
do_event_initializationsignals();
// standard operation may be interrupt by other requests
switch (mailbox.arm2pru_req) {
case ARM2PRU_EMULATION:
// pass BG[4-7] to next device, state machine "idle"
// pass all Arbitration GRANT IN to GRANT OUT for next device.
// This is not necessary while INTR or DMA is actiove:
// INTR is only 1 cycle, DMA has SACK set all the time, aribitration
// prohibited then.
sm_arb_state_idle();
// do only forward GRANT lines if not INTR is pending,
// else our GRANT would be passed too.
break; // fast case: only slave operation
case ARM2PRU_EMULATION_STOP:
ready = true;
break;
case ARM2PRU_DMA:
// start DMA cycle
// can not run parallel with INTR levels
sm_arb_start(ARBITRATION_PRIORITY_BIT_NP);
while (!sm_arb.state()) {
// sm_slave is most time critical, as it must keep track with MSYN/SSYN bus traffic.
// so give it more cpu cycles
while (!sm_slave.state())
;
}
// now SACK held and BBSY set, slave state machine ended, since BBSY found inactive
// debug pin reset by bus access
//DEBUG_PIN_SET(1) ;
sm_dma_start();
//DEBUG_PIN_SET(1) ;
while (!sm_dma.state())
//DEBUG_PIN_SET(1) ;
;// execute dma master cycles
// a dma cycle into a device register may trigger an interrupt
// do not delete that condition
if (mailbox.arm2pru_req == ARM2PRU_DMA)
mailbox.arm2pru_req = ARM2PRU_EMULATION; // clear request
break;
case ARM2PRU_INTR:
// start one INTR cycle. May be raised in midst of slave cycle
// by ARM, if access to "active" register triggers INTR.
// no multiple levels simultaneously allowed, not parallel with DMA !
sm_arb_start(mailbox.intr.priority_bit);
// wait while INTR is accepted. This may take long time,
// if system is at high processor priority (PSW register)
while (!sm_arb.state()) {
// sm_slave is most time critical, as it must keep track with MSYN/SSYN bus traffic.
// so give it more cpu cycles
while (!sm_slave.state())
;
}
// now SACK held and BBSY set, slave state machine ended, since BBSY found inactive
sm_intr_start();
while (!sm_intr.state())
; // execute intr cycle as bus master
mailbox.arm2pru_req = ARM2PRU_EMULATION; // clear request
break;
case ARM2PRU_INITPULSE: // generate a pulse on UNIBUS INIT
// only busmaster may assert INIT. violated here!
sm_slave_start();
sm_init_start();
while (!sm_slave.state() || !sm_init.state())
;
mailbox.arm2pru_req = ARM2PRU_EMULATION; // ACK: done
break;
case ARM2PRU_POWERCYCLE: // do ACLO/DCLO power cycle
// Runs for 4* POWERCYCLE_DELAY_MS millsecs, approx 1 sec.
// perform slave states in parallel, so emulated memory
// is existent for power fail trap and reboot
sm_slave_start();
sm_powercycle_start();
while (!sm_slave.state() || !sm_powercycle.state())
;
mailbox.arm2pru_req = ARM2PRU_EMULATION; // ACK: done
break;
default: // ignore all other requestes while executing emulation
;
} // switch
} // while (!ready)
}
void main(void) {
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
// clear all tables, as backup if ARM fails todo
iopageregisters_init();
buslatches_reset(); // all deasserted
// init mailbox
mailbox.arm2pru_req = ARM2PRU_NONE;
mailbox.events.eventmask = 0;
mailbox.events.initialization_signals_prev = 0;
mailbox.events.initialization_signals_cur = 0;
while (1) {
// display opcode (active for one cycle
// __R30 = (mailbox.arm2pru_req & 0xf) << 8;
/*
mailbox.arm2pru_resp = mailbox.arm2pru_req ;
__R30 = (mailbox.arm2pru_resp & 0xf) << 8;
mailbox.arm2pru_resp = mailbox.arm2pru_req ;
}
*/
/*** Attention: arm2pru_req (and all mailbox vars) change at ANY TIME
* - ARM must set arm2pru_req as last operation on mailbox,
* memory barrier needed.
* - ARM may not access mailbox until arm2pru_req is 0
* - PRU only clears arm2pru_req after actual processing if mailbox
* ***/
switch (mailbox.arm2pru_req) {
case ARM2PRU_NONE: // == 0
// reloop
break;
case ARM2PRU_HALT:
__halt(); // that's it
break;
#ifdef USED
case ARM2PRU_MAILBOXTEST1:
// simulate a register read access.
#ifdef TEST_TIMEOUT
while (1) {
// toggle with REGSEL_0 = PRU1_8
__R30 |= (1 << 8);
// buslatches_setbits(1, BIT(6), BIT(6)) ;
TIMEOUT_SET(NANOSECS(1000));// 1 usec / level
while (!TIMEOUT_REACHED);
__R30 &= ~(1 << 8);
//buslatches_setbits(1, BIT(6), 0) ;
TIMEOUT_SET(NANOSECS(1000));
while (!TIMEOUT_REACHED);
}
#endif
// show on REG_DATAOUT
buslatches_pru0_dataout(mailbox.mailbox_test.addr);
// pru_pru_mailbox.pru0_r30 = mailbox.mailbox_test.addr & 0xff;
// __R30 = (mailbox.mailbox_test.addr & 0xf) << 8;
mailbox.mailbox_test.val = mailbox.mailbox_test.addr;
__R30 = (mailbox.arm2pru_req & 0xf) << 8; // optical ACK
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
#endif
case ARM2PRU_BUSLATCH_INIT: // set all mux registers to "neutral"
buslatches_reset();
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
case ARM2PRU_BUSLATCH_SET: { // set a mux register
// don't feed "volatile" vars into buslatch_macros !!!
uint8_t reg_sel = mailbox.buslatch.addr & 7;
uint8_t bitmask = mailbox.buslatch.bitmask;
uint8_t val = mailbox.buslatch.val;
//buslatches.cur_reg_sel = 0xff; // force new setting of reg_sel
if (BUSLATCH_REG_IS_BYTE(reg_sel))
buslatches_setbyte(reg_sel, val);
else
buslatches_setbits(reg_sel, bitmask, val);
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
}
case ARM2PRU_BUSLATCH_GET: {
// don't feed "volatile" vars into buslatch_macros !!!
uint8_t reg_sel = mailbox.buslatch.addr & 7;
// buslatches.cur_reg_sel = 0xff; // force new setting of reg_sel
mailbox.buslatch.val = buslatches_get(reg_sel);
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
}
case ARM2PRU_BUSLATCH_TEST: {
buslatches_test(mailbox.buslatch_test.addr_0_7, mailbox.buslatch_test.addr_8_15,
mailbox.buslatch_test.data_0_7, mailbox.buslatch_test.data_8_15);
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
}
case ARM2PRU_INITPULSE: // generate a pulse on UNIBUS INIT
// INIT: latch[7], bit 3
buslatches_setbits(7, BIT(3), BIT(3)); // assert INIT
__delay_cycles(MILLISECS(250)); // INIT is 250ms
buslatches_setbits(7, BIT(3), 0); // deassert INIT
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
case ARM2PRU_POWERCYCLE: // do ACLO/DCLO power cycle
buslatches_powercycle();
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
case ARM2PRU_DMA:
sm_dma_start(); // without NPR/NPG arbitration
// simply call current state function, until stopped
// parallel the BUS-slave statemachine is triggered
// by master logic.
while (!sm_dma.state())
;
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
case ARM2PRU_DDR_FILL_PATTERN:
ddrmem_fill_pattern();
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
case ARM2PRU_DDR_SLAVE_MEMORY:
// respond to UNIBUS cycles as slave and
// access DDR as UNIBUS memory.
// only debugging: all signals deasserted
buslatches_reset();
// do UNIBUS slave cycles, until ARM abort this by
// writing into mailbox.arm2pru_req
while (mailbox.arm2pru_req == ARM2PRU_DDR_SLAVE_MEMORY) {
sm_slave_start();
// do all states of an access, start when MSYN found.
while (!sm_slave.state())
;
}
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
case ARM2PRU_EMULATION:
/* start parallel emulation of all devices, */
state_emulation();
mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
break;
} // switch
} // while
}

18
10.01_base/2_src/pru1/pru1_statemachine_arbitration.c
View File

@@ -99,7 +99,7 @@ void sm_arb_start(uint8_t priority_bit) {
// pass BGIN[4-7],NPGIN to next device , if DMA engine idle
uint8_t sm_arb_state_idle() {
uint8_t tmpval;
tmpval = buslatches_get(0);
tmpval = buslatches_getbyte(0);
// forward all 5 GRANT IN inverted to GRANT OUT
buslatches_setbits(0, ARBITRATION_PRIORITY_MASK, ~tmpval)
;
@@ -111,7 +111,7 @@ uint8_t sm_arb_state_idle() {
// execute in parallel with slave!
static uint8_t sm_arb_state_1() {
uint8_t tmpval;
tmpval = buslatches_get(0);
tmpval = buslatches_getbyte(0);
// forward all lines, until idle
buslatches_setbits(0, ARBITRATION_PRIORITY_MASK, ~tmpval) ;
// wait for GRANT idle, other cycle in progress?
@@ -130,14 +130,14 @@ static uint8_t sm_arb_state_1() {
static uint8_t sm_arb_state_2() {
uint8_t tmpval;
if (buslatches_get(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
if (buslatches_getbyte(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
// cleanup: clear all REQUESTS and SACK
buslatches_setbits(1, ARBITRATION_PRIORITY_MASK| BIT(5), 0);
// Todo: signal INIT to ARM!
sm_arb.state = &sm_arb_state_idle;
return 0 ;
}
tmpval = buslatches_get(0);
tmpval = buslatches_getbyte(0);
// forward all other BG lines
// preceding arbitration must see BG removed by master on SACK
@@ -157,20 +157,20 @@ static uint8_t sm_arb_state_2() {
// then become bus master
// Forwarding of other GRANTs not necessary ... arbitrator granted us.
static uint8_t sm_arb_state_3() {
if (buslatches_get(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
if (buslatches_getbyte(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
// cleanup: clear all REQUESTS and SACk
buslatches_setbits(1, ARBITRATION_PRIORITY_MASK| BIT(5), 0);
// Todo: signal INIT to ARM!
sm_arb.state = &sm_arb_state_idle;
return 1;
}
if (buslatches_get(0) & sm_arb.priority_bit) // wait for GRANT IN to be deasserted
if (buslatches_getbyte(0) & sm_arb.priority_bit) // wait for GRANT IN to be deasserted
return 0;
// wait until old bus master cleared BBSY
if (buslatches_get(1) & BIT(6))
if (buslatches_getbyte(1) & BIT(6))
return 0;
// wait until SSYN deasserted by old slave
if (buslatches_get(4) & BIT(5))
if (buslatches_getbyte(4) & BIT(5))
return 0;
// now become new bus master: Set BBSY, Clear REQUEST
// BBSY= bit 6
@@ -207,7 +207,7 @@ set all Reqest lines in latch 1, which have bits set in mailbox.arb_request
if grants for us:
set SACK
wait for active GRANT line going LOW
wait until BBSY=== && SSYN==0 && active GRANT==0 free (long time!)
wait until BBSY==0 && SSYN==0 && active GRANT==0 free (long time!)
set BBSY
set SACK low
NO: SHOULD BE "BEFORE LAST DATA TRAMSFER BY CURRENT MASTER"

26
10.01_base/2_src/pru1/pru1_statemachine_dma.c
View File

@@ -95,7 +95,7 @@ void sm_dma_start() {
// place address and control bits onto bus, also data for DATO
// If slave address is internal (= implemented by UniBone),
// fast UNIBUS slave protocoll is generated on the bus.
// fast UNIBUS slave protocol is generated on the bus.
static uint8_t sm_dma_state_1() {
uint32_t tmpval;
uint32_t addr = mailbox.dma.cur_addr; // non-volatile snapshot
@@ -104,10 +104,12 @@ static uint8_t sm_dma_state_1() {
// uint8_t page_table_entry;
uint8_t b;
bool internal;
// should test SACK and BBSY !
if (mailbox.dma.cur_status != DMA_STATE_RUNNING || mailbox.dma.wordcount == 0)
return 1; // still stopped
if (sm_dma.cur_wordsleft == 1) {
// deassert SACK, enable next arbitration cycle
// deassert SACK before deassert BBSY
@@ -138,10 +140,10 @@ static uint8_t sm_dma_state_1() {
buslatches_setbyte(6, data >> 8); // DATA[8..15] = latch[6]
// wait 150ns, but guaranteed to wait 150ns after SSYN inactive
// prev SSYN & DATA may be still on bus, disturbes DATA
while (buslatches_get(4) & BIT(5))
while (buslatches_getbyte(4) & BIT(5))
; // wait for SSYN inactive
__delay_cycles(NANOSECS(150) - 10);
// assume 10 cycles for buslatches_get and address test
// assume 10 cycles for buslatches_getbyte and address test
// ADDR, CONTROL (and DATA) stable since 150ns, set MSYN
// use 150ns delay to check for internal address
@@ -191,7 +193,7 @@ static uint8_t sm_dma_state_1() {
// wait 150ns after MSYN, no distance to SSYN required
__delay_cycles(NANOSECS(150) - 10);
// assume 10 cycles for buslatches_get and address test
// assume 10 cycles for buslatches_getbyte and address test
// ADDR, CONTROL (and DATA) stable since 150ns, set MSYN next
// use 150ns delay to check for internal address
@@ -239,15 +241,15 @@ static uint8_t sm_dma_state_11() {
uint16_t tmpval;
sm_dma.state_timeout = TIMEOUT_REACHED;
// SSYN = latch[4], bit 5
if (!sm_dma.state_timeout && !(buslatches_get(4) & BIT(5)))
if (!sm_dma.state_timeout && !(buslatches_getbyte(4) & BIT(5)))
return 0; // no SSYN yet: wait
// SSYN set by slave (or timeout). read data
__delay_cycles(NANOSECS(75) - 6); // assume 2*3 cycles for buslatches_get
__delay_cycles(NANOSECS(75) - 6); // assume 2*3 cycles for buslatches_getbyte
// DATA[0..7] = latch[5]
tmpval = buslatches_get(5);
tmpval = buslatches_getbyte(5);
// DATA[8..15] = latch[6]
tmpval |= (buslatches_get(6) << 8);
tmpval |= (buslatches_getbyte(6) << 8);
// save in buffer
*sm_dma.dataptr = tmpval;
// mailbox.dma.words[sm_dma.cur_wordidx] = tmpval;
@@ -263,7 +265,7 @@ static uint8_t sm_dma_state_11() {
static uint8_t sm_dma_state_21() {
sm_dma.state_timeout = TIMEOUT_REACHED; // SSYN timeout?
// SSYN = latch[4], bit 5
if (!sm_dma.state_timeout && !(buslatches_get(4) & BIT(5)))
if (!sm_dma.state_timeout && !(buslatches_getbyte(4) & BIT(5)))
return 0; // no SSYN yet: wait
// SSYN set by slave (or timeout): negate MSYN, remove DATA from bus
@@ -293,8 +295,8 @@ static uint8_t sm_dma_state_99() {
sm_dma.cur_wordsleft--;
if (sm_dma.cur_wordsleft == 0)
final_dma_state = DMA_STATE_READY; // last word: stop
else if (buslatches_get(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
// only bus master (=we!) can issue INIT, so this should never be reached
else if (buslatches_getbyte(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
// only bus master (=CPU?) can issue INIT
final_dma_state = DMA_STATE_INITSTOP;
// deassert SACK after INIT, independent of remaining word count
buslatches_setbits(1, BIT(5), 0); // deassert SACK = latch[1], bit 5

351
10.01_base/2_src/pru1/pru1_statemachine_dma.c.neu
View File

@@ -1,351 +0,0 @@
/*
* Statemachine for execution of master DATO or DATI cycles.
* All references "PDP11BUS handbook 1979"
* Precondition: BBSY already asserted (arbitration got)
*
* Master reponds to INIT bystopping transactions.
* new state
*
* Start: setup dma mailbox setup with
* startaddr, wordcount, cycle, words[]
* Then sm_dma_init() ;
* sm_dma_state = DMA_STATE_RUNNING ;
* while(sm_dma_state != DMA_STATE_READY)
* sm_dma_service() ;
* state is 0 for OK, or 2 for timeout error.
* mailbox.dma.cur_addr is error location
*
* Speed: (clpru 2.2, -O3:
* Example: DATI, time SSYN- active -> (processing) -> MSYN inactive
* a) 2 states, buslatch_set/get function calls, TIMEOUT_SET/REACHED(75) -> 700ns
* b) 2 states, buslatch_set/get macro, TIMEOUT_SET/REACHED(75) -> 605ns
* c) 2 states, no TIMEOUT (75 already met) -> 430ns
* d) 1 marged state, no TIMEOUT ca. 350ns
*/
#define _PRU1_STATEMACHINE_DMA_C_
#include <stdint.h>
#include "deviceregister.h"
#include "mailbox.h"
#include "pru_pru_mailbox.h"
#include "pru1_buslatches.h"
#include "pru1_utils.h"
#include "pru1_statemachine_dma.h"
/* sometimes short timeout of 75 and 150ns are required
* 75ns between state changes is not necessary, code runs longer
* 150ns between state changes is necessary
* Overhead for extra state and TIEOUTSET/REACHED is 100ns
*/
//#define DELAY_75NS do {} while(0)
// #define TIMEOUT_SET_75NS do {} while(0)
//#define TIMEOUT_REACHED_75NS 1
statemachine_dma_t sm_dma;
// forwards ;
static uint8_t sm_dma_state_0(void);
static uint8_t sm_dma_state_1(void);
static uint8_t sm_dma_state_2(void);
static uint8_t sm_dma_state_10(void);
static uint8_t sm_dma_state_20(void);
static uint8_t sm_dma_state_30(void);
static uint8_t sm_dma_state_99(void);
static uint8_t sm_dma_state_100(void);
// dma mailbox setup with
// startaddr, wordcount, cycle, words[] ?
// "cycle" must be UNIBUS_CONTROL_DATI or UNIBUS_CONTROL_DATO
// "arb": 1, if NPR/NPG/SACK arbitration requeired
void sm_dma_start(uint8_t arb) {
mailbox.dma.cur_addr = mailbox.dma.startaddr;
sm_dma.dataptr = (uint16_t *) mailbox.dma.words; // point to start of data buffer
sm_dma.cur_wordsleft = mailbox.dma.wordcount;
if (sm_dma.cur_wordsleft == 0) {
// nothing to do: idle
mailbox.dma.cur_status = DMA_STATE_READY;
sm_dma.state = &sm_dma_state_0;
}
if (arb)
sm_dma.state = &sm_dma_state_1;
else {
// set BBSY, even we do no arbitration
buslatches_set(1, BIT(6), BIT(6))
;
sm_dma.state = &sm_dma_state_10;
}
mailbox.dma.cur_status = DMA_STATE_RUNNING;
// next call to sm_dma.state() starts state machine
}
// idle. call _start()
// execute in parallel with slave!
static uint8_t sm_dma_state_0() {
uint8_t tmpval;
// pass NPG to next device , if DMA engine idle
tmpval = buslatches_get(0) & BIT(4);
if (tmpval)
buslatches_set(0, BIT(4), BIT(4))
; // set NPG_OUT
else
buslatches_set(0, BIT(4), 0)
; // clear NPG_OUT
return 1;
}
// wait for NPG - Non processor Grant
// Assert NPR, wait for NPG, assert SACK, wait for NPG==0, set SACK=0 ,
// execute in parallel with slave!
static uint8_t sm_dma_state_1() {
buslatches_set(1, BIT(4), BIT(4))
; // NPR= latch1, bit 4
sm_dma.state = &sm_dma_state_2; // wait for NPG
return 0;
}
// wait for NPG or INIT
// execute in parallel with slave!
static uint8_t sm_dma_state_2() {
if (buslatches_get(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
sm_dma.state = &sm_dma_state_100; // cleanup
} else if (buslatches_get(0) & BIT(4)) {
// got NPG_IN
buslatches_set(0, BIT(4), 0)
; // clear NPG_OUT, block to next device
// Set BBSY, set SACK, Clear NPR
// NPR/G = Bit 4, ACK = bit 5, BBSY= bit 6
buslatches_set(1, BIT(4)|BIT(5)|BIT(6), BIT(5)|BIT(6))
;
// master should clear NPG now.
sm_dma.state = &sm_dma_state_10; // start data transfer
}
return 0;
}
// place address and control bits onto bus, also data for DATO
// If slave address is internal (= implemented by UniBone),
// fast UNIBUS slave protocoll is generated on the bus.
static uint8_t sm_dma_state_10() {
uint32_t tmpval;
uint32_t addr = mailbox.dma.cur_addr; // non-volatile snapshot
uint16_t data;
uint8_t control = mailbox.dma.control;
uint8_t internal_addr;
if (sm_dma.cur_wordsleft == 1) {
// deassert SACK, enable next arbitration cycle
// parallel to last word data transfer
buslatches_set(1, BIT(5), 0); // SACK = latch[1], bit 5
}
sm_dma.state_timeout = 0;
// addr0..7 = latch[2]
buslatches_set(2, 0xff, addr & 0xff);
// addr8..15 = latch[3]
buslatches_set(3, 0xff, (addr >> 8));
// addr 16,17 = latch[4].0,1
// C0 = latch[4], bit 2
// C1 = latch[4], bit 3
// MSYN = latch[4], bit 4
// SSYN = latch[4], bit 5
if (control == UNIBUS_CONTROL_DATO) {
tmpval = (addr >> 16) & 3;
tmpval |= BIT(3); // DATO: c1=1, c0=0
// bit 2,4,5 == 0 -> C0,MSYN,SSYN not asserted
buslatches_set(4, 0x3f, tmpval);
// write data. SSYN may still be active???
// data = mailbox.dma.words[sm_dma.cur_wordidx];
data = *sm_dma.dataptr;
buslatches_set(5, 0xff, data & 0xff); // DATA[0..7] = latch[5]
buslatches_set(6, 0xff, data >> 8); // DATA[8..15] = latch[6]
// wait 150ns, but guaranteed to wait 150ns after SSYN inactive
// prev SSYN & DATA may be still on bus, disturbes DATA
while (buslatches_get(4) & BIT(5))
; // wait for SSYN inactive
__delay_cycles(NANOSECS(150) - 10);
// assume 10 cycles for buslatches_get and address test
// ADDR, CONTROL (and DATA) stable since 150ns, set MSYN
// use 150ns delay to check for internal address
internal_addr = DEVICEREGISTER_IS_INTERNAL(addr);
// !!! optimizer may not move this around !!!
// try "volatile internal_addr" (__asm(";---") may be rearanged)
// MSYN = latch[4], bit 4
buslatches_set(4, BIT(4), BIT(4)); // master assert MSYN
if (internal_addr) {
uint8_t b;
// DATO to internal slave (fast test).
// write data into slave
switch (control) {
case UNIBUS_CONTROL_DATO:
deviceregister_write_w(addr, data);
break;
case UNIBUS_CONTROL_DATOB:
// A00=1: upper byte, A00=0: lower byte
b = (addr & 1) ? (data >> 8) : (data & 0xff);
deviceregister_write_b(addr, b); // always sucessful, addr already tested
break;
}
buslatches_set(4, BIT(5), BIT(5)); // slave assert SSYN
buslatches_set(4, BIT(4), 0); // master deassert MSYN
buslatches_set(5, 0xff, 0); // master removes data
buslatches_set(6, 0xff, 0);
buslatches_set(4, BIT(5), 0); // slave deassert SSYN
sm_dma.state = &sm_dma_state_99; // next word
} else {
// DATO to external slave
// wait for a slave SSYN
TIMEOUT_SET(NANOSECS(1000*UNIBUS_TIMEOUT_PERIOD_US));
sm_dma.state = &sm_dma_state_30; // wait SSYN DATAO
}
} else {
// DATI
tmpval = (addr >> 16) & 3;
// bit 2,3,4,5 == 0 -> C0,C1,MSYN,SSYN not asserted
buslatches_set(4, 0x3f, tmpval);
// wait 150ns after MSYN, no distance to SSYN required
__delay_cycles(NANOSECS(150) - 10);
// assume 10 cycles for buslatches_get and address test
// ADDR, CONTROL (and DATA) stable since 150ns, set MSYN next
// use 150ns delay to check for internal address
internal_addr = DEVICEREGISTER_IS_INTERNAL(addr);
// !!! optimizer may not move this around!!!
// MSYN = latch[4], bit 4
buslatches_set(4, BIT(4), BIT(4)); // master assert MSYN
if (internal_addr) {
deviceregister_read(addr, &data);
// DATI to internal slave: put MSYN/SSYN/DATA protocol onto bus,
// slave puts data onto bus
// DATA[0..7] = latch[5]
buslatches_set(5, 0xff, data & 0xff);
// DATA[8..15] = latch[6]
buslatches_set(6, 0xff, data >> 8);
// theoretically another bus member could set bits in bus addr & data ...
// if yes, we would have to read back the bus lines
*sm_dma.dataptr = data;
// mailbox.dma.words[sm_dma.cur_wordidx] = data;
buslatches_set(4, BIT(5), BIT(5)); // slave assert SSYN
buslatches_set(4, BIT(4), 0); // master deassert MSYN
buslatches_set(5, 0xff, 0); // slave removes data
buslatches_set(6, 0xff, 0);
buslatches_set(4, BIT(5), 0); // slave deassert SSYN
sm_dma.state = &sm_dma_state_99; // next word
} else {
// DATI to external slave
// wait for a slave SSYN
TIMEOUT_SET(NANOSECS(1000*UNIBUS_TIMEOUT_PERIOD_US));
sm_dma.state = &sm_dma_state_20; // wait SSYN DATI
}
}
return 0; // still running
}
// DATI to external slave: MSYN set, wait for SSYN or timeout
static uint8_t sm_dma_state_20() {
uint16_t tmpval;
sm_dma.state_timeout = TIMEOUT_REACHED;
// SSYN = latch[4], bit 5
if (!sm_dma.state_timeout && !(buslatches_get(4) & BIT(5)))
return 0; // no SSYN yet: wait
// SSYN set by slave (or timeout). read data
__delay_cycles(NANOSECS(75) - 6); // assume 2*3 cycles for buslatches_get
// DATA[0..7] = latch[5]
tmpval = buslatches_get(5);
// DATA[8..15] = latch[6]
tmpval |= (buslatches_get(6) << 8);
// save in buffer
*sm_dma.dataptr = tmpval;
// mailbox.dma.words[sm_dma.cur_wordidx] = tmpval;
// negate MSYN
buslatches_set(4, BIT(4), 0);
// DATI: remove address,control, MSYN,SSYN from bus, 75ns after MSYN inactive
__delay_cycles(NANOSECS(75) - 8); // assume 8 cycles for state change
sm_dma.state = &sm_dma_state_99;
return 0; // still running
}
// DATO to external slave: wait for SSYN or timeout
static uint8_t sm_dma_state_30() {
sm_dma.state_timeout = TIMEOUT_REACHED; // SSYN timeout?
// SSYN = latch[4], bit 5
if (!sm_dma.state_timeout && !(buslatches_get(4) & BIT(5)))
return 0; // no SSYN yet: wait
// SSYN set by slave (or timeout): negate MSYN, remove DATA from bus
buslatches_set(4, BIT(4), 0); // deassert MSYN
buslatches_set(5, 0xff, 0);
buslatches_set(6, 0xff, 0);
// DATO: remove address,control, MSYN,SSYN from bus, 75ns after MSYN inactive
__delay_cycles(NANOSECS(75) - 8); // assume 8 cycles for state change
sm_dma.state = &sm_dma_state_99;
return 0; // still running
}
// word is transfered, or timeout.
static uint8_t sm_dma_state_99() {
uint8_t final_dma_state;
// from state_12, state_21
// 2 reasons to terminate transfer
// - BUS timeout at curent address
// - last word transferred
if (sm_dma.state_timeout) {
final_dma_state = DMA_STATE_TIMEOUTSTOP;
} else {
sm_dma.dataptr++; // point to next word in buffer
sm_dma.cur_wordsleft--;
if (sm_dma.cur_wordsleft == 0) {
final_dma_state = DMA_STATE_READY; // last word: stop
sm_dma.state = &sm_dma_state_0; // idle now
} else if (buslatches_get(7) & BIT(3)) { // INIT stops transaction: latch[7], bit 3
final_dma_state = DMA_STATE_INITSTOP;
sm_dma.state = &sm_dma_state_100; // cleanup
return 0;
} else {
final_dma_state = DMA_STATE_RUNNING; // more words: continue
sm_dma.state = &sm_dma_state_10; // reloop next word
}
}
if (final_dma_state == DMA_STATE_RUNNING) {
// dataptr and wordsleft already incremented
mailbox.dma.cur_addr += 2; // signal progress to ARM
return 0;
} else {
// remove addr and control from bus
buslatches_set(2, 0xff, 0);
buslatches_set(3, 0xff, 0);
buslatches_set(4, 0x3f, 0);
// remove BBSY: latch[1], bit 6
buslatches_set(1, BIT(6), 0);
mailbox.dma.cur_status = final_dma_state; // signal to ARM
return 1; // now idle
}
}
// cleanup after INIT
static uint8_t sm_dma_state_100() {
// remove addr and control from bus
buslatches_set(2, 0xff, 0);
buslatches_set(3, 0xff, 0);
buslatches_set(4, 0x3f, 0);
// remove BBSY, SACK and NPR: latch[1], bit 6
buslatches_set(1, BIT(4)|BIT(5)|BIT(6), 0);
mailbox.dma.cur_status = DMA_STATE_INITSTOP; // signal to ARM
sm_dma.state = &sm_dma_state_0; // idle now
return 1; // now stopped
}

29
10.01_base/2_src/pru1/pru1_statemachine_dma.h.neu
View File

@@ -1,29 +0,0 @@
#ifndef _PRU1_STATEMACHINE_DMA_H_
#define _PRU1_STATEMACHINE_DMA_H_
// execution of a state. return : 1, if statemachine stopped
typedef uint8_t (*sm_dma_state_func_ptr)(void);
//static dma_state_func_ptr sm_dma_state; // current state as ptr to "state fucntion"
typedef struct {
sm_dma_state_func_ptr state; // current state as ptr to "state fucntion"
uint8_t state_timeout; // timeout occured?
uint16_t *dataptr ; // points to current word in mailbox.words[] ;
uint16_t cur_wordsleft; // # of words left to transfer
} statemachine_dma_t;
#ifndef _PRU1_STATEMACHINE_DMA_C_
extern statemachine_dma_t sm_dma;
#endif
void sm_dma_start(uint8_t arb) ;
#endif

2
10.01_base/2_src/pru1/pru1_statemachine_init.c
View File

@@ -45,7 +45,7 @@
// Assume this events come so slow, no one gets raised until
// prev event processed.
void do_event_initializationsignals() {
uint8_t tmp = buslatches_get(7) & 0x38 ;
uint8_t tmp = buslatches_getbyte(7) & 0x38 ;
if (tmp != mailbox.events.initialization_signals_cur) {
// save old state, so ARM can detect what changed
mailbox.events.initialization_signals_prev = mailbox.events.initialization_signals_cur ;

2
10.01_base/2_src/pru1/pru1_statemachine_intr.c
View File

@@ -81,7 +81,7 @@ static uint8_t sm_intr_state_1() {
// wait for SSYN
static uint8_t sm_intr_state_2() {
if (!(buslatches_get(4) & BIT(5)))
if (!(buslatches_getbyte(4) & BIT(5)))
return 0;
// received SSYN

4
10.01_base/2_src/pru1/pru1_statemachine_powercycle.c
View File

@@ -77,7 +77,9 @@ static uint8_t sm_powercycle_state_1() {
TIMEOUT_SET(MILLISECS(POWERCYCLE_DELAY_MS))
; // wait for DC power shutdown
sm_powercycle.state = &sm_powercycle_state_2;
// DEBUG_OUT(0x01) ;
do_event_initializationsignals() ;
// DEBUG_OUT(0x02) ;
return 0;
}
@@ -89,7 +91,9 @@ static uint8_t sm_powercycle_state_2() {
TIMEOUT_SET(MILLISECS(POWERCYCLE_DELAY_MS))
; // system powered off
sm_powercycle.state = &sm_powercycle_state_3;
// DEBUG_OUT(0x03) ;
do_event_initializationsignals() ;
// DEBUG_OUT(0x04) ;
return 0;
}

20
10.01_base/2_src/pru1/pru1_statemachine_slave.c
View File

@@ -72,7 +72,7 @@ static uint8_t sm_slave_state_1() {
uint8_t b;
// fast sample of busstate, should be atomic
latch4val = buslatches_get(4); // MSYN first
latch4val = buslatches_getbyte(4); // MSYN first
// MSYN active ?
if (!(latch4val & BIT(4)))
@@ -83,8 +83,8 @@ static uint8_t sm_slave_state_1() {
// checking against SSYN guarantees address if valid if fetched now.
// However, another Bus slave can SSYN immediately
latch2val = buslatches_get(2); // A0..7
latch3val = buslatches_get(3); // A8..15
latch2val = buslatches_getbyte(2); // A0..7
latch3val = buslatches_getbyte(3); // A8..15
// decode address and control
// addr0..7 = latch[2]
@@ -127,9 +127,9 @@ static uint8_t sm_slave_state_1() {
case UNIBUS_CONTROL_DATO:
// fetch data in any case
// DATA[0..7] = latch[5]
w = buslatches_get(5);
w = buslatches_getbyte(5);
// DATA[8..15] = latch[6]
w |= (uint16_t) buslatches_get(6) << 8;
w |= (uint16_t) buslatches_getbyte(6) << 8;
if (iopageregisters_write_w(addr, w)) {
//DEBUG_PIN_PULSE ; // trigger scope/LA. auto cleared on next reg_sel
@@ -148,10 +148,10 @@ static uint8_t sm_slave_state_1() {
// fetch data
if (addr & 1) {
// DATA[8..15] = latch[6]
b = buslatches_get(6);
b = buslatches_getbyte(6);
} else {
// DATA[0..7] = latch[5]
b = buslatches_get(5);
b = buslatches_getbyte(5);
}
if (iopageregisters_write_b(addr, b)) { // always sucessful, addr already tested
// SSYN = latch[4], bit 5
@@ -171,7 +171,7 @@ static uint8_t sm_slave_state_1() {
// also wait for EVENT ACK
static uint8_t sm_slave_state_10() {
// MSYN = latch[4], bit 4
if (buslatches_get(4) & BIT(4))
if (buslatches_getbyte(4) & BIT(4))
return 0; // MSYN still active
if (mailbox.events.eventmask)
return 0; // long SSYN delay until ARM acknowledges all events
@@ -189,7 +189,7 @@ static uint8_t sm_slave_state_10() {
// also wait for EVENT ACK
static uint8_t sm_slave_state_20() {
// MSYN = latch[4], bit 4
if (buslatches_get(4) & BIT(4))
if (buslatches_getbyte(4) & BIT(4))
return 0; // MSYN still active
if (mailbox.events.eventmask)
return 0; // long SSYN delay until ARM acknowledges event
@@ -210,7 +210,7 @@ static uint8_t sm_slave_state_20() {
// end of inactive cycle: wait for MSYN to go inactive
static uint8_t sm_slave_state_99() {
// MSYN = latch[4], bit 4
if (buslatches_get(4) & BIT(4))
if (buslatches_getbyte(4) & BIT(4))
return 0; // MSYN still active
sm_slave.state = &sm_slave_state_1;

11
10.01_base/2_src/pru1/pru1_utils.h
View File

@@ -119,6 +119,17 @@ http://theembeddedkitchen.net/beaglelogic-building-a-logic-analyzer-with-the-pru
__R30 &= ~(1 << 12) ; \
} while(0)
#ifdef TRASH
// set DEBUG PIN and value to PRU0 outputs
// output appear delayed by PRU0!
#define DEBUG_OUT(val) do { \
__R30 |= (1 << 12) ; \
buslatches_pru0_dataout(val) ; \
__R30 &= ~(1 << 12) ; \
} while(0)
#endif
// To signal the host that we're done, we set bit 5 in our R31
// simultaneously with putting the number of the signal we want

31
10.01_base/2_src/shared/mailbox.h
View File

@@ -32,21 +32,22 @@
#include "unibus.h"
// arm to pru
#define ARM2PRU_NONE 0
#define ARM2PRU_NONE 0 // don't change
#define ARM2PRU_HALT 1 // run PRU1 into halt
#define ARM2PRU_MAILBOXTEST1 2
#define ARM2PRU_BUSLATCH_INIT 3 // reset all mux registers to "neutral"
#define ARM2PRU_BUSLATCH_SET 4 // set a mux register
#define ARM2PRU_BUSLATCH_GET 5 // read a mux register
#define ARM2PRU_BUSLATCH_TEST 6 // read a mux register
#define ARM2PRU_INITPULSE 7 // pulse UNIBUS INIT
#define ARM2PRU_POWERCYCLE 8 // ACLO/DCLO power cycle simulation
#define ARM2PRU_DMA 9 // DMA with or without arbitration
#define ARM2PRU_DDR_FILL_PATTERN 10 // fill DDR with test pattern
#define ARM2PRU_DDR_SLAVE_MEMORY 11 // use DDR as UNIBUS slave memory
#define ARM2PRU_EMULATION 12 // start & execute device emulation loop
#define ARM2PRU_EMULATION_STOP 13 // stop device emulation loop
#define ARM2PRU_INTR 14 // INTR, only with arbitration
#define ARM2PRU_BUSLATCH_EXERCISER 6 // exercise 8 accesses to mux registers
#define ARM2PRU_BUSLATCH_TEST 7 // read a mux register
#define ARM2PRU_INITPULSE 8 // pulse UNIBUS INIT
#define ARM2PRU_POWERCYCLE 9 // ACLO/DCLO power cycle simulation
#define ARM2PRU_DMA_ARB_NONE 10 // DMA without NPR/NPG/SACK arbitration
#define ARM2PRU_DMA_ARB_CLIENT 11 // DMA with arbitration by external Arbitrator
#define ARM2PRU_DMA_ARB_MASTER 12 // DMA as Arbitrator
#define ARM2PRU_DDR_FILL_PATTERN 13 // fill DDR with test pattern
#define ARM2PRU_DDR_SLAVE_MEMORY 14 // use DDR as UNIBUS slave memory
#define ARM2PRU_INTR 15 // INTR, only with arbitration
// possible states of DMA machine
#define DMA_STATE_READY 0 // idle
@@ -83,6 +84,15 @@ typedef struct {
uint32_t val; // value set/get.
} mailbox_buslatch_t;
#define MAILBOX_BUSLATCH_EXERCISER_PATTERN_COUNT 4
typedef struct {
uint8_t pattern ; // input: which access pattern?
uint8_t addr[8] ; // access sequence of register addresses
uint8_t writeval[8] ; // data value for each
uint8_t readval[8] ; // read back results
} mailbox_buslatch_exerciser_t;
typedef struct {
uint8_t addr_0_7; // start values for test sequence
uint8_t addr_8_15;
@@ -155,6 +165,7 @@ typedef struct {
mailbox_test_t mailbox_test;
mailbox_buslatch_t buslatch;
mailbox_buslatch_test_t buslatch_test;
mailbox_buslatch_exerciser_t buslatch_exerciser;
mailbox_dma_t dma;
mailbox_intr_t intr;
};

89
10.01_base/2_src/shared/tuning.h Normal file
View File

@@ -0,0 +1,89 @@
/* tuning.h: Constants to adapt UNIBUS functions
Copyright (c) 2019, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7-jun-2019 JH entered beta phase
*/
#define TUNING_PCB_LEGACY_SECURE
//#define TUNING_PCB_2018_12_OPTIMIZED
//#define TUNING_PCB_TEST
/*** Wait cycles for buslatch access. Depends on PCB, used chips and alofirth ***/
// A BBB with optimized terminators can reach 8
// BBG can reach *ALMOST* 9
// #define BUSLATCHES_GETBYTE_DELAY 10 // Standard
#if defined(TUNING_PCB_TEST)
// experimental to test error rates
#define BUSLATCHES_GETBYTE_DELAY 10
#define BUSLATCHES_SETBITS_DELAY 2
#define BUSLATCHES_SETBYTE_DELAY 6
#elif defined(TUNING_PCB_LEGACY_SECURE)
/* Secure setting for PCBs <= 2018-12, delivered before June 2019.
Necessary for longtime ZKMA on critical PCBs.
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138
RN8,9 (DATIN) : 47
RN10 <1:6>(REGADR): 33
RN10 <7:8>(REGWRITE): 33
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22
RN4,RN5 [[/DATOUT]] end) -> 1K/-
*/
#define BUSLATCHES_GETBYTE_DELAY 11
#define BUSLATCHES_SETBITS_DELAY 5
#define BUSLATCHES_SETBYTE_DELAY 7
#elif defined(TUNING_PCB_2018_12_OPTIMIZED)
/* Setting for PCB v2018_12 with optimized timing (ticket 21, June 2019)
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138 -> 74AHC138
RN8,9 (DATIN) : 47 -> 68 Ohm
RN10 <1:6>(REGADR): 33->0 Ohm
RN10 <7:8>(REGWRITE): 33->0 Ohm
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22 -> 27
RN4,RN5 [[/DATOUT]] end) -> 180/-
*/
#define BUSLATCHES_GETBYTE_DELAY 9
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
//#define BUSLATCHES_GETBYTE_DELAY 8
//#define BUSLATCHES_SETBITS_DELAY 3
//#define BUSLATCHES_SETBYTE_DELAY 5
#endif
// UNIBUS timing: Wait to stabilize DATA before MSYN asserted
// per DEC spec
// #define UNIBUS_DMA_MASTER_PRE_MSYN_NS 150
// Josh Dersch on 11/84, also for VAX 11/750
// Addtional delay on PDP11s with private memory interconnect (PMI)
// and UNIBUS/PMI translation?
// Experiments with "250" made still occasional errors.
#define UNIBUS_DMA_MASTER_PRE_MSYN_NS 350

36
10.01_base/2_src/shared/unibus.h
View File

@@ -34,6 +34,7 @@
#define UNIBUS_WORDCOUNT 0x20000 // 128KiW = 256 KiB
// bus transaction. can be directly assigned to lines C1,C0
#define UNIBUS_CONTROL_DATI 0x00 // 16 bit word from slave to master
#define UNIBUS_CONTROL_DATIP 0x01 // DATI, inhibts core restore. DATO must follow.
@@ -64,22 +65,19 @@ typedef struct {
// parameter and functions for low level UNIBUS control
class unibus_c: public logsource_c {
private:
public:
enum arbitration_mode_enum {
ARBITRATION_MODE_NONE = 0, // no BR*/BG*, NR/NPG SACK protocoll
ARBITRATION_MODE_CLIENT = 1, // external Arbitrator (running PDP-11 CPU) required
ARBITRATION_MODE_MASTER = 2 // implmenet Arbitrator
// with or without physical CPU for arbitration
} ;
bool emulation_logic_started = false;
// save required test values for control on read back
private:
timeout_c timeout;
public:
/* Global flag describing PDP-11 condition:
* Is there a PDP-11 CPU doing NPR or INTR arbitration?
* "false", if
* - no CPU plugged in,
* - or CPU HALTED and console processor inhibts arbitration with SACK.
* INTR tests needs a PDP-11 CPU for arbitration.
*/
bool arbitration_active = false;
// percent of time to be used for DMA master cycles
unsigned dma_bandwidth_percent ;
@@ -95,23 +93,21 @@ public:
void powercycle(void) ;
void interrupt(uint8_t priority, uint16_t vector) ;
bool dma(uint8_t control, uint32_t startaddr,
bool dma(enum unibus_c::arbitration_mode_enum arbitration_mode, uint8_t control, uint32_t startaddr,
unsigned blocksize);
void mem_read(uint16_t *words, uint32_t start_addr,
void mem_read(enum unibus_c::arbitration_mode_enum arbitration_mode,
uint16_t *words, uint32_t start_addr,
uint32_t end_addr, unsigned blocksize, bool *timeout) ;
void mem_write(uint16_t *words, unsigned start_addr,
void mem_write(enum unibus_c::arbitration_mode_enum arbitration_mode,
uint16_t *words, unsigned start_addr,
unsigned end_addr, unsigned blocksize, bool *timeout) ;
uint32_t test_sizer(void) ;
uint32_t test_sizer(enum unibus_c::arbitration_mode_enum arbitration_mode) ;
uint16_t testwords[UNIBUS_WORDCOUNT];
void test_mem(uint32_t start_addr, uint32_t end_addr, unsigned mode) ;
void emulation_logic_start(void) ;
void emulation_logic_stop(void) ;
void test_mem(enum unibus_c::arbitration_mode_enum arbitration_mode, uint32_t start_addr, uint32_t end_addr, unsigned mode) ;
};

282
10.01_base/4_deploy/pru0.map
View File

@@ -1,282 +0,0 @@
******************************************************************************
PRU Linker Unix v2.3.1
******************************************************************************
>> Linked Sun Mar 31 20:55:28 2019
OUTPUT FILE NAME: </home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0.out>
ENTRY POINT SYMBOL: "_c_int00_noinit_noargs" address: 00000000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
PRU_IMEM 00000000 00002000 0000005c 00001fa4 RWIX
PAGE 1:
PRU_DMEM_0_1 00000000 00002000 00000114 00001eec RWIX
PRU_DMEM_1_0 00002000 00002000 00000000 00002000 RWIX
PAGE 2:
PRU_SHAREDMEM 00010000 00003000 00000000 00003000 RWIX
PRU_INTC 00020000 00001504 00000000 00001504 RWIX
PRU_CFG 00026000 00000044 00000044 00000000 RWIX
PRU_UART 00028000 00000038 00000000 00000038 RWIX
PRU_IEP 0002e000 0000031c 00000000 0000031c RWIX
PRU_ECAP 00030000 00000060 00000000 00000060 RWIX
RSVD27 00032000 00000100 00000000 00000100 RWIX
RSVD21 00032400 00000100 00000000 00000100 RWIX
L3OCMC 40000000 00010000 00000000 00010000 RWIX
MCASP0_DMA 46000000 00000100 00000000 00000100 RWIX
UART1 48022000 00000088 00000000 00000088 RWIX
UART2 48024000 00000088 00000000 00000088 RWIX
I2C1 4802a000 000000d8 00000000 000000d8 RWIX
MCSPI0 48030000 000001a4 00000000 000001a4 RWIX
DMTIMER2 48040000 0000005c 00000000 0000005c RWIX
MMCHS0 48060000 00000300 00000000 00000300 RWIX
MBX0 480c8000 00000140 00000000 00000140 RWIX
SPINLOCK 480ca000 00000880 00000000 00000880 RWIX
I2C2 4819c000 000000d8 00000000 000000d8 RWIX
MCSPI1 481a0000 000001a4 00000000 000001a4 RWIX
DCAN0 481cc000 000001e8 00000000 000001e8 RWIX
DCAN1 481d0000 000001e8 00000000 000001e8 RWIX
PWMSS0 48300000 000002c4 00000000 000002c4 RWIX
PWMSS1 48302000 000002c4 00000000 000002c4 RWIX
PWMSS2 48304000 000002c4 00000000 000002c4 RWIX
RSVD13 48310000 00000100 00000000 00000100 RWIX
RSVD10 48318000 00000100 00000000 00000100 RWIX
TPCC 49000000 00001098 00000000 00001098 RWIX
GEMAC 4a100000 0000128c 00000000 0000128c RWIX
DDR 80000000 00000100 00000000 00000100 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.text:_c_int00*
* 0 00000000 0000001c
00000000 0000001c rtspruv3_le.lib : boot.c.obj (.text:_c_int00_noinit_noargs)
.text 0 0000001c 00000040
0000001c 00000024 pru0_main.object (.text:main)
00000040 0000000c pru0_datout.asmobject (.text)
0000004c 00000008 rtspruv3_le.lib : exit.c.obj (.text:abort)
00000054 00000008 : exit.c.obj (.text:loader_exit)
.stack 1 00000000 00000100 UNINITIALIZED
00000000 00000004 rtspruv3_le.lib : boot.c.obj (.stack)
00000004 000000fc --HOLE--
.cinit 1 00000000 00000000 UNINITIALIZED
.resource_table
* 1 00000100 00000014
00000100 00000014 pru0_main.object (.resource_table:retain)
.creg.PRU_CFG.noload.near
* 2 00026000 00000044 NOLOAD SECTION
00026000 00000044 pru0_main.object (.creg.PRU_CFG.noload.near)
.creg.PRU_CFG.near
* 2 00026044 00000000 UNINITIALIZED
.creg.PRU_CFG.noload.far
* 2 00026044 00000000 NOLOAD SECTION
.creg.PRU_CFG.far
* 2 00026044 00000000 UNINITIALIZED
MODULE SUMMARY
Module code ro data rw data
------ ---- ------- -------
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/
pru0_main.object 36 0 88
pru0_datout.asmobject 12 0 0
+--+-----------------------+------+---------+---------+
Total: 48 0 88
/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//lib/rtspruv3_le.lib
boot.c.obj 28 0 0
exit.c.obj 16 0 0
+--+-----------------------+------+---------+---------+
Total: 44 0 0
Stack: 0 0 256
+--+-----------------------+------+---------+---------+
Grand Total: 92 0 344
SEGMENT ATTRIBUTES
id tag seg value
-- --- --- -----
0 PHA_PAGE 1 1
1 PHA_PAGE 2 1
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
page address name
---- ------- ----
0 00000054 C$$EXIT
2 00026000 CT_CFG
abs 481cc000 __PRU_CREG_BASE_DCAN0
abs 481d0000 __PRU_CREG_BASE_DCAN1
abs 80000000 __PRU_CREG_BASE_DDR
abs 48040000 __PRU_CREG_BASE_DMTIMER2
abs 4a100000 __PRU_CREG_BASE_GEMAC
abs 4802a000 __PRU_CREG_BASE_I2C1
abs 4819c000 __PRU_CREG_BASE_I2C2
abs 40000000 __PRU_CREG_BASE_L3OCMC
abs 480c8000 __PRU_CREG_BASE_MBX0
abs 46000000 __PRU_CREG_BASE_MCASP0_DMA
abs 48030000 __PRU_CREG_BASE_MCSPI0
abs 481a0000 __PRU_CREG_BASE_MCSPI1
abs 48060000 __PRU_CREG_BASE_MMCHS0
abs 00026000 __PRU_CREG_BASE_PRU_CFG
abs 00000000 __PRU_CREG_BASE_PRU_DMEM_0_1
abs 00002000 __PRU_CREG_BASE_PRU_DMEM_1_0
abs 00030000 __PRU_CREG_BASE_PRU_ECAP
abs 0002e000 __PRU_CREG_BASE_PRU_IEP
abs 00020000 __PRU_CREG_BASE_PRU_INTC
abs 00010000 __PRU_CREG_BASE_PRU_SHAREDMEM
abs 00028000 __PRU_CREG_BASE_PRU_UART
abs 48300000 __PRU_CREG_BASE_PWMSS0
abs 48302000 __PRU_CREG_BASE_PWMSS1
abs 48304000 __PRU_CREG_BASE_PWMSS2
abs 48318000 __PRU_CREG_BASE_RSVD10
abs 48310000 __PRU_CREG_BASE_RSVD13
abs 00032400 __PRU_CREG_BASE_RSVD21
abs 00032000 __PRU_CREG_BASE_RSVD27
abs 480ca000 __PRU_CREG_BASE_SPINLOCK
abs 49000000 __PRU_CREG_BASE_TPCC
abs 48022000 __PRU_CREG_BASE_UART1
abs 48024000 __PRU_CREG_BASE_UART2
abs 0000000e __PRU_CREG_DCAN0
abs 0000000f __PRU_CREG_DCAN1
abs 0000001f __PRU_CREG_DDR
abs 00000001 __PRU_CREG_DMTIMER2
abs 00000009 __PRU_CREG_GEMAC
abs 00000002 __PRU_CREG_I2C1
abs 00000011 __PRU_CREG_I2C2
abs 0000001e __PRU_CREG_L3OCMC
abs 00000016 __PRU_CREG_MBX0
abs 00000008 __PRU_CREG_MCASP0_DMA
abs 00000006 __PRU_CREG_MCSPI0
abs 00000010 __PRU_CREG_MCSPI1
abs 00000005 __PRU_CREG_MMCHS0
abs 00000004 __PRU_CREG_PRU_CFG
abs 00000018 __PRU_CREG_PRU_DMEM_0_1
abs 00000019 __PRU_CREG_PRU_DMEM_1_0
abs 00000003 __PRU_CREG_PRU_ECAP
abs 0000001a __PRU_CREG_PRU_IEP
abs 00000000 __PRU_CREG_PRU_INTC
abs 0000001c __PRU_CREG_PRU_SHAREDMEM
abs 00000007 __PRU_CREG_PRU_UART
abs 00000012 __PRU_CREG_PWMSS0
abs 00000013 __PRU_CREG_PWMSS1
abs 00000014 __PRU_CREG_PWMSS2
abs 0000000a __PRU_CREG_RSVD10
abs 0000000d __PRU_CREG_RSVD13
abs 00000015 __PRU_CREG_RSVD21
abs 0000001b __PRU_CREG_RSVD27
abs 00000017 __PRU_CREG_SPINLOCK
abs 0000001d __PRU_CREG_TPCC
abs 0000000b __PRU_CREG_UART1
abs 0000000c __PRU_CREG_UART2
1 00000100 __TI_STACK_END
abs 00000100 __TI_STACK_SIZE
abs ffffffff __c_args__
0 00000000 _c_int00_noinit_noargs
1 00000000 _stack
0 0000004c abort
0 0000001c main
0 00000040 pru0_dataout
1 00000100 pru_remoteproc_ResourceTable
GLOBAL SYMBOLS: SORTED BY Symbol Address
page address name
---- ------- ----
0 00000000 _c_int00_noinit_noargs
0 0000001c main
0 00000040 pru0_dataout
0 0000004c abort
0 00000054 C$$EXIT
1 00000000 _stack
1 00000100 __TI_STACK_END
1 00000100 pru_remoteproc_ResourceTable
2 00026000 CT_CFG
abs 00000000 __PRU_CREG_BASE_PRU_DMEM_0_1
abs 00000000 __PRU_CREG_PRU_INTC
abs 00000001 __PRU_CREG_DMTIMER2
abs 00000002 __PRU_CREG_I2C1
abs 00000003 __PRU_CREG_PRU_ECAP
abs 00000004 __PRU_CREG_PRU_CFG
abs 00000005 __PRU_CREG_MMCHS0
abs 00000006 __PRU_CREG_MCSPI0
abs 00000007 __PRU_CREG_PRU_UART
abs 00000008 __PRU_CREG_MCASP0_DMA
abs 00000009 __PRU_CREG_GEMAC
abs 0000000a __PRU_CREG_RSVD10
abs 0000000b __PRU_CREG_UART1
abs 0000000c __PRU_CREG_UART2
abs 0000000d __PRU_CREG_RSVD13
abs 0000000e __PRU_CREG_DCAN0
abs 0000000f __PRU_CREG_DCAN1
abs 00000010 __PRU_CREG_MCSPI1
abs 00000011 __PRU_CREG_I2C2
abs 00000012 __PRU_CREG_PWMSS0
abs 00000013 __PRU_CREG_PWMSS1
abs 00000014 __PRU_CREG_PWMSS2
abs 00000015 __PRU_CREG_RSVD21
abs 00000016 __PRU_CREG_MBX0
abs 00000017 __PRU_CREG_SPINLOCK
abs 00000018 __PRU_CREG_PRU_DMEM_0_1
abs 00000019 __PRU_CREG_PRU_DMEM_1_0
abs 0000001a __PRU_CREG_PRU_IEP
abs 0000001b __PRU_CREG_RSVD27
abs 0000001c __PRU_CREG_PRU_SHAREDMEM
abs 0000001d __PRU_CREG_TPCC
abs 0000001e __PRU_CREG_L3OCMC
abs 0000001f __PRU_CREG_DDR
abs 00000100 __TI_STACK_SIZE
abs 00002000 __PRU_CREG_BASE_PRU_DMEM_1_0
abs 00010000 __PRU_CREG_BASE_PRU_SHAREDMEM
abs 00020000 __PRU_CREG_BASE_PRU_INTC
abs 00026000 __PRU_CREG_BASE_PRU_CFG
abs 00028000 __PRU_CREG_BASE_PRU_UART
abs 0002e000 __PRU_CREG_BASE_PRU_IEP
abs 00030000 __PRU_CREG_BASE_PRU_ECAP
abs 00032000 __PRU_CREG_BASE_RSVD27
abs 00032400 __PRU_CREG_BASE_RSVD21
abs 40000000 __PRU_CREG_BASE_L3OCMC
abs 46000000 __PRU_CREG_BASE_MCASP0_DMA
abs 48022000 __PRU_CREG_BASE_UART1
abs 48024000 __PRU_CREG_BASE_UART2
abs 4802a000 __PRU_CREG_BASE_I2C1
abs 48030000 __PRU_CREG_BASE_MCSPI0
abs 48040000 __PRU_CREG_BASE_DMTIMER2
abs 48060000 __PRU_CREG_BASE_MMCHS0
abs 480c8000 __PRU_CREG_BASE_MBX0
abs 480ca000 __PRU_CREG_BASE_SPINLOCK
abs 4819c000 __PRU_CREG_BASE_I2C2
abs 481a0000 __PRU_CREG_BASE_MCSPI1
abs 481cc000 __PRU_CREG_BASE_DCAN0
abs 481d0000 __PRU_CREG_BASE_DCAN1
abs 48300000 __PRU_CREG_BASE_PWMSS0
abs 48302000 __PRU_CREG_BASE_PWMSS1
abs 48304000 __PRU_CREG_BASE_PWMSS2
abs 48310000 __PRU_CREG_BASE_RSVD13
abs 48318000 __PRU_CREG_BASE_RSVD10
abs 49000000 __PRU_CREG_BASE_TPCC
abs 4a100000 __PRU_CREG_BASE_GEMAC
abs 80000000 __PRU_CREG_BASE_DDR
abs ffffffff __c_args__
[75 symbols]

BIN
10.01_base/4_deploy/pru0.out
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66
10.01_base/4_deploy/pru0_config.c
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@@ -1,66 +0,0 @@
/*** Following code generated by "/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/update_pru_config.sh 0 pru0_array.c /home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_config /home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0.map" ***/
#define _PRU0_CONFIG_C_
#include <stdint.h>
// under c++ linker error with const attribute ?!
#define const
// BEGIN original hexpru --array output
const uint32_t pru0_image_0[] = {
0x240000c0,
0x24010080,
0x0504e0e2,
0x2eff818e,
0x230007c3,
0x240001ee,
0x230013c3,
0x0502e2e2,
0x91042480,
0xe10002c3,
0x1d04e0e0,
0x81042480,
0x230010c3,
0xf10002c3,
0x0102e2e2,
0x20c30000,
0x2e87018e,
0x10eeeefe,
0x21001000,
0x230015c3,
0x21001400,
0x10000000,
0x20c30000};
const uint8_t pru0_image_1[] = {
0x01,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00};
// END original hexpru --array output
// sizeof() for code image
unsigned pru0_sizeof_code(void) {
return sizeof(pru0_image_0) ;
}
// under c++ linker error with const attribute ?!

35
10.01_base/4_deploy/pru0_config.h
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@@ -1,35 +0,0 @@
/*** Following code generated by "/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/update_pru_config.sh 0 pru0_array.c /home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_config /home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0.map" ***/
#ifndef _PRU0_CONFIG_H_
#define _PRU0_CONFIG_H_
#include <stdint.h>
#ifndef _PRU0_CONFIG_C_
// extern const uint32_t pru0_image_0[] ;
extern uint32_t pru0_image_0[] ;
#endif
unsigned pru0_sizeof_code(void) ;
// code entry point "_c_int00_noinit_noargs" from linker map file:
#define PRU0_ENTRY_ADDR 0x00000000
// Mailbox page & offset in PRU internal shared 12 KB RAM
// Accessible by both PRUs, must be located in shared RAM
// offset 0 == addr 0x10000 in linker cmd files for PRU0 AND PRU1 projects.
// For use with prussdrv_map_prumem()
#ifndef PRU_MAILBOX_RAM_ID
#define PRU_MAILBOX_RAM_ID PRUSS0_SHARED_DATARAM
#define PRU_MAILBOX_RAM_OFFSET 0
#endif
// Device register page & offset in PRU0 8KB RAM mapped into PRU1 space
// offset 0 == addr 0x2000 in linker cmd files for PRU1 projects.
// For use with prussdrv_map_prumem()
#ifndef PRU_DEVICEREGISTER_RAM_ID
#define PRU_DEVICEREGISTER_RAM_ID PRUSS0_PRU0_DATARAM
#define PRU_DEVICEREGISTER_RAM_OFFSET 0
#endif
#endif

BIN
10.01_base/4_deploy/pru0_datout.asmobject
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54
10.01_base/4_deploy/pru0_datout.lst
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@@ -1,54 +0,0 @@
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:28 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru0_datout.asmsrc PAGE 1
1;
2; pru0_datout.asmsrc: PRU0 loop to copy XFR to GPIO out
3;
4; Copyright (c) 2018, Joerg Hoppe
5; j_hoppe@t-online.de, www.retrocmp.com
6;
7; Permission is hereby granted, free of charge, to any person obtaining a
8; copy of this software and associated documentation files (the "Software"),
9; to deal in the Software without restriction, including without limitation
10; the rights to use, copy, modify, merge, publish, distribute, sublicense,
11; and/or sell copies of the Software, and to permit persons to whom the
12; Software is furnished to do so, subject to the following conditions:
13;
14; The above copyright notice and this permission notice shall be included in
15; all copies or substantial portions of the Software.
16;
17; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20; JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21; IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22; CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23;
24;
25; 12-nov-2018 JH entered beta phase
26;
27;
28; Assembler function, which endlessly reads r14 from XFR area
29; and copies to output pins DATOUT
30; needs 15ns to loop
31;
32; to be declared in C as
33; extern "C" {
34; void pru0_dataout(void) ;
35; }
36; See Compiler 2.2 Guide, Chapter 6.6
37
38 .global pru0_dataout
39
40 ; a 32bit parameter is received in r14
41 ; 10 ns delay
42 00000000 pru0_dataout:
43 ; do nothing at first
44 ; Device ID 14 = "other PRU"
45 00000000 0000002E87018E xin 14,&r14,4
46 00000004 00000010EEEEFE mov r30,r14
47 00000008 00000021000000! jmp pru0_dataout ; never returns
No Assembly Errors, No Assembly Warnings

2528
10.01_base/4_deploy/pru0_main.asm
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2760
10.01_base/4_deploy/pru0_main.lst
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BIN
10.01_base/4_deploy/pru0_main.object
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9
10.01_base/4_deploy/pru0_main.pp
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@@ -1,9 +0,0 @@
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: pru0_main.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_cfg.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: resource_table_empty.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stddef.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/rsc_types.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/pru_types.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_main.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h

147
10.01_base/4_deploy/pru0_pru_mailbox.asm
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@@ -1,147 +0,0 @@
;******************************************************************************
;* PRU C/C++ Codegen Unix v2.3.1 *
;* Date/Time created: Sun Mar 31 20:55:28 2019 *
;******************************************************************************
.compiler_opts --abi=eabi --endian=little --hll_source=on --object_format=elf --silicon_version=3 --symdebug:dwarf --symdebug:dwarf_version=3
$C$DW$CU .dwtag DW_TAG_compile_unit
.dwattr $C$DW$CU, DW_AT_name("pru0_pru_mailbox.c")
.dwattr $C$DW$CU, DW_AT_producer("TI PRU C/C++ Codegen Unix v2.3.1 Copyright (c) 2012-2017 Texas Instruments Incorporated")
.dwattr $C$DW$CU, DW_AT_TI_version(0x01)
.dwattr $C$DW$CU, DW_AT_comp_dir("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/pru0")
.global ||pru_pru_mailbox||
||pru_pru_mailbox||: .usect ".pru_pru_mailbox_sec",4,1
$C$DW$1 .dwtag DW_TAG_variable
.dwattr $C$DW$1, DW_AT_name("pru_pru_mailbox")
.dwattr $C$DW$1, DW_AT_TI_symbol_name("pru_pru_mailbox")
.dwattr $C$DW$1, DW_AT_location[DW_OP_addr ||pru_pru_mailbox||]
.dwattr $C$DW$1, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$1, DW_AT_external
.dwattr $C$DW$1, DW_AT_decl_file("pru0_pru_mailbox.c")
.dwattr $C$DW$1, DW_AT_decl_line(0x2d)
.dwattr $C$DW$1, DW_AT_decl_column(0x1c)
; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/optpru /tmp/TI1ibOMhU80 /tmp/TI1ibqMS7YA
; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/acpiapru -@/tmp/TI1ib4bvnr7
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
$C$DW$T$20 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$20, DW_AT_byte_size(0x04)
$C$DW$2 .dwtag DW_TAG_member
.dwattr $C$DW$2, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$2, DW_AT_name("xxx_pru0_r30")
.dwattr $C$DW$2, DW_AT_TI_symbol_name("xxx_pru0_r30")
.dwattr $C$DW$2, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$2, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$2, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h")
.dwattr $C$DW$2, DW_AT_decl_line(0x24)
.dwattr $C$DW$2, DW_AT_decl_column(0x0b)
.dwattr $C$DW$T$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h")
.dwattr $C$DW$T$20, DW_AT_decl_line(0x20)
.dwattr $C$DW$T$20, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$20
$C$DW$T$21 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$21, DW_AT_name("pru_pru_mailbox_t")
.dwattr $C$DW$T$21, DW_AT_type(*$C$DW$T$20)
.dwattr $C$DW$T$21, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h")
.dwattr $C$DW$T$21, DW_AT_decl_line(0x26)
.dwattr $C$DW$T$21, DW_AT_decl_column(0x03)
$C$DW$T$22 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$21)
$C$DW$T$2 .dwtag DW_TAG_unspecified_type
.dwattr $C$DW$T$2, DW_AT_name("void")
$C$DW$T$4 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
.dwattr $C$DW$T$4, DW_AT_name("bool")
.dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
$C$DW$T$5 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$5, DW_AT_name("signed char")
.dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
$C$DW$T$6 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
.dwattr $C$DW$T$6, DW_AT_name("unsigned char")
.dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
$C$DW$T$7 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$7, DW_AT_name("wchar_t")
.dwattr $C$DW$T$7, DW_AT_byte_size(0x04)
$C$DW$T$8 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$8, DW_AT_name("short")
.dwattr $C$DW$T$8, DW_AT_byte_size(0x02)
$C$DW$T$9 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$9, DW_AT_name("unsigned short")
.dwattr $C$DW$T$9, DW_AT_byte_size(0x02)
$C$DW$T$10 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$10, DW_AT_name("int")
.dwattr $C$DW$T$10, DW_AT_byte_size(0x04)
$C$DW$T$11 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$11, DW_AT_name("unsigned int")
.dwattr $C$DW$T$11, DW_AT_byte_size(0x04)
$C$DW$T$19 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$19, DW_AT_name("uint32_t")
.dwattr $C$DW$T$19, DW_AT_type(*$C$DW$T$11)
.dwattr $C$DW$T$19, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h")
.dwattr $C$DW$T$19, DW_AT_decl_line(0x41)
.dwattr $C$DW$T$19, DW_AT_decl_column(0x1c)
$C$DW$T$12 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$12, DW_AT_name("long")
.dwattr $C$DW$T$12, DW_AT_byte_size(0x04)
$C$DW$T$13 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$13, DW_AT_name("unsigned long")
.dwattr $C$DW$T$13, DW_AT_byte_size(0x04)
$C$DW$T$14 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$14, DW_AT_name("long long")
.dwattr $C$DW$T$14, DW_AT_byte_size(0x08)
$C$DW$T$15 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
.dwattr $C$DW$T$15, DW_AT_byte_size(0x08)
$C$DW$T$16 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$16, DW_AT_name("float")
.dwattr $C$DW$T$16, DW_AT_byte_size(0x04)
$C$DW$T$17 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$17, DW_AT_name("double")
.dwattr $C$DW$T$17, DW_AT_byte_size(0x08)
$C$DW$T$18 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$18, DW_AT_name("long double")
.dwattr $C$DW$T$18, DW_AT_byte_size(0x08)
.dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
.dwendtag $C$DW$CU

164
10.01_base/4_deploy/pru0_pru_mailbox.lst
View File

@@ -1,164 +0,0 @@
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:28 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru0_pru_mailbox.asm PAGE 1
1;******************************************************************************
2;* PRU C/C++ Codegen Unix v2.3.1 *
3;* Date/Time created: Sun Mar 31 20:55:28 2019 *
4;******************************************************************************
5 .compiler_opts --abi=eabi --endian=little --hll_source=on --object_format=elf --silicon_versio
6
7$C$DW$CU .dwtag DW_TAG_compile_unit
8 .dwattr $C$DW$CU, DW_AT_name("pru0_pru_mailbox.c")
9 .dwattr $C$DW$CU, DW_AT_producer("TI PRU C/C++ Codegen Unix v2.3.1 Copyright (c) 2012-2017 Tex
10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01)
11 .dwattr $C$DW$CU, DW_AT_comp_dir("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/pru0")
12 .global ||pru_pru_mailbox||
13 00000000 ||pru_pru_mailbox||: .usect ".pru_pru_mailbox_sec",4,1
14$C$DW$1 .dwtag DW_TAG_variable
15 .dwattr $C$DW$1, DW_AT_name("pru_pru_mailbox")
16 .dwattr $C$DW$1, DW_AT_TI_symbol_name("pru_pru_mailbox")
17 .dwattr $C$DW$1, DW_AT_location[DW_OP_addr ||pru_pru_mailbox||]
18 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$22)
19 .dwattr $C$DW$1, DW_AT_external
20 .dwattr $C$DW$1, DW_AT_decl_file("pru0_pru_mailbox.c")
21 .dwattr $C$DW$1, DW_AT_decl_line(0x2d)
22 .dwattr $C$DW$1, DW_AT_decl_column(0x1c)
23
24; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/optpru /tmp/
25; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/acpiapru -@/
26
27;******************************************************************************
28;* TYPE INFORMATION *
29;******************************************************************************
30
31$C$DW$T$20 .dwtag DW_TAG_structure_type
32 .dwattr $C$DW$T$20, DW_AT_byte_size(0x04)
33$C$DW$2 .dwtag DW_TAG_member
34 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$19)
35 .dwattr $C$DW$2, DW_AT_name("xxx_pru0_r30")
36 .dwattr $C$DW$2, DW_AT_TI_symbol_name("xxx_pru0_r30")
37 .dwattr $C$DW$2, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
38 .dwattr $C$DW$2, DW_AT_accessibility(DW_ACCESS_public)
39 .dwattr $C$DW$2, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru
40 .dwattr $C$DW$2, DW_AT_decl_line(0x24)
41 .dwattr $C$DW$2, DW_AT_decl_column(0x0b)
42
43 .dwattr $C$DW$T$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
44 .dwattr $C$DW$T$20, DW_AT_decl_line(0x20)
45 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10)
46 .dwendtag $C$DW$T$20
47
48$C$DW$T$21 .dwtag DW_TAG_typedef
49 .dwattr $C$DW$T$21, DW_AT_name("pru_pru_mailbox_t")
50 .dwattr $C$DW$T$21, DW_AT_type(*$C$DW$T$20)
51 .dwattr $C$DW$T$21, DW_AT_language(DW_LANG_C)
52 .dwattr $C$DW$T$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
53 .dwattr $C$DW$T$21, DW_AT_decl_line(0x26)
54 .dwattr $C$DW$T$21, DW_AT_decl_column(0x03)
55
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:28 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru0_pru_mailbox.asm PAGE 2
56$C$DW$T$22 .dwtag DW_TAG_volatile_type
57 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$21)
58
59$C$DW$T$2 .dwtag DW_TAG_unspecified_type
60 .dwattr $C$DW$T$2, DW_AT_name("void")
61
62$C$DW$T$4 .dwtag DW_TAG_base_type
63 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
64 .dwattr $C$DW$T$4, DW_AT_name("bool")
65 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
66
67$C$DW$T$5 .dwtag DW_TAG_base_type
68 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
69 .dwattr $C$DW$T$5, DW_AT_name("signed char")
70 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
71
72$C$DW$T$6 .dwtag DW_TAG_base_type
73 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
74 .dwattr $C$DW$T$6, DW_AT_name("unsigned char")
75 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
76
77$C$DW$T$7 .dwtag DW_TAG_base_type
78 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
79 .dwattr $C$DW$T$7, DW_AT_name("wchar_t")
80 .dwattr $C$DW$T$7, DW_AT_byte_size(0x04)
81
82$C$DW$T$8 .dwtag DW_TAG_base_type
83 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
84 .dwattr $C$DW$T$8, DW_AT_name("short")
85 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02)
86
87$C$DW$T$9 .dwtag DW_TAG_base_type
88 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
89 .dwattr $C$DW$T$9, DW_AT_name("unsigned short")
90 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02)
91
92$C$DW$T$10 .dwtag DW_TAG_base_type
93 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
94 .dwattr $C$DW$T$10, DW_AT_name("int")
95 .dwattr $C$DW$T$10, DW_AT_byte_size(0x04)
96
97$C$DW$T$11 .dwtag DW_TAG_base_type
98 .dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
99 .dwattr $C$DW$T$11, DW_AT_name("unsigned int")
100 .dwattr $C$DW$T$11, DW_AT_byte_size(0x04)
101
102$C$DW$T$19 .dwtag DW_TAG_typedef
103 .dwattr $C$DW$T$19, DW_AT_name("uint32_t")
104 .dwattr $C$DW$T$19, DW_AT_type(*$C$DW$T$11)
105 .dwattr $C$DW$T$19, DW_AT_language(DW_LANG_C)
106 .dwattr $C$DW$T$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compi
107 .dwattr $C$DW$T$19, DW_AT_decl_line(0x41)
108 .dwattr $C$DW$T$19, DW_AT_decl_column(0x1c)
109
110$C$DW$T$12 .dwtag DW_TAG_base_type
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:28 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru0_pru_mailbox.asm PAGE 3
111 .dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
112 .dwattr $C$DW$T$12, DW_AT_name("long")
113 .dwattr $C$DW$T$12, DW_AT_byte_size(0x04)
114
115$C$DW$T$13 .dwtag DW_TAG_base_type
116 .dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
117 .dwattr $C$DW$T$13, DW_AT_name("unsigned long")
118 .dwattr $C$DW$T$13, DW_AT_byte_size(0x04)
119
120$C$DW$T$14 .dwtag DW_TAG_base_type
121 .dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
122 .dwattr $C$DW$T$14, DW_AT_name("long long")
123 .dwattr $C$DW$T$14, DW_AT_byte_size(0x08)
124
125$C$DW$T$15 .dwtag DW_TAG_base_type
126 .dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
127 .dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
128 .dwattr $C$DW$T$15, DW_AT_byte_size(0x08)
129
130$C$DW$T$16 .dwtag DW_TAG_base_type
131 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
132 .dwattr $C$DW$T$16, DW_AT_name("float")
133 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04)
134
135$C$DW$T$17 .dwtag DW_TAG_base_type
136 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
137 .dwattr $C$DW$T$17, DW_AT_name("double")
138 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08)
139
140$C$DW$T$18 .dwtag DW_TAG_base_type
141 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
142 .dwattr $C$DW$T$18, DW_AT_name("long double")
143 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08)
144
145 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
146 .dwendtag $C$DW$CU
147
No Assembly Errors, No Assembly Warnings

BIN
10.01_base/4_deploy/pru0_pru_mailbox.object
View File

Binary file not shown.

4
10.01_base/4_deploy/pru0_pru_mailbox.pp
View File

@@ -1,4 +0,0 @@
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_pru_mailbox.object: pru0_pru_mailbox.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_pru_mailbox.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_pru_mailbox.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru0_pru_mailbox.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h

407
10.01_base/4_deploy/pru1.map
View File

@@ -1,407 +0,0 @@
******************************************************************************
PRU Linker Unix v2.3.1
******************************************************************************
>> Linked Sun Mar 31 20:55:40 2019
OUTPUT FILE NAME: </home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1.out>
ENTRY POINT SYMBOL: "_c_int00_noinit_noargs" address: 00000000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
PRU_IMEM 00000000 00002000 00002000 00000000 RWIX
PAGE 1:
PRU_DMEM_0_1 00000000 00002000 0000013c 00001ec4 RWIX
PRU_DMEM_1_0 00002000 00002000 00001820 000007e0 RWIX
PAGE 2:
PRU_SHAREDMEM 00010000 00003000 00000424 00002bdc RWIX
PRU_INTC 00020000 00001504 00000000 00001504 RWIX
PRU_CFG 00026000 00000044 00000044 00000000 RWIX
PRU_UART 00028000 00000038 00000000 00000038 RWIX
PRU_IEP 0002e000 0000031c 00000000 0000031c RWIX
PRU_ECAP 00030000 00000060 00000000 00000060 RWIX
RSVD27 00032000 00000100 00000000 00000100 RWIX
RSVD21 00032400 00000100 00000000 00000100 RWIX
L3OCMC 40000000 00010000 00000000 00010000 RWIX
MCASP0_DMA 46000000 00000100 00000000 00000100 RWIX
UART1 48022000 00000088 00000000 00000088 RWIX
UART2 48024000 00000088 00000000 00000088 RWIX
I2C1 4802a000 000000d8 00000000 000000d8 RWIX
MCSPI0 48030000 000001a4 00000000 000001a4 RWIX
DMTIMER2 48040000 0000005c 00000000 0000005c RWIX
MMCHS0 48060000 00000300 00000000 00000300 RWIX
MBX0 480c8000 00000140 00000000 00000140 RWIX
SPINLOCK 480ca000 00000880 00000000 00000880 RWIX
I2C2 4819c000 000000d8 00000000 000000d8 RWIX
MCSPI1 481a0000 000001a4 00000000 000001a4 RWIX
DCAN0 481cc000 000001e8 00000000 000001e8 RWIX
DCAN1 481d0000 000001e8 00000000 000001e8 RWIX
PWMSS0 48300000 000002c4 00000000 000002c4 RWIX
PWMSS1 48302000 000002c4 00000000 000002c4 RWIX
PWMSS2 48304000 000002c4 00000000 000002c4 RWIX
RSVD13 48310000 00000100 00000000 00000100 RWIX
RSVD10 48318000 00000100 00000000 00000100 RWIX
TPCC 49000000 00001098 00000000 00001098 RWIX
GEMAC 4a100000 0000128c 00000000 0000128c RWIX
DDR 80000000 00000100 00000000 00000100 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.text:_c_int00*
* 0 00000000 0000001c
00000000 0000001c rtspruv3_le.lib : boot.c.obj (.text:_c_int00_noinit_noargs)
.text 0 0000001c 00001fe4
0000001c 0000050c pru1_statemachine_dma.object (.text:sm_dma_state_1)
00000528 00000370 pru1_main.object (.text:main)
00000898 00000250 pru1_statemachine_slave.object (.text:sm_slave_state_1)
00000ae8 000001c8 pru1_statemachine_dma.object (.text:sm_dma_state_99)
00000cb0 0000015c pru1_statemachine_arbitration.object (.text:sm_arb_state_2)
00000e0c 00000130 pru1_buslatches.object (.text:buslatches_reset)
00000f3c 00000120 pru1_iopageregisters.object (.text:iopageregisters_write_b)
0000105c 0000011c pru1_statemachine_arbitration.object (.text:sm_arb_state_3)
00001178 00000100 pru1_buslatches.object (.text:buslatches_powercycle)
00001278 000000f4 pru1_statemachine_dma.object (.text:sm_dma_state_11)
0000136c 000000e8 pru1_iopageregisters.object (.text:iopageregisters_write_w)
00001454 000000e8 pru1_statemachine_dma.object (.text:sm_dma_state_21)
0000153c 000000e8 pru1_statemachine_intr.object (.text:sm_intr_state_2)
00001624 000000d8 pru1_statemachine_intr.object (.text:sm_intr_state_1)
000016fc 000000d4 pru1_iopageregisters.object (.text:iopageregisters_read)
000017d0 000000d4 pru1_statemachine_arbitration.object (.text:sm_arb_state_1)
000018a4 000000c4 pru1_statemachine_slave.object (.text:sm_slave_state_20)
00001968 000000ac pru1_statemachine_powercycle.object (.text:sm_powercycle_state_2)
00001a14 000000ac pru1_statemachine_powercycle.object (.text:sm_powercycle_state_3)
00001ac0 000000a8 pru1_statemachine_init.object (.text:sm_init_start)
00001b68 00000098 pru1_statemachine_powercycle.object (.text:sm_powercycle_state_1)
00001c00 0000008c pru1_statemachine_slave.object (.text:sm_slave_state_10)
00001c8c 00000080 pru1_statemachine_init.object (.text:sm_init_state_1)
00001d0c 00000080 pru1_statemachine_powercycle.object (.text:sm_powercycle_state_4)
00001d8c 00000074 pru1_statemachine_arbitration.object (.text:sm_arb_state_idle)
00001e00 00000060 pru1_statemachine_init.object (.text:do_event_initializationsignals)
00001e60 00000060 pru1_iopageregisters.object (.text:iopageregisters_init)
00001ec0 00000038 pru1_statemachine_dma.object (.text:sm_dma_start)
00001ef8 00000034 pru1_statemachine_slave.object (.text:sm_slave_state_99)
00001f2c 0000002c pru1_buslatches.object (.text:buslatches_test)
00001f58 0000002c pru1_ddrmem.object (.text:ddrmem_fill_pattern)
00001f84 00000014 pru1_statemachine_arbitration.object (.text:sm_arb_start)
00001f98 00000010 pru1_statemachine_intr.object (.text:sm_intr_start)
00001fa8 00000010 pru1_statemachine_powercycle.object (.text:sm_powercycle_start)
00001fb8 00000010 pru1_statemachine_slave.object (.text:sm_slave_start)
00001fc8 00000008 rtspruv3_le.lib : exit.c.obj (.text:abort)
00001fd0 00000008 : exit.c.obj (.text:loader_exit)
00001fd8 00000008 pru1_buslatches_pru0_datout.asmobject (.text)
00001fe0 00000008 pru1_statemachine_arbitration.object (.text:sm_arb_state_4)
00001fe8 00000008 pru1_statemachine_init.object (.text:sm_init_state_idle)
00001ff0 00000008 pru1_statemachine_intr.object (.text:sm_intr_state_idle)
00001ff8 00000008 pru1_statemachine_powercycle.object (.text:sm_powercycle_state_idle)
.stack 1 00000000 00000100 UNINITIALIZED
00000000 00000004 rtspruv3_le.lib : boot.c.obj (.stack)
00000004 000000fc --HOLE--
.bss 1 00000100 00000028 UNINITIALIZED
00000100 00000010 (.common:buslatches)
00000110 00000009 (.common:sm_dma)
00000119 00000004 (.common:timeout_target)
0000011d 00000003 (.common:sm_arb)
00000120 00000002 (.common:sm_init)
00000122 00000002 (.common:sm_intr)
00000124 00000002 (.common:sm_powercycle)
00000126 00000002 (.common:sm_slave)
.cinit 1 00000000 00000000 UNINITIALIZED
.resource_table
* 1 00000128 00000014
00000128 00000014 pru1_main.object (.resource_table:retain)
.deviceregisters_sec
* 1 00002000 00001820 UNINITIALIZED
00002000 00001820 pru1_iopageregisters.object (.deviceregisters_sec)
.mailbox_arm_sec
* 2 00010000 00000424 UNINITIALIZED
00010000 00000424 pru1_arm_mailbox.object (.mailbox_arm_sec)
.creg.PRU_CFG.noload.near
* 2 00026000 00000044 NOLOAD SECTION
00026000 00000044 pru1_buslatches.object (.creg.PRU_CFG.noload.near)
.creg.PRU_CFG.near
* 2 00026044 00000000 UNINITIALIZED
.creg.PRU_CFG.noload.far
* 2 00026044 00000000 NOLOAD SECTION
.creg.PRU_CFG.far
* 2 00026044 00000000 UNINITIALIZED
MODULE SUMMARY
Module code ro data rw data
------ ---- ------- -------
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/
pru1_iopageregisters.object 828 0 6176
pru1_statemachine_dma.object 2280 0 9
pru1_arm_mailbox.object 0 0 1060
pru1_statemachine_slave.object 996 0 2
pru1_statemachine_arbitration.object 988 0 3
pru1_main.object 880 0 20
pru1_buslatches.object 604 0 84
pru1_statemachine_powercycle.object 648 0 2
pru1_statemachine_intr.object 472 0 2
pru1_statemachine_init.object 400 0 2
pru1_ddrmem.object 44 0 0
pru1_buslatches_pru0_datout.asmobject 8 0 0
pru1_utils.object 0 0 4
+--+---------------------------------------+------+---------+---------+
Total: 8148 0 7364
/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//lib/rtspruv3_le.lib
boot.c.obj 28 0 0
exit.c.obj 16 0 0
+--+---------------------------------------+------+---------+---------+
Total: 44 0 0
Stack: 0 0 256
+--+---------------------------------------+------+---------+---------+
Grand Total: 8192 0 7620
SEGMENT ATTRIBUTES
id tag seg value
-- --- --- -----
0 PHA_PAGE 1 1
1 PHA_PAGE 2 1
2 PHA_PAGE 3 1
3 PHA_PAGE 4 2
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
page address name
---- ------- ----
0 00001fd0 C$$EXIT
2 00026000 CT_CFG
abs 481cc000 __PRU_CREG_BASE_DCAN0
abs 481d0000 __PRU_CREG_BASE_DCAN1
abs 80000000 __PRU_CREG_BASE_DDR
abs 48040000 __PRU_CREG_BASE_DMTIMER2
abs 4a100000 __PRU_CREG_BASE_GEMAC
abs 4802a000 __PRU_CREG_BASE_I2C1
abs 4819c000 __PRU_CREG_BASE_I2C2
abs 40000000 __PRU_CREG_BASE_L3OCMC
abs 480c8000 __PRU_CREG_BASE_MBX0
abs 46000000 __PRU_CREG_BASE_MCASP0_DMA
abs 48030000 __PRU_CREG_BASE_MCSPI0
abs 481a0000 __PRU_CREG_BASE_MCSPI1
abs 48060000 __PRU_CREG_BASE_MMCHS0
abs 00026000 __PRU_CREG_BASE_PRU_CFG
abs 00000000 __PRU_CREG_BASE_PRU_DMEM_0_1
abs 00002000 __PRU_CREG_BASE_PRU_DMEM_1_0
abs 00030000 __PRU_CREG_BASE_PRU_ECAP
abs 0002e000 __PRU_CREG_BASE_PRU_IEP
abs 00020000 __PRU_CREG_BASE_PRU_INTC
abs 00010000 __PRU_CREG_BASE_PRU_SHAREDMEM
abs 00028000 __PRU_CREG_BASE_PRU_UART
abs 48300000 __PRU_CREG_BASE_PWMSS0
abs 48302000 __PRU_CREG_BASE_PWMSS1
abs 48304000 __PRU_CREG_BASE_PWMSS2
abs 48318000 __PRU_CREG_BASE_RSVD10
abs 48310000 __PRU_CREG_BASE_RSVD13
abs 00032400 __PRU_CREG_BASE_RSVD21
abs 00032000 __PRU_CREG_BASE_RSVD27
abs 480ca000 __PRU_CREG_BASE_SPINLOCK
abs 49000000 __PRU_CREG_BASE_TPCC
abs 48022000 __PRU_CREG_BASE_UART1
abs 48024000 __PRU_CREG_BASE_UART2
abs 0000000e __PRU_CREG_DCAN0
abs 0000000f __PRU_CREG_DCAN1
abs 0000001f __PRU_CREG_DDR
abs 00000001 __PRU_CREG_DMTIMER2
abs 00000009 __PRU_CREG_GEMAC
abs 00000002 __PRU_CREG_I2C1
abs 00000011 __PRU_CREG_I2C2
abs 0000001e __PRU_CREG_L3OCMC
abs 00000016 __PRU_CREG_MBX0
abs 00000008 __PRU_CREG_MCASP0_DMA
abs 00000006 __PRU_CREG_MCSPI0
abs 00000010 __PRU_CREG_MCSPI1
abs 00000005 __PRU_CREG_MMCHS0
abs 00000004 __PRU_CREG_PRU_CFG
abs 00000018 __PRU_CREG_PRU_DMEM_0_1
abs 00000019 __PRU_CREG_PRU_DMEM_1_0
abs 00000003 __PRU_CREG_PRU_ECAP
abs 0000001a __PRU_CREG_PRU_IEP
abs 00000000 __PRU_CREG_PRU_INTC
abs 0000001c __PRU_CREG_PRU_SHAREDMEM
abs 00000007 __PRU_CREG_PRU_UART
abs 00000012 __PRU_CREG_PWMSS0
abs 00000013 __PRU_CREG_PWMSS1
abs 00000014 __PRU_CREG_PWMSS2
abs 0000000a __PRU_CREG_RSVD10
abs 0000000d __PRU_CREG_RSVD13
abs 00000015 __PRU_CREG_RSVD21
abs 0000001b __PRU_CREG_RSVD27
abs 00000017 __PRU_CREG_SPINLOCK
abs 0000001d __PRU_CREG_TPCC
abs 0000000b __PRU_CREG_UART1
abs 0000000c __PRU_CREG_UART2
1 00000100 __TI_STACK_END
abs 00000100 __TI_STACK_SIZE
abs ffffffff __c_args__
0 00000000 _c_int00_noinit_noargs
1 00000000 _stack
0 00001fc8 abort
1 00000100 buslatches
0 00001178 buslatches_powercycle
0 00001fd8 buslatches_pru0_dataout
0 00000e0c buslatches_reset
0 00001f2c buslatches_test
0 00001f58 ddrmem_fill_pattern
1 00002000 deviceregisters
0 00001e00 do_event_initializationsignals
0 00001e60 iopageregisters_init
0 000016fc iopageregisters_read
0 00000f3c iopageregisters_write_b
0 0000136c iopageregisters_write_w
2 00010000 mailbox
0 00000528 main
1 00000128 pru_remoteproc_ResourceTable
1 0000011d sm_arb
0 00001f84 sm_arb_start
0 00001d8c sm_arb_state_idle
1 00000110 sm_dma
0 00001ec0 sm_dma_start
1 00000120 sm_init
0 00001ac0 sm_init_start
0 00001fe8 sm_init_state_idle
1 00000122 sm_intr
0 00001f98 sm_intr_start
1 00000124 sm_powercycle
0 00001fa8 sm_powercycle_start
0 00001ff8 sm_powercycle_state_idle
1 00000126 sm_slave
0 00001fb8 sm_slave_start
1 00000119 timeout_target
GLOBAL SYMBOLS: SORTED BY Symbol Address
page address name
---- ------- ----
0 00000000 _c_int00_noinit_noargs
0 00000528 main
0 00000e0c buslatches_reset
0 00000f3c iopageregisters_write_b
0 00001178 buslatches_powercycle
0 0000136c iopageregisters_write_w
0 000016fc iopageregisters_read
0 00001ac0 sm_init_start
0 00001d8c sm_arb_state_idle
0 00001e00 do_event_initializationsignals
0 00001e60 iopageregisters_init
0 00001ec0 sm_dma_start
0 00001f2c buslatches_test
0 00001f58 ddrmem_fill_pattern
0 00001f84 sm_arb_start
0 00001f98 sm_intr_start
0 00001fa8 sm_powercycle_start
0 00001fb8 sm_slave_start
0 00001fc8 abort
0 00001fd0 C$$EXIT
0 00001fd8 buslatches_pru0_dataout
0 00001fe8 sm_init_state_idle
0 00001ff8 sm_powercycle_state_idle
1 00000000 _stack
1 00000100 __TI_STACK_END
1 00000100 buslatches
1 00000110 sm_dma
1 00000119 timeout_target
1 0000011d sm_arb
1 00000120 sm_init
1 00000122 sm_intr
1 00000124 sm_powercycle
1 00000126 sm_slave
1 00000128 pru_remoteproc_ResourceTable
1 00002000 deviceregisters
2 00010000 mailbox
2 00026000 CT_CFG
abs 00000000 __PRU_CREG_BASE_PRU_DMEM_0_1
abs 00000000 __PRU_CREG_PRU_INTC
abs 00000001 __PRU_CREG_DMTIMER2
abs 00000002 __PRU_CREG_I2C1
abs 00000003 __PRU_CREG_PRU_ECAP
abs 00000004 __PRU_CREG_PRU_CFG
abs 00000005 __PRU_CREG_MMCHS0
abs 00000006 __PRU_CREG_MCSPI0
abs 00000007 __PRU_CREG_PRU_UART
abs 00000008 __PRU_CREG_MCASP0_DMA
abs 00000009 __PRU_CREG_GEMAC
abs 0000000a __PRU_CREG_RSVD10
abs 0000000b __PRU_CREG_UART1
abs 0000000c __PRU_CREG_UART2
abs 0000000d __PRU_CREG_RSVD13
abs 0000000e __PRU_CREG_DCAN0
abs 0000000f __PRU_CREG_DCAN1
abs 00000010 __PRU_CREG_MCSPI1
abs 00000011 __PRU_CREG_I2C2
abs 00000012 __PRU_CREG_PWMSS0
abs 00000013 __PRU_CREG_PWMSS1
abs 00000014 __PRU_CREG_PWMSS2
abs 00000015 __PRU_CREG_RSVD21
abs 00000016 __PRU_CREG_MBX0
abs 00000017 __PRU_CREG_SPINLOCK
abs 00000018 __PRU_CREG_PRU_DMEM_0_1
abs 00000019 __PRU_CREG_PRU_DMEM_1_0
abs 0000001a __PRU_CREG_PRU_IEP
abs 0000001b __PRU_CREG_RSVD27
abs 0000001c __PRU_CREG_PRU_SHAREDMEM
abs 0000001d __PRU_CREG_TPCC
abs 0000001e __PRU_CREG_L3OCMC
abs 0000001f __PRU_CREG_DDR
abs 00000100 __TI_STACK_SIZE
abs 00002000 __PRU_CREG_BASE_PRU_DMEM_1_0
abs 00010000 __PRU_CREG_BASE_PRU_SHAREDMEM
abs 00020000 __PRU_CREG_BASE_PRU_INTC
abs 00026000 __PRU_CREG_BASE_PRU_CFG
abs 00028000 __PRU_CREG_BASE_PRU_UART
abs 0002e000 __PRU_CREG_BASE_PRU_IEP
abs 00030000 __PRU_CREG_BASE_PRU_ECAP
abs 00032000 __PRU_CREG_BASE_RSVD27
abs 00032400 __PRU_CREG_BASE_RSVD21
abs 40000000 __PRU_CREG_BASE_L3OCMC
abs 46000000 __PRU_CREG_BASE_MCASP0_DMA
abs 48022000 __PRU_CREG_BASE_UART1
abs 48024000 __PRU_CREG_BASE_UART2
abs 4802a000 __PRU_CREG_BASE_I2C1
abs 48030000 __PRU_CREG_BASE_MCSPI0
abs 48040000 __PRU_CREG_BASE_DMTIMER2
abs 48060000 __PRU_CREG_BASE_MMCHS0
abs 480c8000 __PRU_CREG_BASE_MBX0
abs 480ca000 __PRU_CREG_BASE_SPINLOCK
abs 4819c000 __PRU_CREG_BASE_I2C2
abs 481a0000 __PRU_CREG_BASE_MCSPI1
abs 481cc000 __PRU_CREG_BASE_DCAN0
abs 481d0000 __PRU_CREG_BASE_DCAN1
abs 48300000 __PRU_CREG_BASE_PWMSS0
abs 48302000 __PRU_CREG_BASE_PWMSS1
abs 48304000 __PRU_CREG_BASE_PWMSS2
abs 48310000 __PRU_CREG_BASE_RSVD13
abs 48318000 __PRU_CREG_BASE_RSVD10
abs 49000000 __PRU_CREG_BASE_TPCC
abs 4a100000 __PRU_CREG_BASE_GEMAC
abs 80000000 __PRU_CREG_BASE_DDR
abs ffffffff __c_args__
[103 symbols]

BIN
10.01_base/4_deploy/pru1.out
View File

Binary file not shown.

724
10.01_base/4_deploy/pru1_arm_mailbox.asm
View File

@@ -1,724 +0,0 @@
;******************************************************************************
;* PRU C/C++ Codegen Unix v2.3.1 *
;* Date/Time created: Sun Mar 31 20:55:29 2019 *
;******************************************************************************
.compiler_opts --abi=eabi --endian=little --hll_source=on --object_format=elf --silicon_version=3 --symdebug:dwarf --symdebug:dwarf_version=3
$C$DW$CU .dwtag DW_TAG_compile_unit
.dwattr $C$DW$CU, DW_AT_name("pru1_arm_mailbox.c")
.dwattr $C$DW$CU, DW_AT_producer("TI PRU C/C++ Codegen Unix v2.3.1 Copyright (c) 2012-2017 Texas Instruments Incorporated")
.dwattr $C$DW$CU, DW_AT_TI_version(0x01)
.dwattr $C$DW$CU, DW_AT_comp_dir("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/pru1")
.global ||mailbox||
||mailbox||: .usect ".mailbox_arm_sec",1060,1
$C$DW$1 .dwtag DW_TAG_variable
.dwattr $C$DW$1, DW_AT_name("mailbox")
.dwattr $C$DW$1, DW_AT_TI_symbol_name("mailbox")
.dwattr $C$DW$1, DW_AT_location[DW_OP_addr ||mailbox||]
.dwattr $C$DW$1, DW_AT_type(*$C$DW$T$47)
.dwattr $C$DW$1, DW_AT_external
.dwattr $C$DW$1, DW_AT_decl_file("pru1_arm_mailbox.c")
.dwattr $C$DW$1, DW_AT_decl_line(0x25)
.dwattr $C$DW$1, DW_AT_decl_column(0x18)
; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/optpru --gen_opt_info=2 /tmp/TI1iUvMTKLB /tmp/TI1iUx89pCn --opt_info_filename=/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.nfo
; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/acpiapru -@/tmp/TI1iUn9E65z
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
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$C$DW$2 .dwtag DW_TAG_member
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.dwattr $C$DW$2, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$2, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$2, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h")
.dwattr $C$DW$2, DW_AT_decl_line(0x34)
.dwattr $C$DW$2, DW_AT_decl_column(0x02)
.dwattr $C$DW$T$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h")
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.dwendtag $C$DW$T$19
$C$DW$T$20 .dwtag DW_TAG_typedef
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.dwattr $C$DW$T$20, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h")
.dwattr $C$DW$T$20, DW_AT_decl_line(0x38)
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$C$DW$T$21 .dwtag DW_TAG_structure_type
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$C$DW$3 .dwtag DW_TAG_member
.dwattr $C$DW$3, DW_AT_type(*$C$DW$T$20)
.dwattr $C$DW$3, DW_AT_name("memory")
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.dwattr $C$DW$3, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
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.dwattr $C$DW$T$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h")
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.dwattr $C$DW$T$32, DW_AT_language(DW_LANG_C)
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$C$DW$T$33 .dwtag DW_TAG_volatile_type
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$C$DW$4 .dwtag DW_TAG_member
.dwattr $C$DW$4, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$4, DW_AT_name("eventmask")
.dwattr $C$DW$4, DW_AT_TI_symbol_name("eventmask")
.dwattr $C$DW$4, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
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.dwattr $C$DW$4, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$4, DW_AT_decl_line(0x7a)
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$C$DW$5 .dwtag DW_TAG_member
.dwattr $C$DW$5, DW_AT_type(*$C$DW$T$22)
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.dwattr $C$DW$5, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwattr $C$DW$6, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwattr $C$DW$7, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwattr $C$DW$10, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwattr $C$DW$11, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwattr $C$DW$T$25, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwendtag $C$DW$T$25
$C$DW$T$35 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$35, DW_AT_name("mailbox_events_t")
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.dwattr $C$DW$T$35, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
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.dwattr $C$DW$12, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$12, DW_AT_decl_line(0x4c)
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.dwattr $C$DW$13, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$13, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$13, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$13, DW_AT_decl_line(0x4d)
.dwattr $C$DW$13, DW_AT_decl_column(0x0b)
.dwattr $C$DW$T$26, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$26, DW_AT_decl_line(0x4b)
.dwattr $C$DW$T$26, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$26
$C$DW$T$40 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$40, DW_AT_name("mailbox_test_t")
.dwattr $C$DW$T$40, DW_AT_type(*$C$DW$T$26)
.dwattr $C$DW$T$40, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$40, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$40, DW_AT_decl_line(0x4e)
.dwattr $C$DW$T$40, DW_AT_decl_column(0x03)
$C$DW$T$27 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$27, DW_AT_byte_size(0x0c)
$C$DW$14 .dwtag DW_TAG_member
.dwattr $C$DW$14, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$14, DW_AT_name("addr")
.dwattr $C$DW$14, DW_AT_TI_symbol_name("addr")
.dwattr $C$DW$14, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$14, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$14, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$14, DW_AT_decl_line(0x51)
.dwattr $C$DW$14, DW_AT_decl_column(0x0b)
$C$DW$15 .dwtag DW_TAG_member
.dwattr $C$DW$15, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$15, DW_AT_name("bitmask")
.dwattr $C$DW$15, DW_AT_TI_symbol_name("bitmask")
.dwattr $C$DW$15, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$15, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$15, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$15, DW_AT_decl_line(0x52)
.dwattr $C$DW$15, DW_AT_decl_column(0x0b)
$C$DW$16 .dwtag DW_TAG_member
.dwattr $C$DW$16, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$16, DW_AT_name("val")
.dwattr $C$DW$16, DW_AT_TI_symbol_name("val")
.dwattr $C$DW$16, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
.dwattr $C$DW$16, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$16, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$16, DW_AT_decl_line(0x53)
.dwattr $C$DW$16, DW_AT_decl_column(0x0b)
.dwattr $C$DW$T$27, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$27, DW_AT_decl_line(0x50)
.dwattr $C$DW$T$27, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$27
$C$DW$T$41 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$41, DW_AT_name("mailbox_buslatch_t")
.dwattr $C$DW$T$41, DW_AT_type(*$C$DW$T$27)
.dwattr $C$DW$T$41, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$41, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$41, DW_AT_decl_line(0x54)
.dwattr $C$DW$T$41, DW_AT_decl_column(0x03)
$C$DW$T$28 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$28, DW_AT_byte_size(0x04)
$C$DW$17 .dwtag DW_TAG_member
.dwattr $C$DW$17, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$17, DW_AT_name("addr_0_7")
.dwattr $C$DW$17, DW_AT_TI_symbol_name("addr_0_7")
.dwattr $C$DW$17, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$17, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$17, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$17, DW_AT_decl_line(0x57)
.dwattr $C$DW$17, DW_AT_decl_column(0x0a)
$C$DW$18 .dwtag DW_TAG_member
.dwattr $C$DW$18, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$18, DW_AT_name("addr_8_15")
.dwattr $C$DW$18, DW_AT_TI_symbol_name("addr_8_15")
.dwattr $C$DW$18, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$18, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$18, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$18, DW_AT_decl_line(0x58)
.dwattr $C$DW$18, DW_AT_decl_column(0x0a)
$C$DW$19 .dwtag DW_TAG_member
.dwattr $C$DW$19, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$19, DW_AT_name("data_0_7")
.dwattr $C$DW$19, DW_AT_TI_symbol_name("data_0_7")
.dwattr $C$DW$19, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$19, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$19, DW_AT_decl_line(0x59)
.dwattr $C$DW$19, DW_AT_decl_column(0x0a)
$C$DW$20 .dwtag DW_TAG_member
.dwattr $C$DW$20, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$20, DW_AT_name("data_8_15")
.dwattr $C$DW$20, DW_AT_TI_symbol_name("data_8_15")
.dwattr $C$DW$20, DW_AT_data_member_location[DW_OP_plus_uconst 0x3]
.dwattr $C$DW$20, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$20, DW_AT_decl_line(0x5a)
.dwattr $C$DW$20, DW_AT_decl_column(0x0a)
.dwattr $C$DW$T$28, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$28, DW_AT_decl_line(0x56)
.dwattr $C$DW$T$28, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$28
$C$DW$T$42 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$42, DW_AT_name("mailbox_buslatch_test_t")
.dwattr $C$DW$T$42, DW_AT_type(*$C$DW$T$28)
.dwattr $C$DW$T$42, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$42, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$42, DW_AT_decl_line(0x5b)
.dwattr $C$DW$T$42, DW_AT_decl_column(0x03)
$C$DW$T$30 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$30, DW_AT_byte_size(0x40c)
$C$DW$21 .dwtag DW_TAG_member
.dwattr $C$DW$21, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$21, DW_AT_name("cur_status")
.dwattr $C$DW$21, DW_AT_TI_symbol_name("cur_status")
.dwattr $C$DW$21, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$21, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$21, DW_AT_decl_line(0x61)
.dwattr $C$DW$21, DW_AT_decl_column(0x0a)
$C$DW$22 .dwtag DW_TAG_member
.dwattr $C$DW$22, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$22, DW_AT_name("control")
.dwattr $C$DW$22, DW_AT_TI_symbol_name("control")
.dwattr $C$DW$22, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
.dwattr $C$DW$22, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$22, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$22, DW_AT_decl_line(0x62)
.dwattr $C$DW$22, DW_AT_decl_column(0x0a)
$C$DW$23 .dwtag DW_TAG_member
.dwattr $C$DW$23, DW_AT_type(*$C$DW$T$24)
.dwattr $C$DW$23, DW_AT_name("wordcount")
.dwattr $C$DW$23, DW_AT_TI_symbol_name("wordcount")
.dwattr $C$DW$23, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$23, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$23, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$23, DW_AT_decl_line(0x63)
.dwattr $C$DW$23, DW_AT_decl_column(0x0b)
$C$DW$24 .dwtag DW_TAG_member
.dwattr $C$DW$24, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$24, DW_AT_name("cur_addr")
.dwattr $C$DW$24, DW_AT_TI_symbol_name("cur_addr")
.dwattr $C$DW$24, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$24, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$24, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$24, DW_AT_decl_line(0x64)
.dwattr $C$DW$24, DW_AT_decl_column(0x0b)
$C$DW$25 .dwtag DW_TAG_member
.dwattr $C$DW$25, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$25, DW_AT_name("startaddr")
.dwattr $C$DW$25, DW_AT_TI_symbol_name("startaddr")
.dwattr $C$DW$25, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
.dwattr $C$DW$25, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$25, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$25, DW_AT_decl_line(0x65)
.dwattr $C$DW$25, DW_AT_decl_column(0x0b)
$C$DW$26 .dwtag DW_TAG_member
.dwattr $C$DW$26, DW_AT_type(*$C$DW$T$29)
.dwattr $C$DW$26, DW_AT_name("words")
.dwattr $C$DW$26, DW_AT_TI_symbol_name("words")
.dwattr $C$DW$26, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
.dwattr $C$DW$26, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$26, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$26, DW_AT_decl_line(0x66)
.dwattr $C$DW$26, DW_AT_decl_column(0x0b)
.dwattr $C$DW$T$30, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$30, DW_AT_decl_line(0x5f)
.dwattr $C$DW$T$30, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$30
$C$DW$T$43 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$43, DW_AT_name("mailbox_dma_t")
.dwattr $C$DW$T$43, DW_AT_type(*$C$DW$T$30)
.dwattr $C$DW$T$43, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$43, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$43, DW_AT_decl_line(0x67)
.dwattr $C$DW$T$43, DW_AT_decl_column(0x03)
$C$DW$T$31 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$31, DW_AT_byte_size(0x03)
$C$DW$27 .dwtag DW_TAG_member
.dwattr $C$DW$27, DW_AT_type(*$C$DW$T$24)
.dwattr $C$DW$27, DW_AT_name("vector")
.dwattr $C$DW$27, DW_AT_TI_symbol_name("vector")
.dwattr $C$DW$27, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$27, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$27, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$27, DW_AT_decl_line(0x6b)
.dwattr $C$DW$27, DW_AT_decl_column(0x0b)
$C$DW$28 .dwtag DW_TAG_member
.dwattr $C$DW$28, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$28, DW_AT_name("priority_bit")
.dwattr $C$DW$28, DW_AT_TI_symbol_name("priority_bit")
.dwattr $C$DW$28, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
.dwattr $C$DW$28, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$28, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$28, DW_AT_decl_line(0x6c)
.dwattr $C$DW$28, DW_AT_decl_column(0x0a)
.dwattr $C$DW$T$31, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$31, DW_AT_decl_line(0x6a)
.dwattr $C$DW$T$31, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$31
$C$DW$T$44 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$44, DW_AT_name("mailbox_intr_t")
.dwattr $C$DW$T$44, DW_AT_type(*$C$DW$T$31)
.dwattr $C$DW$T$44, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$44, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$44, DW_AT_decl_line(0x6d)
.dwattr $C$DW$T$44, DW_AT_decl_column(0x03)
$C$DW$T$36 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$36, DW_AT_byte_size(0x424)
$C$DW$29 .dwtag DW_TAG_member
.dwattr $C$DW$29, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$29, DW_AT_name("arm2pru_req")
.dwattr $C$DW$29, DW_AT_TI_symbol_name("arm2pru_req")
.dwattr $C$DW$29, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$29, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$29, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$29, DW_AT_decl_line(0x90)
.dwattr $C$DW$29, DW_AT_decl_column(0x0b)
$C$DW$30 .dwtag DW_TAG_member
.dwattr $C$DW$30, DW_AT_type(*$C$DW$T$23)
.dwattr $C$DW$30, DW_AT_name("arm2pru_resp")
.dwattr $C$DW$30, DW_AT_TI_symbol_name("arm2pru_resp")
.dwattr $C$DW$30, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
.dwattr $C$DW$30, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$30, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$30, DW_AT_decl_line(0x91)
.dwattr $C$DW$30, DW_AT_decl_column(0x0b)
$C$DW$31 .dwtag DW_TAG_member
.dwattr $C$DW$31, DW_AT_type(*$C$DW$T$34)
.dwattr $C$DW$31, DW_AT_name("ddrmem_base_physical")
.dwattr $C$DW$31, DW_AT_TI_symbol_name("ddrmem_base_physical")
.dwattr $C$DW$31, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
.dwattr $C$DW$31, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$31, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$31, DW_AT_decl_line(0x94)
.dwattr $C$DW$31, DW_AT_decl_column(0x15)
$C$DW$32 .dwtag DW_TAG_member
.dwattr $C$DW$32, DW_AT_type(*$C$DW$T$35)
.dwattr $C$DW$32, DW_AT_name("events")
.dwattr $C$DW$32, DW_AT_TI_symbol_name("events")
.dwattr $C$DW$32, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
.dwattr $C$DW$32, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$32, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$32, DW_AT_decl_line(0x97)
.dwattr $C$DW$32, DW_AT_decl_column(0x13)
$C$DW$33 .dwtag DW_TAG_member
.dwattr $C$DW$33, DW_AT_type(*$C$DW$T$45)
.dwattr $C$DW$33, DW_AT_name("$P$T1")
.dwattr $C$DW$33, DW_AT_TI_symbol_name("$P$T1")
.dwattr $C$DW$33, DW_AT_data_member_location[DW_OP_plus_uconst 0x18]
.dwattr $C$DW$33, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$33, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$33, DW_AT_decl_line(0x9a)
.dwattr $C$DW$33, DW_AT_decl_column(0x02)
.dwattr $C$DW$T$36, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$36, DW_AT_decl_line(0x8d)
.dwattr $C$DW$T$36, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$36
$C$DW$T$46 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$46, DW_AT_name("mailbox_t")
.dwattr $C$DW$T$46, DW_AT_type(*$C$DW$T$36)
.dwattr $C$DW$T$46, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$46, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h")
.dwattr $C$DW$T$46, DW_AT_decl_line(0xa1)
.dwattr $C$DW$T$46, DW_AT_decl_column(0x03)
$C$DW$T$47 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$47, DW_AT_type(*$C$DW$T$46)
$C$DW$T$39 .dwtag DW_TAG_union_type
.dwattr $C$DW$T$39, DW_AT_byte_size(0x40000)
$C$DW$34 .dwtag DW_TAG_member
.dwattr $C$DW$34, DW_AT_type(*$C$DW$T$37)
.dwattr $C$DW$34, DW_AT_name("words")
.dwattr $C$DW$34, DW_AT_TI_symbol_name("words")
.dwattr $C$DW$34, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$34, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$34, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h")
.dwattr $C$DW$34, DW_AT_decl_line(0x35)
.dwattr $C$DW$34, DW_AT_decl_column(0x0b)
$C$DW$35 .dwtag DW_TAG_member
.dwattr $C$DW$35, DW_AT_type(*$C$DW$T$38)
.dwattr $C$DW$35, DW_AT_name("bytes")
.dwattr $C$DW$35, DW_AT_TI_symbol_name("bytes")
.dwattr $C$DW$35, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$35, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$35, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h")
.dwattr $C$DW$35, DW_AT_decl_line(0x36)
.dwattr $C$DW$35, DW_AT_decl_column(0x0b)
.dwattr $C$DW$T$39, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h")
.dwattr $C$DW$T$39, DW_AT_decl_line(0x34)
.dwattr $C$DW$T$39, DW_AT_decl_column(0x08)
.dwendtag $C$DW$T$39
$C$DW$T$45 .dwtag DW_TAG_union_type
.dwattr $C$DW$T$45, DW_AT_byte_size(0x40c)
$C$DW$36 .dwtag DW_TAG_member
.dwattr $C$DW$36, DW_AT_type(*$C$DW$T$40)
.dwattr $C$DW$36, DW_AT_name("mailbox_test")
.dwattr $C$DW$36, DW_AT_TI_symbol_name("mailbox_test")
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$C$DW$37 .dwtag DW_TAG_member
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.dwattr $C$DW$40, DW_AT_decl_line(0x9f)
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.dwattr $C$DW$T$45, DW_AT_decl_line(0x9a)
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$C$DW$T$5 .dwtag DW_TAG_base_type
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$C$DW$T$6 .dwtag DW_TAG_base_type
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$C$DW$T$8 .dwtag DW_TAG_base_type
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.dwattr $C$DW$T$24, DW_AT_decl_line(0x3f)
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$C$DW$42 .dwtag DW_TAG_subrange_type
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$C$DW$T$37 .dwtag DW_TAG_array_type
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$C$DW$43 .dwtag DW_TAG_subrange_type
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$C$DW$T$10 .dwtag DW_TAG_base_type
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$C$DW$T$11 .dwtag DW_TAG_base_type
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$C$DW$T$18 .dwtag DW_TAG_base_type
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.dwattr $C$DW$T$18, DW_AT_name("long double")
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.dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
.dwendtag $C$DW$CU

796
10.01_base/4_deploy/pru1_arm_mailbox.lst
View File

@@ -1,796 +0,0 @@
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 1
1;******************************************************************************
2;* PRU C/C++ Codegen Unix v2.3.1 *
3;* Date/Time created: Sun Mar 31 20:55:29 2019 *
4;******************************************************************************
5 .compiler_opts --abi=eabi --endian=little --hll_source=on --object_format=elf --silicon_versio
6
7$C$DW$CU .dwtag DW_TAG_compile_unit
8 .dwattr $C$DW$CU, DW_AT_name("pru1_arm_mailbox.c")
9 .dwattr $C$DW$CU, DW_AT_producer("TI PRU C/C++ Codegen Unix v2.3.1 Copyright (c) 2012-2017 Tex
10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01)
11 .dwattr $C$DW$CU, DW_AT_comp_dir("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/pru1")
12 .global ||mailbox||
13 00000000 ||mailbox||: .usect ".mailbox_arm_sec",1060,1
14$C$DW$1 .dwtag DW_TAG_variable
15 .dwattr $C$DW$1, DW_AT_name("mailbox")
16 .dwattr $C$DW$1, DW_AT_TI_symbol_name("mailbox")
17 .dwattr $C$DW$1, DW_AT_location[DW_OP_addr ||mailbox||]
18 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$47)
19 .dwattr $C$DW$1, DW_AT_external
20 .dwattr $C$DW$1, DW_AT_decl_file("pru1_arm_mailbox.c")
21 .dwattr $C$DW$1, DW_AT_decl_line(0x25)
22 .dwattr $C$DW$1, DW_AT_decl_column(0x18)
23
24; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/optpru --gen
25; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/acpiapru -@/
26
27;******************************************************************************
28;* TYPE INFORMATION *
29;******************************************************************************
30
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32 .dwattr $C$DW$T$19, DW_AT_byte_size(0x40000)
33$C$DW$2 .dwtag DW_TAG_member
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35 .dwattr $C$DW$2, DW_AT_name("$P$T0")
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37 .dwattr $C$DW$2, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
38 .dwattr $C$DW$2, DW_AT_accessibility(DW_ACCESS_public)
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40 .dwattr $C$DW$2, DW_AT_decl_line(0x34)
41 .dwattr $C$DW$2, DW_AT_decl_column(0x02)
42
43 .dwattr $C$DW$T$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
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47
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50 .dwattr $C$DW$T$20, DW_AT_type(*$C$DW$T$19)
51 .dwattr $C$DW$T$20, DW_AT_language(DW_LANG_C)
52 .dwattr $C$DW$T$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
53 .dwattr $C$DW$T$20, DW_AT_decl_line(0x38)
54 .dwattr $C$DW$T$20, DW_AT_decl_column(0x03)
55
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 2
56
57$C$DW$T$21 .dwtag DW_TAG_structure_type
58 .dwattr $C$DW$T$21, DW_AT_byte_size(0x40000)
59$C$DW$3 .dwtag DW_TAG_member
60 .dwattr $C$DW$3, DW_AT_type(*$C$DW$T$20)
61 .dwattr $C$DW$3, DW_AT_name("memory")
62 .dwattr $C$DW$3, DW_AT_TI_symbol_name("memory")
63 .dwattr $C$DW$3, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
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66 .dwattr $C$DW$3, DW_AT_decl_line(0x17)
67 .dwattr $C$DW$3, DW_AT_decl_column(0x12)
68
69 .dwattr $C$DW$T$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
70 .dwattr $C$DW$T$21, DW_AT_decl_line(0x14)
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72 .dwendtag $C$DW$T$21
73
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80 .dwattr $C$DW$T$32, DW_AT_decl_column(0x03)
81
82$C$DW$T$33 .dwtag DW_TAG_volatile_type
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84
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88
89
90$C$DW$T$25 .dwtag DW_TAG_structure_type
91 .dwattr $C$DW$T$25, DW_AT_byte_size(0x0c)
92$C$DW$4 .dwtag DW_TAG_member
93 .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$22)
94 .dwattr $C$DW$4, DW_AT_name("eventmask")
95 .dwattr $C$DW$4, DW_AT_TI_symbol_name("eventmask")
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97 .dwattr $C$DW$4, DW_AT_accessibility(DW_ACCESS_public)
98 .dwattr $C$DW$4, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mai
99 .dwattr $C$DW$4, DW_AT_decl_line(0x7a)
100 .dwattr $C$DW$4, DW_AT_decl_column(0x0a)
101
102$C$DW$5 .dwtag DW_TAG_member
103 .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$22)
104 .dwattr $C$DW$5, DW_AT_name("unibus_control")
105 .dwattr $C$DW$5, DW_AT_TI_symbol_name("unibus_control")
106 .dwattr $C$DW$5, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
107 .dwattr $C$DW$5, DW_AT_accessibility(DW_ACCESS_public)
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109 .dwattr $C$DW$5, DW_AT_decl_line(0x7d)
110 .dwattr $C$DW$5, DW_AT_decl_column(0x0a)
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 3
111
112$C$DW$6 .dwtag DW_TAG_member
113 .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$22)
114 .dwattr $C$DW$6, DW_AT_name("device_handle")
115 .dwattr $C$DW$6, DW_AT_TI_symbol_name("device_handle")
116 .dwattr $C$DW$6, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
117 .dwattr $C$DW$6, DW_AT_accessibility(DW_ACCESS_public)
118 .dwattr $C$DW$6, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mai
119 .dwattr $C$DW$6, DW_AT_decl_line(0x7f)
120 .dwattr $C$DW$6, DW_AT_decl_column(0x0a)
121
122$C$DW$7 .dwtag DW_TAG_member
123 .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$22)
124 .dwattr $C$DW$7, DW_AT_name("device_register_idx")
125 .dwattr $C$DW$7, DW_AT_TI_symbol_name("device_register_idx")
126 .dwattr $C$DW$7, DW_AT_data_member_location[DW_OP_plus_uconst 0x3]
127 .dwattr $C$DW$7, DW_AT_accessibility(DW_ACCESS_public)
128 .dwattr $C$DW$7, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mai
129 .dwattr $C$DW$7, DW_AT_decl_line(0x81)
130 .dwattr $C$DW$7, DW_AT_decl_column(0x0a)
131
132$C$DW$8 .dwtag DW_TAG_member
133 .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$23)
134 .dwattr $C$DW$8, DW_AT_name("addr")
135 .dwattr $C$DW$8, DW_AT_TI_symbol_name("addr")
136 .dwattr $C$DW$8, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
137 .dwattr $C$DW$8, DW_AT_accessibility(DW_ACCESS_public)
138 .dwattr $C$DW$8, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mai
139 .dwattr $C$DW$8, DW_AT_decl_line(0x83)
140 .dwattr $C$DW$8, DW_AT_decl_column(0x0b)
141
142$C$DW$9 .dwtag DW_TAG_member
143 .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$24)
144 .dwattr $C$DW$9, DW_AT_name("data")
145 .dwattr $C$DW$9, DW_AT_TI_symbol_name("data")
146 .dwattr $C$DW$9, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
147 .dwattr $C$DW$9, DW_AT_accessibility(DW_ACCESS_public)
148 .dwattr $C$DW$9, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mai
149 .dwattr $C$DW$9, DW_AT_decl_line(0x84)
150 .dwattr $C$DW$9, DW_AT_decl_column(0x0b)
151
152$C$DW$10 .dwtag DW_TAG_member
153 .dwattr $C$DW$10, DW_AT_type(*$C$DW$T$22)
154 .dwattr $C$DW$10, DW_AT_name("initialization_signals_prev")
155 .dwattr $C$DW$10, DW_AT_TI_symbol_name("initialization_signals_prev")
156 .dwattr $C$DW$10, DW_AT_data_member_location[DW_OP_plus_uconst 0xa]
157 .dwattr $C$DW$10, DW_AT_accessibility(DW_ACCESS_public)
158 .dwattr $C$DW$10, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
159 .dwattr $C$DW$10, DW_AT_decl_line(0x87)
160 .dwattr $C$DW$10, DW_AT_decl_column(0x0a)
161
162$C$DW$11 .dwtag DW_TAG_member
163 .dwattr $C$DW$11, DW_AT_type(*$C$DW$T$22)
164 .dwattr $C$DW$11, DW_AT_name("initialization_signals_cur")
165 .dwattr $C$DW$11, DW_AT_TI_symbol_name("initialization_signals_cur")
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 4
166 .dwattr $C$DW$11, DW_AT_data_member_location[DW_OP_plus_uconst 0xb]
167 .dwattr $C$DW$11, DW_AT_accessibility(DW_ACCESS_public)
168 .dwattr $C$DW$11, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
169 .dwattr $C$DW$11, DW_AT_decl_line(0x88)
170 .dwattr $C$DW$11, DW_AT_decl_column(0x0a)
171
172 .dwattr $C$DW$T$25, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
173 .dwattr $C$DW$T$25, DW_AT_decl_line(0x79)
174 .dwattr $C$DW$T$25, DW_AT_decl_column(0x10)
175 .dwendtag $C$DW$T$25
176
177$C$DW$T$35 .dwtag DW_TAG_typedef
178 .dwattr $C$DW$T$35, DW_AT_name("mailbox_events_t")
179 .dwattr $C$DW$T$35, DW_AT_type(*$C$DW$T$25)
180 .dwattr $C$DW$T$35, DW_AT_language(DW_LANG_C)
181 .dwattr $C$DW$T$35, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
182 .dwattr $C$DW$T$35, DW_AT_decl_line(0x8b)
183 .dwattr $C$DW$T$35, DW_AT_decl_column(0x03)
184
185
186$C$DW$T$26 .dwtag DW_TAG_structure_type
187 .dwattr $C$DW$T$26, DW_AT_byte_size(0x08)
188$C$DW$12 .dwtag DW_TAG_member
189 .dwattr $C$DW$12, DW_AT_type(*$C$DW$T$23)
190 .dwattr $C$DW$12, DW_AT_name("addr")
191 .dwattr $C$DW$12, DW_AT_TI_symbol_name("addr")
192 .dwattr $C$DW$12, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
193 .dwattr $C$DW$12, DW_AT_accessibility(DW_ACCESS_public)
194 .dwattr $C$DW$12, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
195 .dwattr $C$DW$12, DW_AT_decl_line(0x4c)
196 .dwattr $C$DW$12, DW_AT_decl_column(0x0b)
197
198$C$DW$13 .dwtag DW_TAG_member
199 .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$23)
200 .dwattr $C$DW$13, DW_AT_name("val")
201 .dwattr $C$DW$13, DW_AT_TI_symbol_name("val")
202 .dwattr $C$DW$13, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
203 .dwattr $C$DW$13, DW_AT_accessibility(DW_ACCESS_public)
204 .dwattr $C$DW$13, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
205 .dwattr $C$DW$13, DW_AT_decl_line(0x4d)
206 .dwattr $C$DW$13, DW_AT_decl_column(0x0b)
207
208 .dwattr $C$DW$T$26, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
209 .dwattr $C$DW$T$26, DW_AT_decl_line(0x4b)
210 .dwattr $C$DW$T$26, DW_AT_decl_column(0x10)
211 .dwendtag $C$DW$T$26
212
213$C$DW$T$40 .dwtag DW_TAG_typedef
214 .dwattr $C$DW$T$40, DW_AT_name("mailbox_test_t")
215 .dwattr $C$DW$T$40, DW_AT_type(*$C$DW$T$26)
216 .dwattr $C$DW$T$40, DW_AT_language(DW_LANG_C)
217 .dwattr $C$DW$T$40, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
218 .dwattr $C$DW$T$40, DW_AT_decl_line(0x4e)
219 .dwattr $C$DW$T$40, DW_AT_decl_column(0x03)
220
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 5
221
222$C$DW$T$27 .dwtag DW_TAG_structure_type
223 .dwattr $C$DW$T$27, DW_AT_byte_size(0x0c)
224$C$DW$14 .dwtag DW_TAG_member
225 .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$23)
226 .dwattr $C$DW$14, DW_AT_name("addr")
227 .dwattr $C$DW$14, DW_AT_TI_symbol_name("addr")
228 .dwattr $C$DW$14, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
229 .dwattr $C$DW$14, DW_AT_accessibility(DW_ACCESS_public)
230 .dwattr $C$DW$14, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
231 .dwattr $C$DW$14, DW_AT_decl_line(0x51)
232 .dwattr $C$DW$14, DW_AT_decl_column(0x0b)
233
234$C$DW$15 .dwtag DW_TAG_member
235 .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$23)
236 .dwattr $C$DW$15, DW_AT_name("bitmask")
237 .dwattr $C$DW$15, DW_AT_TI_symbol_name("bitmask")
238 .dwattr $C$DW$15, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
239 .dwattr $C$DW$15, DW_AT_accessibility(DW_ACCESS_public)
240 .dwattr $C$DW$15, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
241 .dwattr $C$DW$15, DW_AT_decl_line(0x52)
242 .dwattr $C$DW$15, DW_AT_decl_column(0x0b)
243
244$C$DW$16 .dwtag DW_TAG_member
245 .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$23)
246 .dwattr $C$DW$16, DW_AT_name("val")
247 .dwattr $C$DW$16, DW_AT_TI_symbol_name("val")
248 .dwattr $C$DW$16, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
249 .dwattr $C$DW$16, DW_AT_accessibility(DW_ACCESS_public)
250 .dwattr $C$DW$16, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
251 .dwattr $C$DW$16, DW_AT_decl_line(0x53)
252 .dwattr $C$DW$16, DW_AT_decl_column(0x0b)
253
254 .dwattr $C$DW$T$27, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
255 .dwattr $C$DW$T$27, DW_AT_decl_line(0x50)
256 .dwattr $C$DW$T$27, DW_AT_decl_column(0x10)
257 .dwendtag $C$DW$T$27
258
259$C$DW$T$41 .dwtag DW_TAG_typedef
260 .dwattr $C$DW$T$41, DW_AT_name("mailbox_buslatch_t")
261 .dwattr $C$DW$T$41, DW_AT_type(*$C$DW$T$27)
262 .dwattr $C$DW$T$41, DW_AT_language(DW_LANG_C)
263 .dwattr $C$DW$T$41, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
264 .dwattr $C$DW$T$41, DW_AT_decl_line(0x54)
265 .dwattr $C$DW$T$41, DW_AT_decl_column(0x03)
266
267
268$C$DW$T$28 .dwtag DW_TAG_structure_type
269 .dwattr $C$DW$T$28, DW_AT_byte_size(0x04)
270$C$DW$17 .dwtag DW_TAG_member
271 .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$22)
272 .dwattr $C$DW$17, DW_AT_name("addr_0_7")
273 .dwattr $C$DW$17, DW_AT_TI_symbol_name("addr_0_7")
274 .dwattr $C$DW$17, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
275 .dwattr $C$DW$17, DW_AT_accessibility(DW_ACCESS_public)
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 6
276 .dwattr $C$DW$17, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
277 .dwattr $C$DW$17, DW_AT_decl_line(0x57)
278 .dwattr $C$DW$17, DW_AT_decl_column(0x0a)
279
280$C$DW$18 .dwtag DW_TAG_member
281 .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$22)
282 .dwattr $C$DW$18, DW_AT_name("addr_8_15")
283 .dwattr $C$DW$18, DW_AT_TI_symbol_name("addr_8_15")
284 .dwattr $C$DW$18, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
285 .dwattr $C$DW$18, DW_AT_accessibility(DW_ACCESS_public)
286 .dwattr $C$DW$18, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
287 .dwattr $C$DW$18, DW_AT_decl_line(0x58)
288 .dwattr $C$DW$18, DW_AT_decl_column(0x0a)
289
290$C$DW$19 .dwtag DW_TAG_member
291 .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$22)
292 .dwattr $C$DW$19, DW_AT_name("data_0_7")
293 .dwattr $C$DW$19, DW_AT_TI_symbol_name("data_0_7")
294 .dwattr $C$DW$19, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
295 .dwattr $C$DW$19, DW_AT_accessibility(DW_ACCESS_public)
296 .dwattr $C$DW$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
297 .dwattr $C$DW$19, DW_AT_decl_line(0x59)
298 .dwattr $C$DW$19, DW_AT_decl_column(0x0a)
299
300$C$DW$20 .dwtag DW_TAG_member
301 .dwattr $C$DW$20, DW_AT_type(*$C$DW$T$22)
302 .dwattr $C$DW$20, DW_AT_name("data_8_15")
303 .dwattr $C$DW$20, DW_AT_TI_symbol_name("data_8_15")
304 .dwattr $C$DW$20, DW_AT_data_member_location[DW_OP_plus_uconst 0x3]
305 .dwattr $C$DW$20, DW_AT_accessibility(DW_ACCESS_public)
306 .dwattr $C$DW$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
307 .dwattr $C$DW$20, DW_AT_decl_line(0x5a)
308 .dwattr $C$DW$20, DW_AT_decl_column(0x0a)
309
310 .dwattr $C$DW$T$28, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
311 .dwattr $C$DW$T$28, DW_AT_decl_line(0x56)
312 .dwattr $C$DW$T$28, DW_AT_decl_column(0x10)
313 .dwendtag $C$DW$T$28
314
315$C$DW$T$42 .dwtag DW_TAG_typedef
316 .dwattr $C$DW$T$42, DW_AT_name("mailbox_buslatch_test_t")
317 .dwattr $C$DW$T$42, DW_AT_type(*$C$DW$T$28)
318 .dwattr $C$DW$T$42, DW_AT_language(DW_LANG_C)
319 .dwattr $C$DW$T$42, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
320 .dwattr $C$DW$T$42, DW_AT_decl_line(0x5b)
321 .dwattr $C$DW$T$42, DW_AT_decl_column(0x03)
322
323
324$C$DW$T$30 .dwtag DW_TAG_structure_type
325 .dwattr $C$DW$T$30, DW_AT_byte_size(0x40c)
326$C$DW$21 .dwtag DW_TAG_member
327 .dwattr $C$DW$21, DW_AT_type(*$C$DW$T$22)
328 .dwattr $C$DW$21, DW_AT_name("cur_status")
329 .dwattr $C$DW$21, DW_AT_TI_symbol_name("cur_status")
330 .dwattr $C$DW$21, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 7
331 .dwattr $C$DW$21, DW_AT_accessibility(DW_ACCESS_public)
332 .dwattr $C$DW$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
333 .dwattr $C$DW$21, DW_AT_decl_line(0x61)
334 .dwattr $C$DW$21, DW_AT_decl_column(0x0a)
335
336$C$DW$22 .dwtag DW_TAG_member
337 .dwattr $C$DW$22, DW_AT_type(*$C$DW$T$22)
338 .dwattr $C$DW$22, DW_AT_name("control")
339 .dwattr $C$DW$22, DW_AT_TI_symbol_name("control")
340 .dwattr $C$DW$22, DW_AT_data_member_location[DW_OP_plus_uconst 0x1]
341 .dwattr $C$DW$22, DW_AT_accessibility(DW_ACCESS_public)
342 .dwattr $C$DW$22, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
343 .dwattr $C$DW$22, DW_AT_decl_line(0x62)
344 .dwattr $C$DW$22, DW_AT_decl_column(0x0a)
345
346$C$DW$23 .dwtag DW_TAG_member
347 .dwattr $C$DW$23, DW_AT_type(*$C$DW$T$24)
348 .dwattr $C$DW$23, DW_AT_name("wordcount")
349 .dwattr $C$DW$23, DW_AT_TI_symbol_name("wordcount")
350 .dwattr $C$DW$23, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
351 .dwattr $C$DW$23, DW_AT_accessibility(DW_ACCESS_public)
352 .dwattr $C$DW$23, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
353 .dwattr $C$DW$23, DW_AT_decl_line(0x63)
354 .dwattr $C$DW$23, DW_AT_decl_column(0x0b)
355
356$C$DW$24 .dwtag DW_TAG_member
357 .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$23)
358 .dwattr $C$DW$24, DW_AT_name("cur_addr")
359 .dwattr $C$DW$24, DW_AT_TI_symbol_name("cur_addr")
360 .dwattr $C$DW$24, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
361 .dwattr $C$DW$24, DW_AT_accessibility(DW_ACCESS_public)
362 .dwattr $C$DW$24, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
363 .dwattr $C$DW$24, DW_AT_decl_line(0x64)
364 .dwattr $C$DW$24, DW_AT_decl_column(0x0b)
365
366$C$DW$25 .dwtag DW_TAG_member
367 .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$23)
368 .dwattr $C$DW$25, DW_AT_name("startaddr")
369 .dwattr $C$DW$25, DW_AT_TI_symbol_name("startaddr")
370 .dwattr $C$DW$25, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
371 .dwattr $C$DW$25, DW_AT_accessibility(DW_ACCESS_public)
372 .dwattr $C$DW$25, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
373 .dwattr $C$DW$25, DW_AT_decl_line(0x65)
374 .dwattr $C$DW$25, DW_AT_decl_column(0x0b)
375
376$C$DW$26 .dwtag DW_TAG_member
377 .dwattr $C$DW$26, DW_AT_type(*$C$DW$T$29)
378 .dwattr $C$DW$26, DW_AT_name("words")
379 .dwattr $C$DW$26, DW_AT_TI_symbol_name("words")
380 .dwattr $C$DW$26, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
381 .dwattr $C$DW$26, DW_AT_accessibility(DW_ACCESS_public)
382 .dwattr $C$DW$26, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
383 .dwattr $C$DW$26, DW_AT_decl_line(0x66)
384 .dwattr $C$DW$26, DW_AT_decl_column(0x0b)
385
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 8
386 .dwattr $C$DW$T$30, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
387 .dwattr $C$DW$T$30, DW_AT_decl_line(0x5f)
388 .dwattr $C$DW$T$30, DW_AT_decl_column(0x10)
389 .dwendtag $C$DW$T$30
390
391$C$DW$T$43 .dwtag DW_TAG_typedef
392 .dwattr $C$DW$T$43, DW_AT_name("mailbox_dma_t")
393 .dwattr $C$DW$T$43, DW_AT_type(*$C$DW$T$30)
394 .dwattr $C$DW$T$43, DW_AT_language(DW_LANG_C)
395 .dwattr $C$DW$T$43, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
396 .dwattr $C$DW$T$43, DW_AT_decl_line(0x67)
397 .dwattr $C$DW$T$43, DW_AT_decl_column(0x03)
398
399
400$C$DW$T$31 .dwtag DW_TAG_structure_type
401 .dwattr $C$DW$T$31, DW_AT_byte_size(0x03)
402$C$DW$27 .dwtag DW_TAG_member
403 .dwattr $C$DW$27, DW_AT_type(*$C$DW$T$24)
404 .dwattr $C$DW$27, DW_AT_name("vector")
405 .dwattr $C$DW$27, DW_AT_TI_symbol_name("vector")
406 .dwattr $C$DW$27, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
407 .dwattr $C$DW$27, DW_AT_accessibility(DW_ACCESS_public)
408 .dwattr $C$DW$27, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
409 .dwattr $C$DW$27, DW_AT_decl_line(0x6b)
410 .dwattr $C$DW$27, DW_AT_decl_column(0x0b)
411
412$C$DW$28 .dwtag DW_TAG_member
413 .dwattr $C$DW$28, DW_AT_type(*$C$DW$T$22)
414 .dwattr $C$DW$28, DW_AT_name("priority_bit")
415 .dwattr $C$DW$28, DW_AT_TI_symbol_name("priority_bit")
416 .dwattr $C$DW$28, DW_AT_data_member_location[DW_OP_plus_uconst 0x2]
417 .dwattr $C$DW$28, DW_AT_accessibility(DW_ACCESS_public)
418 .dwattr $C$DW$28, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
419 .dwattr $C$DW$28, DW_AT_decl_line(0x6c)
420 .dwattr $C$DW$28, DW_AT_decl_column(0x0a)
421
422 .dwattr $C$DW$T$31, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
423 .dwattr $C$DW$T$31, DW_AT_decl_line(0x6a)
424 .dwattr $C$DW$T$31, DW_AT_decl_column(0x10)
425 .dwendtag $C$DW$T$31
426
427$C$DW$T$44 .dwtag DW_TAG_typedef
428 .dwattr $C$DW$T$44, DW_AT_name("mailbox_intr_t")
429 .dwattr $C$DW$T$44, DW_AT_type(*$C$DW$T$31)
430 .dwattr $C$DW$T$44, DW_AT_language(DW_LANG_C)
431 .dwattr $C$DW$T$44, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
432 .dwattr $C$DW$T$44, DW_AT_decl_line(0x6d)
433 .dwattr $C$DW$T$44, DW_AT_decl_column(0x03)
434
435
436$C$DW$T$36 .dwtag DW_TAG_structure_type
437 .dwattr $C$DW$T$36, DW_AT_byte_size(0x424)
438$C$DW$29 .dwtag DW_TAG_member
439 .dwattr $C$DW$29, DW_AT_type(*$C$DW$T$23)
440 .dwattr $C$DW$29, DW_AT_name("arm2pru_req")
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 9
441 .dwattr $C$DW$29, DW_AT_TI_symbol_name("arm2pru_req")
442 .dwattr $C$DW$29, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
443 .dwattr $C$DW$29, DW_AT_accessibility(DW_ACCESS_public)
444 .dwattr $C$DW$29, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
445 .dwattr $C$DW$29, DW_AT_decl_line(0x90)
446 .dwattr $C$DW$29, DW_AT_decl_column(0x0b)
447
448$C$DW$30 .dwtag DW_TAG_member
449 .dwattr $C$DW$30, DW_AT_type(*$C$DW$T$23)
450 .dwattr $C$DW$30, DW_AT_name("arm2pru_resp")
451 .dwattr $C$DW$30, DW_AT_TI_symbol_name("arm2pru_resp")
452 .dwattr $C$DW$30, DW_AT_data_member_location[DW_OP_plus_uconst 0x4]
453 .dwattr $C$DW$30, DW_AT_accessibility(DW_ACCESS_public)
454 .dwattr $C$DW$30, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
455 .dwattr $C$DW$30, DW_AT_decl_line(0x91)
456 .dwattr $C$DW$30, DW_AT_decl_column(0x0b)
457
458$C$DW$31 .dwtag DW_TAG_member
459 .dwattr $C$DW$31, DW_AT_type(*$C$DW$T$34)
460 .dwattr $C$DW$31, DW_AT_name("ddrmem_base_physical")
461 .dwattr $C$DW$31, DW_AT_TI_symbol_name("ddrmem_base_physical")
462 .dwattr $C$DW$31, DW_AT_data_member_location[DW_OP_plus_uconst 0x8]
463 .dwattr $C$DW$31, DW_AT_accessibility(DW_ACCESS_public)
464 .dwattr $C$DW$31, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
465 .dwattr $C$DW$31, DW_AT_decl_line(0x94)
466 .dwattr $C$DW$31, DW_AT_decl_column(0x15)
467
468$C$DW$32 .dwtag DW_TAG_member
469 .dwattr $C$DW$32, DW_AT_type(*$C$DW$T$35)
470 .dwattr $C$DW$32, DW_AT_name("events")
471 .dwattr $C$DW$32, DW_AT_TI_symbol_name("events")
472 .dwattr $C$DW$32, DW_AT_data_member_location[DW_OP_plus_uconst 0xc]
473 .dwattr $C$DW$32, DW_AT_accessibility(DW_ACCESS_public)
474 .dwattr $C$DW$32, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
475 .dwattr $C$DW$32, DW_AT_decl_line(0x97)
476 .dwattr $C$DW$32, DW_AT_decl_column(0x13)
477
478$C$DW$33 .dwtag DW_TAG_member
479 .dwattr $C$DW$33, DW_AT_type(*$C$DW$T$45)
480 .dwattr $C$DW$33, DW_AT_name("$P$T1")
481 .dwattr $C$DW$33, DW_AT_TI_symbol_name("$P$T1")
482 .dwattr $C$DW$33, DW_AT_data_member_location[DW_OP_plus_uconst 0x18]
483 .dwattr $C$DW$33, DW_AT_accessibility(DW_ACCESS_public)
484 .dwattr $C$DW$33, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
485 .dwattr $C$DW$33, DW_AT_decl_line(0x9a)
486 .dwattr $C$DW$33, DW_AT_decl_column(0x02)
487
488 .dwattr $C$DW$T$36, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
489 .dwattr $C$DW$T$36, DW_AT_decl_line(0x8d)
490 .dwattr $C$DW$T$36, DW_AT_decl_column(0x10)
491 .dwendtag $C$DW$T$36
492
493$C$DW$T$46 .dwtag DW_TAG_typedef
494 .dwattr $C$DW$T$46, DW_AT_name("mailbox_t")
495 .dwattr $C$DW$T$46, DW_AT_type(*$C$DW$T$36)
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 10
496 .dwattr $C$DW$T$46, DW_AT_language(DW_LANG_C)
497 .dwattr $C$DW$T$46, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
498 .dwattr $C$DW$T$46, DW_AT_decl_line(0xa1)
499 .dwattr $C$DW$T$46, DW_AT_decl_column(0x03)
500
501$C$DW$T$47 .dwtag DW_TAG_volatile_type
502 .dwattr $C$DW$T$47, DW_AT_type(*$C$DW$T$46)
503
504
505$C$DW$T$39 .dwtag DW_TAG_union_type
506 .dwattr $C$DW$T$39, DW_AT_byte_size(0x40000)
507$C$DW$34 .dwtag DW_TAG_member
508 .dwattr $C$DW$34, DW_AT_type(*$C$DW$T$37)
509 .dwattr $C$DW$34, DW_AT_name("words")
510 .dwattr $C$DW$34, DW_AT_TI_symbol_name("words")
511 .dwattr $C$DW$34, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
512 .dwattr $C$DW$34, DW_AT_accessibility(DW_ACCESS_public)
513 .dwattr $C$DW$34, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/un
514 .dwattr $C$DW$34, DW_AT_decl_line(0x35)
515 .dwattr $C$DW$34, DW_AT_decl_column(0x0b)
516
517$C$DW$35 .dwtag DW_TAG_member
518 .dwattr $C$DW$35, DW_AT_type(*$C$DW$T$38)
519 .dwattr $C$DW$35, DW_AT_name("bytes")
520 .dwattr $C$DW$35, DW_AT_TI_symbol_name("bytes")
521 .dwattr $C$DW$35, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
522 .dwattr $C$DW$35, DW_AT_accessibility(DW_ACCESS_public)
523 .dwattr $C$DW$35, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/un
524 .dwattr $C$DW$35, DW_AT_decl_line(0x36)
525 .dwattr $C$DW$35, DW_AT_decl_column(0x0b)
526
527 .dwattr $C$DW$T$39, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
528 .dwattr $C$DW$T$39, DW_AT_decl_line(0x34)
529 .dwattr $C$DW$T$39, DW_AT_decl_column(0x08)
530 .dwendtag $C$DW$T$39
531
532
533$C$DW$T$45 .dwtag DW_TAG_union_type
534 .dwattr $C$DW$T$45, DW_AT_byte_size(0x40c)
535$C$DW$36 .dwtag DW_TAG_member
536 .dwattr $C$DW$36, DW_AT_type(*$C$DW$T$40)
537 .dwattr $C$DW$36, DW_AT_name("mailbox_test")
538 .dwattr $C$DW$36, DW_AT_TI_symbol_name("mailbox_test")
539 .dwattr $C$DW$36, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
540 .dwattr $C$DW$36, DW_AT_accessibility(DW_ACCESS_public)
541 .dwattr $C$DW$36, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
542 .dwattr $C$DW$36, DW_AT_decl_line(0x9b)
543 .dwattr $C$DW$36, DW_AT_decl_column(0x12)
544
545$C$DW$37 .dwtag DW_TAG_member
546 .dwattr $C$DW$37, DW_AT_type(*$C$DW$T$41)
547 .dwattr $C$DW$37, DW_AT_name("buslatch")
548 .dwattr $C$DW$37, DW_AT_TI_symbol_name("buslatch")
549 .dwattr $C$DW$37, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
550 .dwattr $C$DW$37, DW_AT_accessibility(DW_ACCESS_public)
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 11
551 .dwattr $C$DW$37, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
552 .dwattr $C$DW$37, DW_AT_decl_line(0x9c)
553 .dwattr $C$DW$37, DW_AT_decl_column(0x16)
554
555$C$DW$38 .dwtag DW_TAG_member
556 .dwattr $C$DW$38, DW_AT_type(*$C$DW$T$42)
557 .dwattr $C$DW$38, DW_AT_name("buslatch_test")
558 .dwattr $C$DW$38, DW_AT_TI_symbol_name("buslatch_test")
559 .dwattr $C$DW$38, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
560 .dwattr $C$DW$38, DW_AT_accessibility(DW_ACCESS_public)
561 .dwattr $C$DW$38, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
562 .dwattr $C$DW$38, DW_AT_decl_line(0x9d)
563 .dwattr $C$DW$38, DW_AT_decl_column(0x1b)
564
565$C$DW$39 .dwtag DW_TAG_member
566 .dwattr $C$DW$39, DW_AT_type(*$C$DW$T$43)
567 .dwattr $C$DW$39, DW_AT_name("dma")
568 .dwattr $C$DW$39, DW_AT_TI_symbol_name("dma")
569 .dwattr $C$DW$39, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
570 .dwattr $C$DW$39, DW_AT_accessibility(DW_ACCESS_public)
571 .dwattr $C$DW$39, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
572 .dwattr $C$DW$39, DW_AT_decl_line(0x9e)
573 .dwattr $C$DW$39, DW_AT_decl_column(0x11)
574
575$C$DW$40 .dwtag DW_TAG_member
576 .dwattr $C$DW$40, DW_AT_type(*$C$DW$T$44)
577 .dwattr $C$DW$40, DW_AT_name("intr")
578 .dwattr $C$DW$40, DW_AT_TI_symbol_name("intr")
579 .dwattr $C$DW$40, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
580 .dwattr $C$DW$40, DW_AT_accessibility(DW_ACCESS_public)
581 .dwattr $C$DW$40, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ma
582 .dwattr $C$DW$40, DW_AT_decl_line(0x9f)
583 .dwattr $C$DW$40, DW_AT_decl_column(0x12)
584
585 .dwattr $C$DW$T$45, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
586 .dwattr $C$DW$T$45, DW_AT_decl_line(0x9a)
587 .dwattr $C$DW$T$45, DW_AT_decl_column(0x08)
588 .dwendtag $C$DW$T$45
589
590$C$DW$T$2 .dwtag DW_TAG_unspecified_type
591 .dwattr $C$DW$T$2, DW_AT_name("void")
592
593$C$DW$T$4 .dwtag DW_TAG_base_type
594 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
595 .dwattr $C$DW$T$4, DW_AT_name("bool")
596 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
597
598$C$DW$T$5 .dwtag DW_TAG_base_type
599 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
600 .dwattr $C$DW$T$5, DW_AT_name("signed char")
601 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
602
603$C$DW$T$6 .dwtag DW_TAG_base_type
604 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
605 .dwattr $C$DW$T$6, DW_AT_name("unsigned char")
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 12
606 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
607
608$C$DW$T$22 .dwtag DW_TAG_typedef
609 .dwattr $C$DW$T$22, DW_AT_name("uint8_t")
610 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$6)
611 .dwattr $C$DW$T$22, DW_AT_language(DW_LANG_C)
612 .dwattr $C$DW$T$22, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compi
613 .dwattr $C$DW$T$22, DW_AT_decl_line(0x3d)
614 .dwattr $C$DW$T$22, DW_AT_decl_column(0x1c)
615
616
617$C$DW$T$38 .dwtag DW_TAG_array_type
618 .dwattr $C$DW$T$38, DW_AT_type(*$C$DW$T$22)
619 .dwattr $C$DW$T$38, DW_AT_language(DW_LANG_C)
620 .dwattr $C$DW$T$38, DW_AT_byte_size(0x40000)
621$C$DW$41 .dwtag DW_TAG_subrange_type
622 .dwattr $C$DW$41, DW_AT_upper_bound(0x3ffff)
623
624 .dwendtag $C$DW$T$38
625
626$C$DW$T$7 .dwtag DW_TAG_base_type
627 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
628 .dwattr $C$DW$T$7, DW_AT_name("wchar_t")
629 .dwattr $C$DW$T$7, DW_AT_byte_size(0x04)
630
631$C$DW$T$8 .dwtag DW_TAG_base_type
632 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
633 .dwattr $C$DW$T$8, DW_AT_name("short")
634 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02)
635
636$C$DW$T$9 .dwtag DW_TAG_base_type
637 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
638 .dwattr $C$DW$T$9, DW_AT_name("unsigned short")
639 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02)
640
641$C$DW$T$24 .dwtag DW_TAG_typedef
642 .dwattr $C$DW$T$24, DW_AT_name("uint16_t")
643 .dwattr $C$DW$T$24, DW_AT_type(*$C$DW$T$9)
644 .dwattr $C$DW$T$24, DW_AT_language(DW_LANG_C)
645 .dwattr $C$DW$T$24, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compi
646 .dwattr $C$DW$T$24, DW_AT_decl_line(0x3f)
647 .dwattr $C$DW$T$24, DW_AT_decl_column(0x1c)
648
649
650$C$DW$T$29 .dwtag DW_TAG_array_type
651 .dwattr $C$DW$T$29, DW_AT_type(*$C$DW$T$24)
652 .dwattr $C$DW$T$29, DW_AT_language(DW_LANG_C)
653 .dwattr $C$DW$T$29, DW_AT_byte_size(0x400)
654$C$DW$42 .dwtag DW_TAG_subrange_type
655 .dwattr $C$DW$42, DW_AT_upper_bound(0x1ff)
656
657 .dwendtag $C$DW$T$29
658
659
660$C$DW$T$37 .dwtag DW_TAG_array_type
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 13
661 .dwattr $C$DW$T$37, DW_AT_type(*$C$DW$T$24)
662 .dwattr $C$DW$T$37, DW_AT_language(DW_LANG_C)
663 .dwattr $C$DW$T$37, DW_AT_byte_size(0x40000)
664$C$DW$43 .dwtag DW_TAG_subrange_type
665 .dwattr $C$DW$43, DW_AT_upper_bound(0x1ffff)
666
667 .dwendtag $C$DW$T$37
668
669$C$DW$T$10 .dwtag DW_TAG_base_type
670 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
671 .dwattr $C$DW$T$10, DW_AT_name("int")
672 .dwattr $C$DW$T$10, DW_AT_byte_size(0x04)
673
674$C$DW$T$11 .dwtag DW_TAG_base_type
675 .dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
676 .dwattr $C$DW$T$11, DW_AT_name("unsigned int")
677 .dwattr $C$DW$T$11, DW_AT_byte_size(0x04)
678
679$C$DW$T$23 .dwtag DW_TAG_typedef
680 .dwattr $C$DW$T$23, DW_AT_name("uint32_t")
681 .dwattr $C$DW$T$23, DW_AT_type(*$C$DW$T$11)
682 .dwattr $C$DW$T$23, DW_AT_language(DW_LANG_C)
683 .dwattr $C$DW$T$23, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compi
684 .dwattr $C$DW$T$23, DW_AT_decl_line(0x41)
685 .dwattr $C$DW$T$23, DW_AT_decl_column(0x1c)
686
687$C$DW$T$12 .dwtag DW_TAG_base_type
688 .dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
689 .dwattr $C$DW$T$12, DW_AT_name("long")
690 .dwattr $C$DW$T$12, DW_AT_byte_size(0x04)
691
692$C$DW$T$13 .dwtag DW_TAG_base_type
693 .dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
694 .dwattr $C$DW$T$13, DW_AT_name("unsigned long")
695 .dwattr $C$DW$T$13, DW_AT_byte_size(0x04)
696
697$C$DW$T$14 .dwtag DW_TAG_base_type
698 .dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
699 .dwattr $C$DW$T$14, DW_AT_name("long long")
700 .dwattr $C$DW$T$14, DW_AT_byte_size(0x08)
701
702$C$DW$T$15 .dwtag DW_TAG_base_type
703 .dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
704 .dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
705 .dwattr $C$DW$T$15, DW_AT_byte_size(0x08)
706
707$C$DW$T$16 .dwtag DW_TAG_base_type
708 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
709 .dwattr $C$DW$T$16, DW_AT_name("float")
710 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04)
711
712$C$DW$T$17 .dwtag DW_TAG_base_type
713 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
714 .dwattr $C$DW$T$17, DW_AT_name("double")
715 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08)
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:29 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_arm_mailbox.asm PAGE 14
716
717$C$DW$T$18 .dwtag DW_TAG_base_type
718 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
719 .dwattr $C$DW$T$18, DW_AT_name("long double")
720 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08)
721
722 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
723 .dwendtag $C$DW$CU
724
No Assembly Errors, No Assembly Warnings

8
10.01_base/4_deploy/pru1_arm_mailbox.nfo
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@@ -1,8 +0,0 @@
PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
Global variable is not referenced in this file:
extern int __MCALL_implicit_state__
== END OF INFO OUTPUT==

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10.01_base/4_deploy/pru1_arm_mailbox.object
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10.01_base/4_deploy/pru1_arm_mailbox.pp
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@@ -1,6 +0,0 @@
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.object: pru1_arm_mailbox.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_arm_mailbox.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h

3325
10.01_base/4_deploy/pru1_buslatches.asm
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3648
10.01_base/4_deploy/pru1_buslatches.lst
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108
10.01_base/4_deploy/pru1_buslatches.nfo
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@@ -1,108 +0,0 @@
PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
==============================================================================
extern void buslatches_reset() is called from 0 sites in this file.
It appears to be inlineable (size = 81 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (8 times)
buslatches_pru0_dataout() (8 times)
==============================================================================
extern void buslatches_powercycle() is called from 0 sites in this file.
It appears to be inlineable (size = 79 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (7 times)
buslatches_pru0_dataout() (4 times)
==============================================================================
extern void buslatches_test() is called from 0 sites in this file.
It appears to be inlineable (size = 27 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
extern void buslatches_powercycle() is called from 0 sites in this file.
It appears to be inlineable (size = 79 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (7 times)
buslatches_pru0_dataout() (4 times)
extern void buslatches_reset() is called from 0 sites in this file.
It appears to be inlineable (size = 81 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (8 times)
buslatches_pru0_dataout() (8 times)
extern void buslatches_test() is called from 0 sites in this file.
It appears to be inlineable (size = 27 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
These functions may be recursive:
buslatches_powercycle()
buslatches_reset()
These external functions are called but not defined here:
buslatches_pru0_dataout()
__delay_cycles()
==============================================================================
extern void buslatches_test() is called from 0 sites in this file.
It appears to be inlineable (size = 27 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern void buslatches_reset() is called from 0 sites in this file.
It appears to be inlineable (size = 81 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void buslatches_powercycle() is called from 0 sites in this file.
It appears to be inlineable (size = 79 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void buslatches_test() is called from 0 sites in this file.
It appears to be inlineable (size = 27 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern void buslatches_reset() is called from 0 sites in this file.
It appears to be inlineable (size = 81 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void buslatches_powercycle() is called from 0 sites in this file.
It appears to be inlineable (size = 79 units)
It has 7 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
== END OF INFO OUTPUT==

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10.01_base/4_deploy/pru1_buslatches.pp
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@@ -1,14 +0,0 @@
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: pru1_buslatches.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdlib.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_ti_config.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/linkage.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: pru1_utils.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_cfg.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_ctrl.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_buslatches.object: pru1_buslatches.h

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PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:40 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_buslatches_pru0_datout.asmsrc PAGE 1
1; pru1_buslatches_pru0_datout.asmsrc: transfer R14 to PRU0 over XFR
2;
3; Copyright (c) 2018, Joerg Hoppe
4; j_hoppe@t-online.de, www.retrocmp.com
5;
6; Permission is hereby granted, free of charge, to any person obtaining a
7; copy of this software and associated documentation files (the "Software"),
8; to deal in the Software without restriction, including without limitation
9; the rights to use, copy, modify, merge, publish, distribute, sublicense,
10; and/or sell copies of the Software, and to permit persons to whom the
11; Software is furnished to do so, subject to the following conditions:
12;
13; The above copyright notice and this permission notice shall be included in
14; all copies or substantial portions of the Software.
15;
16; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19; JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
20; IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21; CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22;
23;
24; 12-nov-2018 JH entered beta phase
25;
26;
27; Assembler function, which transfers r14 to PRU0
28; PRU0 writes this then to DATAOUT pins
29;
30; to be declared in C as
31; extern "C" {
32; void pru1_pru0_dataout(uint32_t val) ;
33; }
34; See Compiler 2.2 Guide, Chapter 6.6
35
36 .global buslatches_pru0_dataout
37
38 ; a 32bit parameter is received in r14
39 ; 10 ns delay
40 00000000 buslatches_pru0_dataout:
41 ; do nothing at first
42 ; Device ID 14 = "other PRU"
43 00000000 0000002F07018E xout 14,&r14,4
44 00000004 00000020C30000 jmp r3.w2 ; return address
45
46
47; loop on pru0: 15ns
48; loop:
49; xin 14,&r14,4
50; mov
51; br loop
No Assembly Errors, No Assembly Warnings

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10.01_base/4_deploy/pru1_config.h
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/*** Following code generated by "/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/update_pru_config.sh 1 pru1_array.c /home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_config /home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1.map" ***/
#ifndef _PRU1_CONFIG_H_
#define _PRU1_CONFIG_H_
#include <stdint.h>
#ifndef _PRU1_CONFIG_C_
// extern const uint32_t pru1_image_0[] ;
extern uint32_t pru1_image_0[] ;
#endif
unsigned pru1_sizeof_code(void) ;
// code entry point "_c_int00_noinit_noargs" from linker map file:
#define PRU1_ENTRY_ADDR 0x00000000
// Mailbox page & offset in PRU internal shared 12 KB RAM
// Accessible by both PRUs, must be located in shared RAM
// offset 0 == addr 0x10000 in linker cmd files for PRU0 AND PRU1 projects.
// For use with prussdrv_map_prumem()
#ifndef PRU_MAILBOX_RAM_ID
#define PRU_MAILBOX_RAM_ID PRUSS0_SHARED_DATARAM
#define PRU_MAILBOX_RAM_OFFSET 0
#endif
// Device register page & offset in PRU0 8KB RAM mapped into PRU1 space
// offset 0 == addr 0x2000 in linker cmd files for PRU1 projects.
// For use with prussdrv_map_prumem()
#ifndef PRU_DEVICEREGISTER_RAM_ID
#define PRU_DEVICEREGISTER_RAM_ID PRUSS0_PRU0_DATARAM
#define PRU_DEVICEREGISTER_RAM_OFFSET 0
#endif
#endif

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PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
==============================================================================
extern void ddrmem_fill_pattern() is called from 0 sites in this file.
It appears to be inlineable (size = 19 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
extern void ddrmem_fill_pattern() is called from 0 sites in this file.
It appears to be inlineable (size = 19 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern void ddrmem_fill_pattern() is called from 0 sites in this file.
It appears to be inlineable (size = 19 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern void ddrmem_fill_pattern() is called from 0 sites in this file.
It appears to be inlineable (size = 19 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
== END OF INFO OUTPUT==

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/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: pru1_ddrmem.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/string.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_ti_config.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/linkage.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_ddrmem.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h

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PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
==============================================================================
static void *memset() is called from 3 sites in this file.
It appears to be inlineable (size = 21 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char iopageregisters_read() is called from 0 sites in this file.
It appears to be inlineable (size = 97 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (1 times)
==============================================================================
extern unsigned char iopageregisters_write_w() is called from 0 sites in this file.
It appears to be inlineable (size = 103 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (1 times)
==============================================================================
extern unsigned char iopageregisters_write_b() is called from 0 sites in this file.
It appears to be inlineable (size = 128 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (1 times)
==============================================================================
extern void iopageregisters_init() is called from 0 sites in this file.
It appears to be inlineable (size = 16 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
memset() (3 times)
extern void iopageregisters_init() is called from 0 sites in this file.
It appears to be inlineable (size = 16 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
memset() (3 times)
extern unsigned char iopageregisters_read() is called from 0 sites in this file.
It appears to be inlineable (size = 97 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (1 times)
extern unsigned char iopageregisters_write_b() is called from 0 sites in this file.
It appears to be inlineable (size = 128 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (1 times)
extern unsigned char iopageregisters_write_w() is called from 0 sites in this file.
It appears to be inlineable (size = 103 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
__delay_cycles() (1 times)
static void *memset() is called from 3 sites in this file.
It appears to be inlineable (size = 21 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
These functions may be recursive:
iopageregisters_read()
iopageregisters_write_b()
iopageregisters_write_w()
Inlineable function will be suppressed: memset()
These external functions are called but not defined here:
__delay_cycles()
==============================================================================
extern unsigned char iopageregisters_write_w() is called from 0 sites in this file.
It appears to be inlineable (size = 103 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char iopageregisters_write_b() is called from 0 sites in this file.
It appears to be inlineable (size = 128 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char iopageregisters_read() is called from 0 sites in this file.
It appears to be inlineable (size = 97 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void iopageregisters_init() is called from 0 sites in this file.
It appears to be inlineable (size = 16 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
memset() (3 times)
==============================================================================
extern unsigned char iopageregisters_write_w() is called from 0 sites in this file.
It appears to be inlineable (size = 103 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char iopageregisters_write_b() is called from 0 sites in this file.
It appears to be inlineable (size = 128 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char iopageregisters_read() is called from 0 sites in this file.
It appears to be inlineable (size = 97 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void iopageregisters_init() is called from 0 sites in this file.
It appears to be inlineable (size = 16 units)
It has 9 non-trivial scope blocks nested 5 deep.
It calls these functions:
memset() (3 times)
== END OF INFO OUTPUT==

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/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: pru1_iopageregisters.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/string.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_ti_config.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/linkage.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: pru1_utils.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_cfg.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_ctrl.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: pru1_buslatches.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_iopageregisters.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/iopageregister.h

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PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
==============================================================================
static void state_emulation() is called from 1 sites in this file.
It appears to be inlineable (size = 189 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
sm_init_start() (1 times)
sm_powercycle_start() (1 times)
sm_arb_state_idle() (1 times)
sm_dma_start() (1 times)
sm_intr_start() (1 times)
sm_arb_start() (2 times)
do_event_initializationsignals() (1 times)
? () (18 times)
sm_slave_start() (3 times)
__delay_cycles() (1 times)
buslatches_powercycle() (1 times)
buslatches_reset() (1 times)
==============================================================================
extern void main() is called from 0 sites in this file.
It appears to be inlineable (size = 318 units)
It has 10 non-trivial scope blocks nested 7 deep.
It calls these functions:
__halt() (1 times)
buslatches_test() (1 times)
buslatches_powercycle() (1 times)
ddrmem_fill_pattern() (1 times)
state_emulation() (1 times)
__delay_cycles() (6 times)
buslatches_pru0_dataout() (4 times)
sm_dma_start() (1 times)
? () (4 times)
sm_slave_start() (1 times)
buslatches_reset() (3 times)
iopageregisters_init() (1 times)
extern void main() is called from 0 sites in this file.
It has 10 non-trivial scope blocks nested 7 deep.
It calls these functions:
__halt() (1 times)
buslatches_test() (1 times)
buslatches_powercycle() (1 times)
ddrmem_fill_pattern() (1 times)
state_emulation() (1 times)
__delay_cycles() (6 times)
buslatches_pru0_dataout() (4 times)
sm_dma_start() (1 times)
? () (4 times)
sm_slave_start() (1 times)
buslatches_reset() (3 times)
iopageregisters_init() (1 times)
static void state_emulation() is called from 1 sites in this file.
It appears to be inlineable (size = 189 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
sm_init_start() (1 times)
sm_powercycle_start() (1 times)
sm_arb_state_idle() (1 times)
sm_dma_start() (1 times)
sm_intr_start() (1 times)
sm_arb_start() (2 times)
do_event_initializationsignals() (1 times)
? () (18 times)
sm_slave_start() (3 times)
__delay_cycles() (1 times)
buslatches_powercycle() (1 times)
buslatches_reset() (1 times)
These functions may be recursive:
main()
state_emulation()
Making this function inlineable: state_emulation()
Inlineable function will be suppressed: state_emulation()
These external functions are called but not defined here:
do_event_initializationsignals()
sm_arb_start()
sm_intr_start()
sm_arb_state_idle()
sm_powercycle_start()
sm_init_start()
iopageregisters_init()
buslatches_reset()
sm_slave_start()
? ()
sm_dma_start()
buslatches_pru0_dataout()
__delay_cycles()
ddrmem_fill_pattern()
buslatches_powercycle()
buslatches_test()
__halt()
==============================================================================
extern void main() is called from 0 sites in this file.
It has 10 non-trivial scope blocks nested 7 deep.
It calls these functions:
state_emulation() (1 times)
====== Unroll-and-jam Result Summary ======
LOOP#2 in main() fails to unroll-and-jam: Outer Loop has multiple blocks
====== End Unroll-and-jam Result ======
====== Unroll-and-jam Result Summary ======
LOOP#5 in main() fails to unroll-and-jam: Outer Loop has multiple blocks
====== End Unroll-and-jam Result ======
====== Unroll-and-jam Result Summary ======
LOOP#7 in main() fails to unroll-and-jam: Outer Loop has multiple blocks
====== End Unroll-and-jam Result ======
====== Unroll-and-jam Result Summary ======
LOOP#10 in main() fails to unroll-and-jam: Outer Loop has multiple blocks
====== End Unroll-and-jam Result ======
====== Unroll-and-jam Result Summary ======
LOOP#13 in main() fails to unroll-and-jam: Outer trip count may be NULL
====== End Unroll-and-jam Result ======
====== Unroll-and-jam Result Summary ======
LOOP#15 in main() fails to unroll-and-jam: Outer trip count may be NULL
====== End Unroll-and-jam Result ======
==============================================================================
extern void main() is called from 0 sites in this file.
It has 12 non-trivial scope blocks nested 7 deep.
It calls these functions:
state_emulation() (1 times)
== END OF INFO OUTPUT==

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/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_main.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdbool.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_cfg.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: resource_table_empty.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stddef.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/rsc_types.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/pru_types.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_utils.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_ctrl.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/iopageregister.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_buslatches.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_statemachine_arbitration.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_statemachine_dma.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_statemachine_intr.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_statemachine_slave.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_statemachine_init.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_main.object: pru1_statemachine_powercycle.h

147
10.01_base/4_deploy/pru1_pru_mailbox.asm
View File

@@ -1,147 +0,0 @@
;******************************************************************************
;* PRU C/C++ Codegen Unix v2.3.1 *
;* Date/Time created: Sun Mar 31 20:55:33 2019 *
;******************************************************************************
.compiler_opts --abi=eabi --endian=little --hll_source=on --object_format=elf --silicon_version=3 --symdebug:dwarf --symdebug:dwarf_version=3
$C$DW$CU .dwtag DW_TAG_compile_unit
.dwattr $C$DW$CU, DW_AT_name("pru1_pru_mailbox.c")
.dwattr $C$DW$CU, DW_AT_producer("TI PRU C/C++ Codegen Unix v2.3.1 Copyright (c) 2012-2017 Texas Instruments Incorporated")
.dwattr $C$DW$CU, DW_AT_TI_version(0x01)
.dwattr $C$DW$CU, DW_AT_comp_dir("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/pru1")
.global ||pru_pru_mailbox||
||pru_pru_mailbox||: .usect ".pru_pru_mailbox_sec",4,1
$C$DW$1 .dwtag DW_TAG_variable
.dwattr $C$DW$1, DW_AT_name("pru_pru_mailbox")
.dwattr $C$DW$1, DW_AT_TI_symbol_name("pru_pru_mailbox")
.dwattr $C$DW$1, DW_AT_location[DW_OP_addr ||pru_pru_mailbox||]
.dwattr $C$DW$1, DW_AT_type(*$C$DW$T$22)
.dwattr $C$DW$1, DW_AT_external
.dwattr $C$DW$1, DW_AT_decl_file("pru1_pru_mailbox.c")
.dwattr $C$DW$1, DW_AT_decl_line(0x2b)
.dwattr $C$DW$1, DW_AT_decl_column(0x1c)
; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/optpru --gen_opt_info=2 /tmp/TI1kruzD7jv /tmp/TI1krVdnvUT --opt_info_filename=/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_pru_mailbox.nfo
; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/acpiapru -@/tmp/TI1kroQKGZh
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
$C$DW$T$20 .dwtag DW_TAG_structure_type
.dwattr $C$DW$T$20, DW_AT_byte_size(0x04)
$C$DW$2 .dwtag DW_TAG_member
.dwattr $C$DW$2, DW_AT_type(*$C$DW$T$19)
.dwattr $C$DW$2, DW_AT_name("xxx_pru0_r30")
.dwattr $C$DW$2, DW_AT_TI_symbol_name("xxx_pru0_r30")
.dwattr $C$DW$2, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
.dwattr $C$DW$2, DW_AT_accessibility(DW_ACCESS_public)
.dwattr $C$DW$2, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h")
.dwattr $C$DW$2, DW_AT_decl_line(0x24)
.dwattr $C$DW$2, DW_AT_decl_column(0x0b)
.dwattr $C$DW$T$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h")
.dwattr $C$DW$T$20, DW_AT_decl_line(0x20)
.dwattr $C$DW$T$20, DW_AT_decl_column(0x10)
.dwendtag $C$DW$T$20
$C$DW$T$21 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$21, DW_AT_name("pru_pru_mailbox_t")
.dwattr $C$DW$T$21, DW_AT_type(*$C$DW$T$20)
.dwattr $C$DW$T$21, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h")
.dwattr $C$DW$T$21, DW_AT_decl_line(0x26)
.dwattr $C$DW$T$21, DW_AT_decl_column(0x03)
$C$DW$T$22 .dwtag DW_TAG_volatile_type
.dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$21)
$C$DW$T$2 .dwtag DW_TAG_unspecified_type
.dwattr $C$DW$T$2, DW_AT_name("void")
$C$DW$T$4 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
.dwattr $C$DW$T$4, DW_AT_name("bool")
.dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
$C$DW$T$5 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$5, DW_AT_name("signed char")
.dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
$C$DW$T$6 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
.dwattr $C$DW$T$6, DW_AT_name("unsigned char")
.dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
$C$DW$T$7 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
.dwattr $C$DW$T$7, DW_AT_name("wchar_t")
.dwattr $C$DW$T$7, DW_AT_byte_size(0x04)
$C$DW$T$8 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$8, DW_AT_name("short")
.dwattr $C$DW$T$8, DW_AT_byte_size(0x02)
$C$DW$T$9 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$9, DW_AT_name("unsigned short")
.dwattr $C$DW$T$9, DW_AT_byte_size(0x02)
$C$DW$T$10 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$10, DW_AT_name("int")
.dwattr $C$DW$T$10, DW_AT_byte_size(0x04)
$C$DW$T$11 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$11, DW_AT_name("unsigned int")
.dwattr $C$DW$T$11, DW_AT_byte_size(0x04)
$C$DW$T$19 .dwtag DW_TAG_typedef
.dwattr $C$DW$T$19, DW_AT_name("uint32_t")
.dwattr $C$DW$T$19, DW_AT_type(*$C$DW$T$11)
.dwattr $C$DW$T$19, DW_AT_language(DW_LANG_C)
.dwattr $C$DW$T$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h")
.dwattr $C$DW$T$19, DW_AT_decl_line(0x41)
.dwattr $C$DW$T$19, DW_AT_decl_column(0x1c)
$C$DW$T$12 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$12, DW_AT_name("long")
.dwattr $C$DW$T$12, DW_AT_byte_size(0x04)
$C$DW$T$13 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$13, DW_AT_name("unsigned long")
.dwattr $C$DW$T$13, DW_AT_byte_size(0x04)
$C$DW$T$14 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
.dwattr $C$DW$T$14, DW_AT_name("long long")
.dwattr $C$DW$T$14, DW_AT_byte_size(0x08)
$C$DW$T$15 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
.dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
.dwattr $C$DW$T$15, DW_AT_byte_size(0x08)
$C$DW$T$16 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$16, DW_AT_name("float")
.dwattr $C$DW$T$16, DW_AT_byte_size(0x04)
$C$DW$T$17 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$17, DW_AT_name("double")
.dwattr $C$DW$T$17, DW_AT_byte_size(0x08)
$C$DW$T$18 .dwtag DW_TAG_base_type
.dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
.dwattr $C$DW$T$18, DW_AT_name("long double")
.dwattr $C$DW$T$18, DW_AT_byte_size(0x08)
.dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
.dwendtag $C$DW$CU

164
10.01_base/4_deploy/pru1_pru_mailbox.lst
View File

@@ -1,164 +0,0 @@
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:34 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_pru_mailbox.asm PAGE 1
1;******************************************************************************
2;* PRU C/C++ Codegen Unix v2.3.1 *
3;* Date/Time created: Sun Mar 31 20:55:33 2019 *
4;******************************************************************************
5 .compiler_opts --abi=eabi --endian=little --hll_source=on --object_format=elf --silicon_versio
6
7$C$DW$CU .dwtag DW_TAG_compile_unit
8 .dwattr $C$DW$CU, DW_AT_name("pru1_pru_mailbox.c")
9 .dwattr $C$DW$CU, DW_AT_producer("TI PRU C/C++ Codegen Unix v2.3.1 Copyright (c) 2012-2017 Tex
10 .dwattr $C$DW$CU, DW_AT_TI_version(0x01)
11 .dwattr $C$DW$CU, DW_AT_comp_dir("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/pru1")
12 .global ||pru_pru_mailbox||
13 00000000 ||pru_pru_mailbox||: .usect ".pru_pru_mailbox_sec",4,1
14$C$DW$1 .dwtag DW_TAG_variable
15 .dwattr $C$DW$1, DW_AT_name("pru_pru_mailbox")
16 .dwattr $C$DW$1, DW_AT_TI_symbol_name("pru_pru_mailbox")
17 .dwattr $C$DW$1, DW_AT_location[DW_OP_addr ||pru_pru_mailbox||]
18 .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$22)
19 .dwattr $C$DW$1, DW_AT_external
20 .dwattr $C$DW$1, DW_AT_decl_file("pru1_pru_mailbox.c")
21 .dwattr $C$DW$1, DW_AT_decl_line(0x2b)
22 .dwattr $C$DW$1, DW_AT_decl_column(0x1c)
23
24; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/optpru --gen
25; /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//bin/acpiapru -@/
26
27;******************************************************************************
28;* TYPE INFORMATION *
29;******************************************************************************
30
31$C$DW$T$20 .dwtag DW_TAG_structure_type
32 .dwattr $C$DW$T$20, DW_AT_byte_size(0x04)
33$C$DW$2 .dwtag DW_TAG_member
34 .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$19)
35 .dwattr $C$DW$2, DW_AT_name("xxx_pru0_r30")
36 .dwattr $C$DW$2, DW_AT_TI_symbol_name("xxx_pru0_r30")
37 .dwattr $C$DW$2, DW_AT_data_member_location[DW_OP_plus_uconst 0x0]
38 .dwattr $C$DW$2, DW_AT_accessibility(DW_ACCESS_public)
39 .dwattr $C$DW$2, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru
40 .dwattr $C$DW$2, DW_AT_decl_line(0x24)
41 .dwattr $C$DW$2, DW_AT_decl_column(0x0b)
42
43 .dwattr $C$DW$T$20, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
44 .dwattr $C$DW$T$20, DW_AT_decl_line(0x20)
45 .dwattr $C$DW$T$20, DW_AT_decl_column(0x10)
46 .dwendtag $C$DW$T$20
47
48$C$DW$T$21 .dwtag DW_TAG_typedef
49 .dwattr $C$DW$T$21, DW_AT_name("pru_pru_mailbox_t")
50 .dwattr $C$DW$T$21, DW_AT_type(*$C$DW$T$20)
51 .dwattr $C$DW$T$21, DW_AT_language(DW_LANG_C)
52 .dwattr $C$DW$T$21, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/
53 .dwattr $C$DW$T$21, DW_AT_decl_line(0x26)
54 .dwattr $C$DW$T$21, DW_AT_decl_column(0x03)
55
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:34 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_pru_mailbox.asm PAGE 2
56$C$DW$T$22 .dwtag DW_TAG_volatile_type
57 .dwattr $C$DW$T$22, DW_AT_type(*$C$DW$T$21)
58
59$C$DW$T$2 .dwtag DW_TAG_unspecified_type
60 .dwattr $C$DW$T$2, DW_AT_name("void")
61
62$C$DW$T$4 .dwtag DW_TAG_base_type
63 .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean)
64 .dwattr $C$DW$T$4, DW_AT_name("bool")
65 .dwattr $C$DW$T$4, DW_AT_byte_size(0x01)
66
67$C$DW$T$5 .dwtag DW_TAG_base_type
68 .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char)
69 .dwattr $C$DW$T$5, DW_AT_name("signed char")
70 .dwattr $C$DW$T$5, DW_AT_byte_size(0x01)
71
72$C$DW$T$6 .dwtag DW_TAG_base_type
73 .dwattr $C$DW$T$6, DW_AT_encoding(DW_ATE_unsigned_char)
74 .dwattr $C$DW$T$6, DW_AT_name("unsigned char")
75 .dwattr $C$DW$T$6, DW_AT_byte_size(0x01)
76
77$C$DW$T$7 .dwtag DW_TAG_base_type
78 .dwattr $C$DW$T$7, DW_AT_encoding(DW_ATE_signed_char)
79 .dwattr $C$DW$T$7, DW_AT_name("wchar_t")
80 .dwattr $C$DW$T$7, DW_AT_byte_size(0x04)
81
82$C$DW$T$8 .dwtag DW_TAG_base_type
83 .dwattr $C$DW$T$8, DW_AT_encoding(DW_ATE_signed)
84 .dwattr $C$DW$T$8, DW_AT_name("short")
85 .dwattr $C$DW$T$8, DW_AT_byte_size(0x02)
86
87$C$DW$T$9 .dwtag DW_TAG_base_type
88 .dwattr $C$DW$T$9, DW_AT_encoding(DW_ATE_unsigned)
89 .dwattr $C$DW$T$9, DW_AT_name("unsigned short")
90 .dwattr $C$DW$T$9, DW_AT_byte_size(0x02)
91
92$C$DW$T$10 .dwtag DW_TAG_base_type
93 .dwattr $C$DW$T$10, DW_AT_encoding(DW_ATE_signed)
94 .dwattr $C$DW$T$10, DW_AT_name("int")
95 .dwattr $C$DW$T$10, DW_AT_byte_size(0x04)
96
97$C$DW$T$11 .dwtag DW_TAG_base_type
98 .dwattr $C$DW$T$11, DW_AT_encoding(DW_ATE_unsigned)
99 .dwattr $C$DW$T$11, DW_AT_name("unsigned int")
100 .dwattr $C$DW$T$11, DW_AT_byte_size(0x04)
101
102$C$DW$T$19 .dwtag DW_TAG_typedef
103 .dwattr $C$DW$T$19, DW_AT_name("uint32_t")
104 .dwattr $C$DW$T$19, DW_AT_type(*$C$DW$T$11)
105 .dwattr $C$DW$T$19, DW_AT_language(DW_LANG_C)
106 .dwattr $C$DW$T$19, DW_AT_decl_file("/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compi
107 .dwattr $C$DW$T$19, DW_AT_decl_line(0x41)
108 .dwattr $C$DW$T$19, DW_AT_decl_column(0x1c)
109
110$C$DW$T$12 .dwtag DW_TAG_base_type
PRU Assembler Unix v2.3.1 Sun Mar 31 20:55:34 2019
Tools Copyright (c) 2012-2017 Texas Instruments Incorporated
pru1_pru_mailbox.asm PAGE 3
111 .dwattr $C$DW$T$12, DW_AT_encoding(DW_ATE_signed)
112 .dwattr $C$DW$T$12, DW_AT_name("long")
113 .dwattr $C$DW$T$12, DW_AT_byte_size(0x04)
114
115$C$DW$T$13 .dwtag DW_TAG_base_type
116 .dwattr $C$DW$T$13, DW_AT_encoding(DW_ATE_unsigned)
117 .dwattr $C$DW$T$13, DW_AT_name("unsigned long")
118 .dwattr $C$DW$T$13, DW_AT_byte_size(0x04)
119
120$C$DW$T$14 .dwtag DW_TAG_base_type
121 .dwattr $C$DW$T$14, DW_AT_encoding(DW_ATE_signed)
122 .dwattr $C$DW$T$14, DW_AT_name("long long")
123 .dwattr $C$DW$T$14, DW_AT_byte_size(0x08)
124
125$C$DW$T$15 .dwtag DW_TAG_base_type
126 .dwattr $C$DW$T$15, DW_AT_encoding(DW_ATE_unsigned)
127 .dwattr $C$DW$T$15, DW_AT_name("unsigned long long")
128 .dwattr $C$DW$T$15, DW_AT_byte_size(0x08)
129
130$C$DW$T$16 .dwtag DW_TAG_base_type
131 .dwattr $C$DW$T$16, DW_AT_encoding(DW_ATE_float)
132 .dwattr $C$DW$T$16, DW_AT_name("float")
133 .dwattr $C$DW$T$16, DW_AT_byte_size(0x04)
134
135$C$DW$T$17 .dwtag DW_TAG_base_type
136 .dwattr $C$DW$T$17, DW_AT_encoding(DW_ATE_float)
137 .dwattr $C$DW$T$17, DW_AT_name("double")
138 .dwattr $C$DW$T$17, DW_AT_byte_size(0x08)
139
140$C$DW$T$18 .dwtag DW_TAG_base_type
141 .dwattr $C$DW$T$18, DW_AT_encoding(DW_ATE_float)
142 .dwattr $C$DW$T$18, DW_AT_name("long double")
143 .dwattr $C$DW$T$18, DW_AT_byte_size(0x08)
144
145 .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C)
146 .dwendtag $C$DW$CU
147
No Assembly Errors, No Assembly Warnings

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PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
Global variable is not referenced in this file:
extern int __MCALL_implicit_state__
== END OF INFO OUTPUT==

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/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_pru_mailbox.object: pru1_pru_mailbox.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_pru_mailbox.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_pru_mailbox.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_pru_mailbox.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h

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PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
==============================================================================
extern void sm_arb_start() is called from 0 sites in this file.
It appears to be inlineable (size = 9 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char sm_arb_state_idle() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (1 times)
__delay_cycles() (2 times)
==============================================================================
static unsigned char sm_arb_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 68 units)
It has 5 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (2 times)
__delay_cycles() (3 times)
==============================================================================
static unsigned char sm_arb_state_2() is called from 0 sites in this file.
It appears to be inlineable (size = 121 units)
It has 9 non-trivial scope blocks nested 5 deep.
It calls these functions:
buslatches_pru0_dataout() (4 times)
__delay_cycles() (6 times)
==============================================================================
static unsigned char sm_arb_state_3() is called from 0 sites in this file.
It appears to be inlineable (size = 102 units)
It has 6 non-trivial scope blocks nested 5 deep.
It calls these functions:
buslatches_pru0_dataout() (2 times)
__delay_cycles() (6 times)
==============================================================================
static unsigned char sm_arb_state_4() is called from 0 sites in this file.
It appears to be inlineable (size = 2 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
extern void sm_arb_start() is called from 0 sites in this file.
It appears to be inlineable (size = 9 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
static unsigned char sm_arb_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 68 units)
It has 5 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (2 times)
__delay_cycles() (3 times)
static unsigned char sm_arb_state_2() is called from 0 sites in this file.
It appears to be inlineable (size = 121 units)
It has 9 non-trivial scope blocks nested 5 deep.
It calls these functions:
buslatches_pru0_dataout() (4 times)
__delay_cycles() (6 times)
static unsigned char sm_arb_state_3() is called from 0 sites in this file.
It appears to be inlineable (size = 102 units)
It has 6 non-trivial scope blocks nested 5 deep.
It calls these functions:
buslatches_pru0_dataout() (2 times)
__delay_cycles() (6 times)
static unsigned char sm_arb_state_4() is called from 0 sites in this file.
It appears to be inlineable (size = 2 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
extern unsigned char sm_arb_state_idle() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (1 times)
__delay_cycles() (2 times)
These functions may be recursive:
sm_arb_state_1()
sm_arb_state_2()
sm_arb_state_3()
sm_arb_state_idle()
These external functions are called but not defined here:
__delay_cycles()
buslatches_pru0_dataout()
==============================================================================
extern unsigned char sm_arb_state_idle() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_4() is called from 0 sites in this file.
It appears to be inlineable (size = 2 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_3() is called from 0 sites in this file.
It appears to be inlineable (size = 102 units)
It has 6 non-trivial scope blocks nested 5 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_2() is called from 0 sites in this file.
It appears to be inlineable (size = 121 units)
It has 9 non-trivial scope blocks nested 5 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 68 units)
It has 5 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void sm_arb_start() is called from 0 sites in this file.
It appears to be inlineable (size = 9 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
extern unsigned char sm_arb_state_idle() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_4() is called from 0 sites in this file.
It appears to be inlineable (size = 2 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_3() is called from 0 sites in this file.
It appears to be inlineable (size = 102 units)
It has 6 non-trivial scope blocks nested 5 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_2() is called from 0 sites in this file.
It appears to be inlineable (size = 121 units)
It has 9 non-trivial scope blocks nested 5 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_arb_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 68 units)
It has 5 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
extern void sm_arb_start() is called from 0 sites in this file.
It appears to be inlineable (size = 9 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
== END OF INFO OUTPUT==

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/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: pru1_statemachine_arbitration.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: pru1_utils.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_cfg.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_ctrl.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: pru1_buslatches.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_arbitration.object: pru1_statemachine_arbitration.h

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PRU C/C++ Optimizer v2.3.1
Build Number 1SGNO-2LI-UASAR-TAR-C08D
==============================================================================
extern void sm_dma_start() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 507 units)
It has 19 non-trivial scope blocks nested 6 deep.
It calls these functions:
iopageregisters_write_w() (1 times)
iopageregisters_write_b() (1 times)
iopageregisters_read() (1 times)
__delay_cycles() (24 times)
buslatches_pru0_dataout() (21 times)
==============================================================================
static unsigned char sm_dma_state_11() is called from 0 sites in this file.
It appears to be inlineable (size = 72 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (1 times)
__delay_cycles() (6 times)
==============================================================================
static unsigned char sm_dma_state_21() is called from 0 sites in this file.
It appears to be inlineable (size = 66 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (3 times)
__delay_cycles() (5 times)
==============================================================================
static unsigned char sm_dma_state_99() is called from 0 sites in this file.
It appears to be inlineable (size = 155 units)
It has 11 non-trivial scope blocks nested 6 deep.
It calls these functions:
buslatches_pru0_dataout() (6 times)
__delay_cycles() (7 times)
extern void sm_dma_start() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
static unsigned char sm_dma_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 507 units)
It has 19 non-trivial scope blocks nested 6 deep.
It calls these functions:
iopageregisters_write_w() (1 times)
iopageregisters_write_b() (1 times)
iopageregisters_read() (1 times)
__delay_cycles() (24 times)
buslatches_pru0_dataout() (21 times)
static unsigned char sm_dma_state_11() is called from 0 sites in this file.
It appears to be inlineable (size = 72 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (1 times)
__delay_cycles() (6 times)
static unsigned char sm_dma_state_21() is called from 0 sites in this file.
It appears to be inlineable (size = 66 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
buslatches_pru0_dataout() (3 times)
__delay_cycles() (5 times)
static unsigned char sm_dma_state_99() is called from 0 sites in this file.
It appears to be inlineable (size = 155 units)
It has 11 non-trivial scope blocks nested 6 deep.
It calls these functions:
buslatches_pru0_dataout() (6 times)
__delay_cycles() (7 times)
These functions may be recursive:
sm_dma_state_1()
sm_dma_state_11()
sm_dma_state_21()
sm_dma_state_99()
These external functions are called but not defined here:
buslatches_pru0_dataout()
__delay_cycles()
iopageregisters_read()
iopageregisters_write_b()
iopageregisters_write_w()
==============================================================================
static unsigned char sm_dma_state_99() is called from 0 sites in this file.
It appears to be inlineable (size = 155 units)
It has 11 non-trivial scope blocks nested 6 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_21() is called from 0 sites in this file.
It appears to be inlineable (size = 66 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_11() is called from 0 sites in this file.
It appears to be inlineable (size = 72 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 507 units)
It has 19 non-trivial scope blocks nested 6 deep.
It calls these functions:
<NONE>
==============================================================================
extern void sm_dma_start() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_99() is called from 0 sites in this file.
It appears to be inlineable (size = 155 units)
It has 11 non-trivial scope blocks nested 6 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_21() is called from 0 sites in this file.
It appears to be inlineable (size = 66 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_11() is called from 0 sites in this file.
It appears to be inlineable (size = 72 units)
It has 4 non-trivial scope blocks nested 4 deep.
It calls these functions:
<NONE>
==============================================================================
static unsigned char sm_dma_state_1() is called from 0 sites in this file.
It appears to be inlineable (size = 507 units)
It has 19 non-trivial scope blocks nested 6 deep.
It calls these functions:
<NONE>
==============================================================================
extern void sm_dma_start() is called from 0 sites in this file.
It appears to be inlineable (size = 30 units)
It has 3 non-trivial scope blocks nested 3 deep.
It calls these functions:
<NONE>
== END OF INFO OUTPUT==

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/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: pru1_statemachine_dma.c
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdint.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/_stdint40.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//include/stdbool.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/iopageregister.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/unibus.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/ddrmem.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: pru1_buslatches.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/10.01_base/2_src/shared/pru_pru_mailbox.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: pru1_utils.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_cfg.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: /home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/pru-software-support-package/include/am335x/pru_ctrl.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: pru1_statemachine_arbitration.h
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1_statemachine_dma.object: pru1_statemachine_dma.h

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