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db0167afe1
PRU1 code split into multiple images 1. test functions 2. UNIBUS operation PRU1 bus latch interface Write byte/bits access not with MACROS (random optimizer influence), now with *_helper() procedures. Same timing, more determinism, much code saving. Nono more ASM code to write PRU0 XFER area. demo: menu to test UNIBUS signals directly rework "Arbitration" logic: now 3-fold Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER - no Arbitrator (SACK penidng for 11/34 Konsole) (NONE) - phyiscal PDP_11 CPU is Arbitrator (CLIENT) - UniBone implements Arbitrator (MASTER) - Same PRU code loop handles all arbitration types PRU buslatch timing slower, for some problematic PCBs More aggressive bus latch selftest (mixed patterns, running on PRU now) Refinement of ready-to-run scripts - Adapted to changed "demo" menu - new name scheme <OS>_<boot- drive>_<PDP-11CPU> indicates - which OS is run - which disk emulation is used and what is the boot device - what is the (minimum) PDP-11 to run that Merged in Joshs DMA timing for 11/84 UNIBUS master cycles waits 350 us before MSYN, instead 150. Merged in Joshs DMA request queue multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially Merged in Joshs MSCP driver - Build RT-11v5.5 for MSCP - added boot loader "du.lst" MSCP run scrips 2.11BSD on MSCP on PDP-11/44 RT11 on MSCP Fix: image file sizing Disk image file exptend automatically if block beyond current file end is written
114 lines
7.1 KiB
Plaintext
114 lines
7.1 KiB
Plaintext
1 .title M9312 'DU' BOOT prom for MSCP compatible controller
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2
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3 ; This source code is a mdified copy of the DEC M9312 23-767A9 boot PROM.
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4 ;
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5 ; This boot PROM is for any MSCP compatible controller (DEC UDA50, EMULEX UC17/UC18).
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6 ;
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7 ; Multiple units and/or CSR addresses are supported via different entry points.
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8
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9 ;
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10 ; Revision history:
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11 ; May 2017: Joerg Hoppe
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12 ;
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13 ; 198?: DEC
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14 ; Original ROM 23-767A9 for M9312.
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15 ;
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16
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17
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18
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19 172150 mscsr =172150 ; std MSCP csrbase
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20
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21 000000 msip =+0 ; IP register
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22 000002 mssa =+2 ; SA register
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23
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24 .asect
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25 010000 .=10000 ; arbitrary position > 3000
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26
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27 ; --------------------------------------------------
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28 001004 rpkt =1004 ; rpkt structure
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29 001070 cpkt =1070 ; cpkt structure
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30 001200 comm =1200 ; comm structure
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31 ;comm =2404 ; comm structure (at 'blt .+12')
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32
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33 ; register usage:
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34 ; r0: unit number 0..3
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35 ; r1: MSCP csrbase
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36 ; r2: moving buffer pointer
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37 ; r3: moving buffer pointer
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38 ; r5: init mask
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39
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40 ; 4 unit numbers => 4 entry addresses
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41 start0:
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42 010000 012700 000000 mov #0,r0
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43 010004 000413 br duNr
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44 010006 000240 nop
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45 start1:
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46 010010 012700 000001 mov #1,r0
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47 010014 000407 br duNr
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48 010016 000240 nop
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49 start2:
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50 010020 012700 000002 mov #2,r0
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51 010024 000403 br duNr
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52 010026 000240 nop
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53 start3:
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54 010030 012700 000003 mov #3,r0
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55
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56 ; retry entry
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57 010034 012701 172150 duNr: mov #mscsr,r1 ; boot std csr, unit <R0>
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58
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59 010040 010021 go: mov r0,(r1)+ ; init controller (write IP), bump ptr
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60 010042 012705 004000 mov #4000,r5 ; S1 state bitmask
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61 010046 012703 010166 mov #mscpdt,r3 ; point to data
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62
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63 ; write 4 init words, with r5 mask from 4000 to 40000
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64 010052 005711 3$: tst (r1) ; error bit set ?
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65 010054 100767 bmi duNr ; yes, fail back to begin to retry
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66 010056 031105 bit (r1),r5 ; step bit set ?
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67 010060 001774 beq 3$ ; not yet, wait loop
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68 010062 012311 mov (r3)+,(r1) ; yes, send next init data
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69 010064 006305 asl r5 ; next mask
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70 010066 100371 bpl 3$ ; s4 done? br if not yet
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71
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72 010070 005002 4$: clr r2 ; set bufptr to 0
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73 010072 005022 5$: clr (r2)+ ; clear buffer [0..2403]
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74 010074 020227 001200 cmp r2,#comm ; check for end of buffer
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75 010100 001374 bne 5$ ; loop if not done
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76
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77 010102 010237 001064 mov r2,@#cpkt-4 ; set lnt -- R2=2404
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78 010106 112337 001100 movb (r3)+,@#cpkt+10 ; set command
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79 010112 111337 001105 movb (r3),@#cpkt+15 ; set bytecnt(hi)
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80 010116 010037 001074 mov r0,@#cpkt+4 ; set unit
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81 010122 012722 001004 mov #rpkt,(r2)+ ; rq desc addr
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82 010126 010522 mov r5,(r2)+ ; rq own bit15
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83 010130 012722 001070 mov #cpkt,(r2)+ ; cp desc addr
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84 010134 010522 mov r5,(r2)+ ; cq own bit15
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85 010136 016102 177776 mov -2(r1),r2 ; wake controller (read IP)
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86
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87 010142 005737 001202 6$: tst @#comm+2 ; rq own controller ?
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88 010146 100775 bmi 6$ ; loop if not done
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89
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90 010150 105737 001016 tstb @#rpkt+12 ; check for error ?
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91 010154 001327 bne duNr ; yup, fail back to begin to retry
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92
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93 010156 105723 tstb (r3)+ ; check end of table ?
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94 010160 001743 beq 4$ ; br if not yet
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95
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96 010162 005041 clr -(r1) ; init controller (write IP)
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97 010164 005007 clr pc ; jmp to bootstrap at zero
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98
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99 ; MSCP init and command data
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100 ; pointed to by r3
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101 mscpdt:
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102 010166 100000 .word 100000 ; S1: 100000 = no int, ring size 1, no vector
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103 010170 001200 .word comm ; S2: 002404 = ringbase lo addr
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104 010172 000000 .word 000000 ; S3: 000000 = no purge/poll, ringbase hi addr
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105 010174 000001 .word 000001 ; S4: 000001 = go bit
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106 ;
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107 ; MSCP command data
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108 ;
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109 010176 011 000 .byte 011,000 ; cmd=011(online), bytecnt_hi=000(0)
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110 010200 041 002 .byte 041,002 ; cmd=041(read), bytecnt_hi=002(512)
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111
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112 .end
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112
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