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db0167afe1
PRU1 code split into multiple images 1. test functions 2. UNIBUS operation PRU1 bus latch interface Write byte/bits access not with MACROS (random optimizer influence), now with *_helper() procedures. Same timing, more determinism, much code saving. Nono more ASM code to write PRU0 XFER area. demo: menu to test UNIBUS signals directly rework "Arbitration" logic: now 3-fold Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER - no Arbitrator (SACK penidng for 11/34 Konsole) (NONE) - phyiscal PDP_11 CPU is Arbitrator (CLIENT) - UniBone implements Arbitrator (MASTER) - Same PRU code loop handles all arbitration types PRU buslatch timing slower, for some problematic PCBs More aggressive bus latch selftest (mixed patterns, running on PRU now) Refinement of ready-to-run scripts - Adapted to changed "demo" menu - new name scheme <OS>_<boot- drive>_<PDP-11CPU> indicates - which OS is run - which disk emulation is used and what is the boot device - what is the (minimum) PDP-11 to run that Merged in Joshs DMA timing for 11/84 UNIBUS master cycles waits 350 us before MSYN, instead 150. Merged in Joshs DMA request queue multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially Merged in Joshs MSCP driver - Build RT-11v5.5 for MSCP - added boot loader "du.lst" MSCP run scrips 2.11BSD on MSCP on PDP-11/44 RT11 on MSCP Fix: image file sizing Disk image file exptend automatically if block beyond current file end is written
92 lines
2.0 KiB
Plaintext
92 lines
2.0 KiB
Plaintext
.title M9312 'DL' BOOT prom for RL11 controller
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; This source code is a modified copy of the DEC M9312 23-751A9 boot PROM.
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;
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; This boot PROM is for the RL11 controller with RL01/RL02 drives.
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;
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; Multiple units and/or CSR addresses are supported via different entry points.
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;
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rlcsr =174400 ; std RL11 csrbase
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rlcs =+0 ; control/status
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rlba =+2 ; bus address
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rlda =+4 ; disk address
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rlmp =+6 ; multipurpose
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cmstat =2*2 ; get status
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cmseek =3*2 ; seek
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cmrdhd =4*2 ; read header
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cmrdda =6*2 ; read data
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.asect
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.=10000 ; arbitrary position > 3000
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; --------------------------------------------------
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start:
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; 4 unit numbers => 4 entry addresses
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start0:
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mov #0,r0
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br dlnr
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nop
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start1:
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mov #1,r0
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br dlnr
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nop
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start2:
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mov #2,r0
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br dlnr
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nop
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start3:
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mov #3,r0
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dlnr:
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mov #rlcsr,r1 ; boot std csr, unit <R0>
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; --------------------------------------------------
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mov r0,r3 ; save unit number
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swab r3 ; unit number in upper byte
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mov r3,(r1) ; set unit, NOP cmd
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mov #013,rlda(r1) ; subcmd reset+getstatus
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bis #cmstat,r3 ; get status cmd (r3lo is 0)
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mov r3,(r1) ; execute
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1$: tstb (r1) ; test for ready
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bpl 1$ ; wait
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clrb r3 ; unit number in upper byte
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bis #cmrdhd,r3 ; read header cmd
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mov r3,(r1) ; execute
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2$: tstb (r1) ; test for ready
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bpl 2$ ; wait
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mov rlmp(r1),r2 ; retrieve cyl/head/sector
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bic #77,r2 ; set sector to zero
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inc r2 ; set head 0, seek to cyl 0
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mov r2,rlda(r1) ; into da for seek
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clrb r3 ; unit number in upper byte
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bis #cmseek,r3 ; seek cmd
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mov r3,(r1) ; execute
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3$: tstb (r1) ; test for ready
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bpl 3$ ; wait
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clr rlda(r1) ; select cyl0/head0/sector0
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mov #-512.,rlmp(r1) ; set word count
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clrb r3 ; unit number in upper byte
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bis #cmrdda,r3 ; read data cmd
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mov r3,(r1) ; execute
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4$: tstb (r1) ; test for ready
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bpl 4$ ; wait
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tst (r1) ; test for error
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bpl 5$ ; br if ok
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reset ; ERROR - reset the world
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br dlnr ; retry. r0 unchanged
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5$: bic #377,(r1) ; execute nop cmd
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clr pc ; jump to bootstrap at zero
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.end
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