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db0167afe1
PRU1 code split into multiple images 1. test functions 2. UNIBUS operation PRU1 bus latch interface Write byte/bits access not with MACROS (random optimizer influence), now with *_helper() procedures. Same timing, more determinism, much code saving. Nono more ASM code to write PRU0 XFER area. demo: menu to test UNIBUS signals directly rework "Arbitration" logic: now 3-fold Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER - no Arbitrator (SACK penidng for 11/34 Konsole) (NONE) - phyiscal PDP_11 CPU is Arbitrator (CLIENT) - UniBone implements Arbitrator (MASTER) - Same PRU code loop handles all arbitration types PRU buslatch timing slower, for some problematic PCBs More aggressive bus latch selftest (mixed patterns, running on PRU now) Refinement of ready-to-run scripts - Adapted to changed "demo" menu - new name scheme <OS>_<boot- drive>_<PDP-11CPU> indicates - which OS is run - which disk emulation is used and what is the boot device - what is the (minimum) PDP-11 to run that Merged in Joshs DMA timing for 11/84 UNIBUS master cycles waits 350 us before MSYN, instead 150. Merged in Joshs DMA request queue multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially Merged in Joshs MSCP driver - Build RT-11v5.5 for MSCP - added boot loader "du.lst" MSCP run scrips 2.11BSD on MSCP on PDP-11/44 RT11 on MSCP Fix: image file sizing Disk image file exptend automatically if block beyond current file end is written
113 lines
2.6 KiB
Plaintext
113 lines
2.6 KiB
Plaintext
.title M9312 'DU' BOOT prom for MSCP compatible controller
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; This source code is a mdified copy of the DEC M9312 23-767A9 boot PROM.
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;
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; This boot PROM is for any MSCP compatible controller (DEC UDA50, EMULEX UC17/UC18).
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;
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; Multiple units and/or CSR addresses are supported via different entry points.
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;
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; Revision history:
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; May 2017: Joerg Hoppe
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;
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; 198?: DEC
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; Original ROM 23-767A9 for M9312.
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;
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mscsr =172150 ; std MSCP csrbase
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msip =+0 ; IP register
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mssa =+2 ; SA register
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.asect
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.=10000 ; arbitrary position > 3000
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; --------------------------------------------------
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rpkt =1004 ; rpkt structure
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cpkt =1070 ; cpkt structure
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comm =1200 ; comm structure
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;comm =2404 ; comm structure (at 'blt .+12')
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; register usage:
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; r0: unit number 0..3
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; r1: MSCP csrbase
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; r2: moving buffer pointer
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; r3: moving buffer pointer
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; r5: init mask
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; 4 unit numbers => 4 entry addresses
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start0:
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mov #0,r0
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br duNr
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nop
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start1:
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mov #1,r0
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br duNr
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nop
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start2:
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mov #2,r0
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br duNr
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nop
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start3:
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mov #3,r0
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; retry entry
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duNr: mov #mscsr,r1 ; boot std csr, unit <R0>
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go: mov r0,(r1)+ ; init controller (write IP), bump ptr
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mov #4000,r5 ; S1 state bitmask
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mov #mscpdt,r3 ; point to data
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; write 4 init words, with r5 mask from 4000 to 40000
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3$: tst (r1) ; error bit set ?
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bmi duNr ; yes, fail back to begin to retry
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bit (r1),r5 ; step bit set ?
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beq 3$ ; not yet, wait loop
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mov (r3)+,(r1) ; yes, send next init data
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asl r5 ; next mask
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bpl 3$ ; s4 done? br if not yet
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4$: clr r2 ; set bufptr to 0
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5$: clr (r2)+ ; clear buffer [0..2403]
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cmp r2,#comm ; check for end of buffer
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bne 5$ ; loop if not done
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mov r2,@#cpkt-4 ; set lnt -- R2=2404
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movb (r3)+,@#cpkt+10 ; set command
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movb (r3),@#cpkt+15 ; set bytecnt(hi)
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mov r0,@#cpkt+4 ; set unit
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mov #rpkt,(r2)+ ; rq desc addr
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mov r5,(r2)+ ; rq own bit15
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mov #cpkt,(r2)+ ; cp desc addr
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mov r5,(r2)+ ; cq own bit15
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mov -2(r1),r2 ; wake controller (read IP)
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6$: tst @#comm+2 ; rq own controller ?
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bmi 6$ ; loop if not done
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tstb @#rpkt+12 ; check for error ?
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bne duNr ; yup, fail back to begin to retry
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tstb (r3)+ ; check end of table ?
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beq 4$ ; br if not yet
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clr -(r1) ; init controller (write IP)
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clr pc ; jmp to bootstrap at zero
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; MSCP init and command data
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; pointed to by r3
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mscpdt:
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.word 100000 ; S1: 100000 = no int, ring size 1, no vector
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.word comm ; S2: 002404 = ringbase lo addr
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.word 000000 ; S3: 000000 = no purge/poll, ringbase hi addr
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.word 000001 ; S4: 000001 = go bit
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;
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; MSCP command data
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;
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.byte 011,000 ; cmd=011(online), bytecnt_hi=000(0)
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.byte 041,002 ; cmd=041(read), bytecnt_hi=002(512)
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.end
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