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6f1b4767164c31a6798194e91ef8f51b2cb2b4de
livingcomputermuseum.UniBone/10.01_base/2_src/shared
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Josh Dersch 6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait). 
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
2019-08-16 02:23:32 +02:00
..
ddrmem.h
Fix GitHub repository
2019-08-05 08:37:03 +02:00
iopageregister.h
Fix GitHub repository
2019-08-05 08:37:03 +02:00
mailbox.h
Fix GitHub repository
2019-08-05 08:37:03 +02:00
pru_pru_mailbox.h
Fix GitHub repository
2019-08-05 08:37:03 +02:00
tuning.h
Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait).
2019-08-16 02:23:32 +02:00
unibus.h
Fix GitHub repository
2019-08-05 08:37:03 +02:00
update_pru_config.sh
Initial
2019-04-05 11:30:26 +02:00