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db0167afe1
PRU1 code split into multiple images 1. test functions 2. UNIBUS operation PRU1 bus latch interface Write byte/bits access not with MACROS (random optimizer influence), now with *_helper() procedures. Same timing, more determinism, much code saving. Nono more ASM code to write PRU0 XFER area. demo: menu to test UNIBUS signals directly rework "Arbitration" logic: now 3-fold Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER - no Arbitrator (SACK penidng for 11/34 Konsole) (NONE) - phyiscal PDP_11 CPU is Arbitrator (CLIENT) - UniBone implements Arbitrator (MASTER) - Same PRU code loop handles all arbitration types PRU buslatch timing slower, for some problematic PCBs More aggressive bus latch selftest (mixed patterns, running on PRU now) Refinement of ready-to-run scripts - Adapted to changed "demo" menu - new name scheme <OS>_<boot- drive>_<PDP-11CPU> indicates - which OS is run - which disk emulation is used and what is the boot device - what is the (minimum) PDP-11 to run that Merged in Joshs DMA timing for 11/84 UNIBUS master cycles waits 350 us before MSYN, instead 150. Merged in Joshs DMA request queue multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially Merged in Joshs MSCP driver - Build RT-11v5.5 for MSCP - added boot loader "du.lst" MSCP run scrips 2.11BSD on MSCP on PDP-11/44 RT11 on MSCP Fix: image file sizing Disk image file exptend automatically if block beyond current file end is written
85 lines
4.6 KiB
Plaintext
85 lines
4.6 KiB
Plaintext
1 .title M9312 'DK/DT' BOOT prom for RK03/05 and TU55/56 controllers
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2
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3 ; This source code is a modified copy of the DEC M9312 23-756A9 boot PROM.
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4 ;
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5 ; This boot PROM is for the RK03/05 DECdisk controllers.
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6 ;
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7 ; Multiple units and/or CSR addresses are supported via different entry points.
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8
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9 177400 rkcsr =177400 ; std RK03/05 DECdisk csrbase
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10
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11 000002 rkwc =+6-4 ; word count
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12 000006 rkda =+12-4 ; disk address
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13
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14 000002 xxwc =rkwc ; common word count offset
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15
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16 .asect
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17 010000 .=10000
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18
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19 ; --------------------------------------------------
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20
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21 start:
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22 ; 8 unit numbers => 8 entry addresses
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23 start0:
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24 010000 012700 000000 mov #0,r0
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25 010004 000435 br dknr
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26 010006 000240 nop
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27 start1:
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28 010010 012700 000001 mov #1,r0
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29 010014 000431 br dknr
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30 010016 000240 nop
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31 start2:
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32 010020 012700 000002 mov #2,r0
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33 010024 000425 br dknr
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34 010026 000240 nop
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35 start3:
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36 010030 012700 000003 mov #3,r0
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37 010034 000421 br dknr
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38 010036 000240 nop
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39 start4:
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40 010040 012700 000004 mov #4,r0
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41 010044 000415 br dknr
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42 010046 000240 nop
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43 start5:
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44 010050 012700 000005 mov #5,r0
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45 010054 000411 br dknr
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46 010056 000240 nop
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47 start6:
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48 010060 012700 000006 mov #6,r0
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49 010064 000405 br dknr
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50 010066 000240 nop
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51 start7:
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52 010070 012700 000007 mov #7,r0
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53 010074 000401 br dknr
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54 010076 000240 nop
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55
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56
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57 dknr:
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58 010100 012701 177404 mov #rkcsr+4,r1 ; boot std csr, unit <R0>
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59
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60 010104 010003 mov r0,r3 ; get unit number
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61 010106 000241 clc ; C=0 for ror
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62 010110 006003 ror r3 ; shift into 15:12
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63 010112 006003 ror r3 ;
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64 010114 006003 ror r3 ;
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65 010116 006003 ror r3 ;
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66 010120 010361 000006 mov r3,rkda(r1) ; unit number, sector 0 to disk addr
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67
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68 010124 012761 177000 000002 mov #-512.,xxwc(r1) ; set word count
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69 010132 052703 000005 bis #5,r3 ; command READ+GO
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70 010136 010311 mov r3,(r1) ; execute
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71 010140 105711 2$: tstb (r1) ; test ready
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72 010142 100376 bpl 2$ ; loop
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73
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74 010144 005711 tst (r1) ; check error
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75 010146 100002 bpl 3$ ; br if no error
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76
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77 010150 000005 reset ; reset the world
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78 010152 000752 br dknr ; and retry
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79
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80 010154 042711 000377 3$: bic #377,(r1) ; nop command
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81 010160 005007 clr pc ; jump to loaded boot sector
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82
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83 .end
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83
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