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PRU1 code split into multiple images 1. test functions 2. UNIBUS operation PRU1 bus latch interface Write byte/bits access not with MACROS (random optimizer influence), now with *_helper() procedures. Same timing, more determinism, much code saving. Nono more ASM code to write PRU0 XFER area. demo: menu to test UNIBUS signals directly rework "Arbitration" logic: now 3-fold Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER - no Arbitrator (SACK penidng for 11/34 Konsole) (NONE) - phyiscal PDP_11 CPU is Arbitrator (CLIENT) - UniBone implements Arbitrator (MASTER) - Same PRU code loop handles all arbitration types PRU buslatch timing slower, for some problematic PCBs More aggressive bus latch selftest (mixed patterns, running on PRU now) Refinement of ready-to-run scripts - Adapted to changed "demo" menu - new name scheme <OS>_<boot- drive>_<PDP-11CPU> indicates - which OS is run - which disk emulation is used and what is the boot device - what is the (minimum) PDP-11 to run that Merged in Joshs DMA timing for 11/84 UNIBUS master cycles waits 350 us before MSYN, instead 150. Merged in Joshs DMA request queue multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially Merged in Joshs MSCP driver - Build RT-11v5.5 for MSCP - added boot loader "du.lst" MSCP run scrips 2.11BSD on MSCP on PDP-11/44 RT11 on MSCP Fix: image file sizing Disk image file exptend automatically if block beyond current file end is written
183 lines
4.4 KiB
C++
183 lines
4.4 KiB
C++
/*
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uda.hpp: MSCP controller port (UDA50)
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Copyright Vulcan Inc. 2019 via Living Computers: Museum + Labs, Seattle, WA.
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Contributed under the BSD 2-clause license.
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*/
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#pragma once
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#include <memory>
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#include "utils.hpp"
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#include "unibusdevice.hpp"
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#include "storagecontroller.hpp"
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#include "mscp_server.hpp"
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#include "mscp_drive.hpp"
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// The number of drives supported by the controller.
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// This is arbitrarily fixed at 8 but could be set to any
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// value up to 65535.
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#define DRIVE_COUNT 8
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// The control/microcode version info returned by SA in the fourth intialization step.
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// This indicates a UDA50 controller, which makes RSTS happy.
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#define UDA50_ID 0x4063
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// The maximum message length we can handle. This is provided as a sanity check
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// to prvent parsing clearly invalid commands.
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#define MAX_MESSAGE_LENGTH 0x1000
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// TODO: this currently assumes a little-endian machine!
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#pragma pack(push,1)
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struct Message
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{
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uint16_t MessageLength;
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union
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{
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struct
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{
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uint16_t Credits : 4;
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uint16_t MessageType : 4;
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uint16_t ConnectionID : 8;
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} Info;
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uint16_t Word1;
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} Word1;
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uint8_t Message[sizeof(ControlMessageHeader)];
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};
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#pragma pack(pop)
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/*
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This implements the Transport layer for a Unibus MSCP controller.
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Logic for initialization, reset, and communcation with the MSCP Server
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is implemented here.
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*/
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class uda_c : public storagecontroller_c
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{
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public:
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uda_c();
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virtual ~uda_c();
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void worker(void) override;
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void on_after_register_access(
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unibusdevice_register_t *device_reg,
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uint8_t unibus_control) override;
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void on_power_changed(void) override;
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void on_init_changed(void) override;
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void on_drive_status_changed(storagedrive_c *drive) override;
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public:
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//
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// Returns the next command message from the command ring, if any.
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// Returns NULL if the ring is empty.
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//
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Message* GetNextCommand(void);
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//
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// Posts a response message to the response ring and memory
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// if there is space.
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// Returns FALSE if the ring is full.
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bool PostResponse(Message* response);
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uint32_t GetControllerIdentifier(void);
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uint16_t GetControllerClassModel(void);
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uint32_t GetDriveCount(void);
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mscp_drive_c* GetDrive(uint32_t driveNumber);
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private:
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// TODO: consolidate these private/public groups here
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void Reset(void);
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void Interrupt(void);
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uint32_t GetCommandDescriptorAddress(size_t index);
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uint32_t GetResponseDescriptorAddress(size_t index);
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public:
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bool DMAWriteWord(uint32_t address, uint16_t word);
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uint16_t DMAReadWord(uint32_t address, bool& success);
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bool DMAWrite(uint32_t address, size_t lengthInBytes, uint8_t* buffer);
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uint8_t* DMARead(uint32_t address, size_t lengthInBytes, size_t bufferSize);
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private:
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void update_SA(uint16_t value);
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// UDA50 registers:
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unibusdevice_register_t *IP_reg;
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unibusdevice_register_t *SA_reg;
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std::shared_ptr<mscp_server> _server;
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uint32_t _ringBase;
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// Lengths are in terms of slots (32 bits each) in the
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// corresponding rings.
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size_t _commandRingLength;
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size_t _responseRingLength;
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// The current slot in the ring being accessed.
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uint32_t _commandRingPointer;
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uint32_t _responseRingPointer;
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// Interrupt vector -- if zero, no interrupts
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// will be generated.
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uint32_t _interruptVector;
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// Interrupt enable flag
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bool _interruptEnable;
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// Purge interrupt enable flag
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bool _purgeInterruptEnable;
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// Value written during step1, saved
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// to make manipulation easier.
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uint16_t _step1Value;
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enum InitializationStep
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{
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Uninitialized = 0,
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Step1 = 1,
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Step2 = 2,
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Step3 = 4,
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Step4 = 8,
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Complete,
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};
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volatile InitializationStep _initStep;
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volatile bool _next_step;
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void StateTransition(InitializationStep nextStep);
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// TODO: this currently assumes a little-endian machine!
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#pragma pack(push,1)
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struct Descriptor
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{
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union
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{
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uint16_t Word0;
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uint16_t EnvelopeLow;
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} Word0;
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union
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{
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uint16_t Word1;
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struct
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{
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uint16_t EnvelopeHigh : 2;
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uint16_t Reserved : 12;
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uint16_t Flag : 1;
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uint16_t Ownership : 1;
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} Fields;
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} Word1;
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};
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#pragma pack(pop)
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};
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