mirror of
https://github.com/livingcomputermuseum/cpus-pdp8.git
synced 2026-01-22 10:41:24 +00:00
debugging
This commit is contained in:
brad
parent
efc438f11d
commit
8a2da8d778
@ -7,22 +7,23 @@ module ide_disk(clk, reset,
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ide_lba, ide_read_req, ide_write_req,
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ide_error, ide_done,
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buffer_addr, buffer_rd, buffer_wr,
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buffer_in, buffer_out);
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buffer_in, buffer_out,
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ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
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input clk;
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input reset;
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input [24:0] ide_lba;
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input [23:0] ide_lba;
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input ide_read_req;
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input ide_write_req;
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output ide_error;
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output ide_done;
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output [7:0] buffer_addr;
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output buffer_rd;
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output buffer_wr;
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output reg [7:0] buffer_addr;
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output reg buffer_rd;
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output reg buffer_wr;
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output reg [11:0] buffer_out;
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output [11:0] buffer_in;
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output [11:0] buffer_out;
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parameter [4:0]
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ready = 5'd0,
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@ -87,8 +88,18 @@ module ide_disk(clk, reset,
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output [1:0] ide_cs;
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output [2:0] ide_da;
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//
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reg [4:0] ide_state;
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reg [4:0] ide_state_next;
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reg [7:0] offset;
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reg [7:0] wc;
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reg err;
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reg done;
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reg set_done, clear_done;
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reg set_err, clear_err;
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reg inc_offset;
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//
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ide ide1(.clk(clk), .reset(reset),
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@ -99,16 +110,20 @@ module ide_disk(clk, reset,
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.ide_cs(ide_cs), .ide_da(ide_da));
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//
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wire [23:0] lba = ide_lba;
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wire start = ide_read_req | ide_write_req;
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wire [23:0] lba;
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wire start;
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assign lba = ide_lba;
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assign start = ide_read_req | ide_write_req;
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assign ide_done = done;
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//
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alway @(posedge clk)
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always @(posedge clk)
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if (reset)
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begin
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err <= 1'b0;
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done <= 1'b1;
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done <= 1'b0;
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offset <= 0;
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wc <= 0;
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end
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@ -142,6 +157,8 @@ module ide_disk(clk, reset,
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else
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begin
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ide_state <= ide_state_next;
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//if (ide_state_next != ready)
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//$display("ide_state %d", ide_state_next);
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end
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always @(ide_state or lba or start or
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@ -150,8 +167,6 @@ module ide_disk(clk, reset,
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begin
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ide_state_next = ide_state;
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assert_int = 0;
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set_err = 0;
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clear_err = 0;
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@ -176,13 +191,13 @@ module ide_disk(clk, reset,
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if (start)
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begin
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ide_state_next = init0;
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clear_done = 1;
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$display("ide_disk: XXX go!");
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end
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end
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init0:
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begin
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clear_done = 1;
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ata_addr = ATA_STATUS;
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ata_rd = 1;
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if (ata_done &&
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@ -335,15 +350,15 @@ module ide_disk(clk, reset,
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begin
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//buffer write
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buffer_addr = offset;
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buffer_out = ata_out;
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buffer_out = ata_out[11:0];
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if (0) $display("read1: XXX ata_out %o, buffer_addr %o",
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ata_out, buffer_addr);
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buffer_wr = 1;
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inc_offset = 1;
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// inc_offset = 1;
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if (wc == 16'h0000)
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if (wc == 8'hff)
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ide_state_next = last0;
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else
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// if (wc == 16'hff00)
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@ -358,14 +373,14 @@ module ide_disk(clk, reset,
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buffer_addr = offset;
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buffer_rd = 1;
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ata_in = dma_data_in;
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ata_in = {4'b0, buffer_in};
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inc_offset = 1;
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ide_state_next = write1;
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end
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write1:
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begin
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if (wc == 0)
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if (wc == 9'hff)
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ide_state_next = last0;
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else
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// if (wc == 16'hff00)
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@ -399,6 +414,7 @@ module ide_disk(clk, reset,
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last3:
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begin
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clear_done = 1;
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ide_state_next = ready;
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$display("ide_disk: XXX last3, done");
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end
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127
rtl/pdp8_rf.v
127
rtl/pdp8_rf.v
@ -1,6 +1,8 @@
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/*
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RF08
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RF08 Emulation using IDE disk
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RF08 Sizes:
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2048 words/track 11 bits
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128 tracks 7 bits
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4 disks 2 bits
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@ -12,7 +14,7 @@
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ddtttttttwwwwwwwwwww
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ema 876543210
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mapped to IDE drive;
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mapping RF08 to IDE disk drive
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2048 x 12 bits -> 2048 x 16 bits = 8 blocks of 512 bytes
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each track is 8 blocks
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each disk is (128 * 8) = 1024 blocks
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@ -23,18 +25,18 @@
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ema bits 7 & 8 select which rs08 disk
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ema bits 6 - 0 select disk head (track #)
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dma contains lower disk word address
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dma contains lower disk word address (offset into block)
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writes to dma trigger; adc is asserted after match w/disk
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writes to dma trigger i/o; adc is asserted after match w/disk
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-------------
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memory:
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PDP-8 memory:
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7750 word count
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7751 current address
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iot:
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PDP-8 IOT's:
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660x
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661x
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@ -87,15 +89,16 @@
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6646 DMMT Maintenance
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uses 3 cycle data break
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Real RF08 uses 3 cycle data break
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ac 8:0, ac 10:0 => 20 bit {EMA,DMA}
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20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 }
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ac 8:0, ac 10:0 => 20 bit {EMA,DMA}
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20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 }
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status
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EIE = WLS | DRL | NXD | PER
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*/
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// EIE = WLS | DRL | NXD | PER
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/*
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3 cycle data break
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@ -127,6 +130,9 @@ requested when the data transfer is completed and the service routine
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will process the information.
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----------- ----------- ----------- -----------
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*/
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/*
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HIGH LEVEL DISK STATE MACHINE:
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@ -358,7 +364,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
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io_data_in, io_data_out, io_select, io_selected,
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io_data_avail, io_interrupt, io_skip,
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ram_read_req, ram_write_req, ram_done,
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ram_ma, ram_in, ram_out);
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ram_ma, ram_in, ram_out,
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ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
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input clk, reset, iot;
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input [11:0] io_data_in;
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@ -379,6 +386,14 @@ module pdp8_rf(clk, reset, iot, state, mb,
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output [11:0] ram_out;
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output [14:0] ram_ma;
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output ide_dior;
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output ide_diow;
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output [1:0] ide_cs;
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output [2:0] ide_da;
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inout [15:0] ide_data_bus;
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// -------------------------------------------------------
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parameter [3:0]
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F0 = 4'b0000,
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F1 = 4'b0001,
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@ -463,7 +478,8 @@ module pdp8_rf(clk, reset, iot, state, mb,
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wire ide_read_req;
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wire ide_write_req;
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wire ide_done;
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wire ide_error;
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//
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assign io_interrupt = (CIE & db_done) ||
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(PIE & PCA) ||
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@ -474,16 +490,62 @@ module pdp8_rf(clk, reset, iot, state, mb,
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assign buffer_matches_DMA = buffer_disk_addr[19:8] == disk_addr[19:8];
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assign buffer_addr = disk_addr[7:0];
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assign ide_done = 1;
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//
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// sector buffer
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//
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wire ide_active;
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wire [7:0] buff_addr;
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wire [11:0] buff_in;
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wire [11:0] buff_out;
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wire buff_rd;
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wire buff_wr;
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wire [7:0] ide_buffer_addr;
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wire [23:0] ide_block_number;
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wire [11:0] ide_buffer_in;
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wire [11:0] ide_buffer_out;
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// ide sector buffer
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ram_256x12 buffer(.A(buffer_addr),
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.DI(buffer_hold),
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.DO(buffer_out),
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.CE_N(1'b0),
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.WE_N(~buffer_wr));
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ram_256x12 buffer(.A(buff_addr),
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.DI(buff_in),
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.DO(buff_out),
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.CE_N(~buff_rd),
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.WE_N(~buff_wr));
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assign ide_active = ide_read_req | ide_write_req;
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// combinatorial
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assign buff_addr = ide_active ? ide_buffer_addr : buffer_addr;
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assign buff_in = ide_active ? ide_buffer_out : buffer_hold;
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assign buff_out = ide_active ? ide_buffer_in : buffer_out;
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assign buff_rd = ide_active ? ide_buffer_rd : 1'b1;
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assign buff_wr = ide_active ? ide_buffer_wr : buffer_wr;
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// ide disk
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ide_disk disk(.clk(clk),
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.reset(reset),
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.ide_lba(ide_block_number),
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.ide_read_req(ide_read_req),
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.ide_write_req(ide_write_req),
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.ide_error(ide_error),
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.ide_done(ide_done),
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.buffer_addr(ide_buffer_addr),
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.buffer_rd(ide_buffer_rd),
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.buffer_wr(ide_buffer_wr),
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.buffer_in(ide_buffer_in),
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.buffer_out(ide_buffer_out),
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.ide_data_bus(ide_data_bus),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da));
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assign ide_block_number = { 12'b0, disk_addr[19:8] };
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//
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// RF controller
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//
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// combinatorial logic
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always @(state or
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ADC or DRL or PER or WLS or NXD or DCF)
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begin
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@ -499,7 +561,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
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6'o60:
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begin
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io_selected = 1'b1;
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case (mb[2:0])
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case (mb[2:0] )
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3'o3: // DMAR
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begin
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io_data_out = 0;
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@ -653,14 +715,9 @@ module pdp8_rf(clk, reset, iot, state, mb,
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end // if (iot)
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// F2:
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// begin
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// if (io_interrupt)
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// $display("iot2 %t, reset io_interrupt", $time);
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//
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// // sampled during f0
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// io_interrupt <= 0;
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// end
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F2:
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begin
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end
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// F3 is a convenient time to do this
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// note that state machine waits when done till next F2
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@ -676,7 +733,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
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endcase // case(state)
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// comb logic for next state
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// comb logic to create 'next state'
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always @(*)
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begin
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db_next_state = DB_idle;
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@ -734,6 +791,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
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db_next_state = ide_done ?
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(is_read ? DB_check_xfer_read:DB_check_xfer_write) :
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DB_read_new_page;
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DB_write_old_page:
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db_next_state = ide_done ? DB_read_new_page : DB_write_old_page;
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@ -816,12 +874,11 @@ module pdp8_rf(clk, reset, iot, state, mb,
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buffer_dirty <= 0;
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buffer_disk_addr[19:8] <= disk_addr[19:8];
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end
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endcase // case (db_state)
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end // else: !if(reset)
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endcase
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end
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//
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// external ram control
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// external ram control (for dma to/from pdp-8 memory)
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//
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assign ram_ma =
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db_state == DB_start_xfer1 ? WC_ADDR :
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@ -853,13 +910,14 @@ module pdp8_rf(clk, reset, iot, state, mb,
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assign buffer_wr = db_state == DB_check_xfer_write && buffer_matches_DMA;
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assign ide_read_req = db_state == DB_read_new_page;
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assign ide_write = db_state == DB_write_old_page;
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assign ide_write_req = db_state == DB_write_old_page;
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//
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// RF08 state
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//
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assign ADC = buffer_matches_DMA;
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// fake the photocell sensor
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always @(posedge clk)
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if (reset)
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photocell_counter <= 0;
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@ -870,6 +928,7 @@ module pdp8_rf(clk, reset, iot, state, mb,
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assign DRE = PCA;
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assign DCF = db_done;
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/* we don't support write lock */
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always @(posedge clk)
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if (reset)
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begin
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@ -1,9 +1,9 @@
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/* 256x12 static ram */
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module ram_256x12(A, DI, DO, CE_N, WE_N);
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input[14:0] A;
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input [11:0] DI;
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input CE_N, WE_N;
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input [7:0] A;
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input [11:0] DI;
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input CE_N, WE_N;
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output [11:0] DO;
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reg [11:0] ram [0:255];
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