Add coax_tx_bit_timer

interface2/rtl/coax_tx_bit_timer.v

@@ -0,0 +1,32 @@
+`default_nettype none
+
+module coax_tx_bit_timer (
+    input clk,
+    input reset,
+    output first_half,
+    output second_half,
+    output last_clock
+);
+    parameter CLOCKS_PER_BIT = 8;
+
+    reg [$clog2(CLOCKS_PER_BIT):0] counter = 0;
+    reg [$clog2(CLOCKS_PER_BIT):0] next_counter;
+
+    always @(*)
+    begin
+        next_counter = last_clock ? 0 : counter + 1;
+    end
+
+    always @(posedge clk)
+    begin
+        counter <= next_counter;
+
+        if (reset)
+            counter <= 0;
+    end
+
+    assign first_half = (counter < CLOCKS_PER_BIT / 2);
+    assign second_half = ~first_half;
+
+    assign last_clock = (counter == CLOCKS_PER_BIT - 1);
+endmodule

interface2/tests/Makefile

@@ -3,8 +3,9 @@ VVP ?= vvp
 
 RTL = ../rtl
 
-all: coax_rx_bit_timer_tb.vcd coax_rx_tb.vcd
+all: coax_tx_bit_timer_tb.vcd coax_rx_bit_timer_tb.vcd coax_rx_tb.vcd
 
+coax_tx_bit_timer_tb: coax_tx_bit_timer_tb.v $(RTL)/coax_tx_bit_timer.v
 coax_rx_bit_timer_tb: coax_rx_bit_timer_tb.v $(RTL)/coax_rx_bit_timer.v
 coax_rx_tb: coax_rx_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_bit_timer.v
 

interface2/tests/coax_tx_bit_timer_tb.v

@@ -0,0 +1,38 @@
+`default_nettype none
+
+module coax_tx_bit_timer_tb;
+    reg clk = 0;
+
+    initial
+    begin
+        forever
+        begin
+            #1 clk <= ~clk;
+        end
+    end
+
+    reg reset = 0;
+    wire first_half;
+    wire second_half;
+    wire last_clock;
+
+    coax_tx_bit_timer #(
+        .CLOCKS_PER_BIT(8)
+    ) dut (
+        .clk(clk),
+        .reset(reset),
+        .first_half(first_half),
+        .second_half(second_half),
+        .last_clock(last_clock)
+    );
+
+    initial
+    begin
+        $dumpfile("coax_tx_bit_timer_tb.vcd");
+        $dumpvars(0, coax_tx_bit_timer_tb);
+
+        #64;
+
+        $finish;
+    end
+endmodule