mirror of
https://github.com/lowobservable/coax.git
synced 2026-02-27 17:32:39 +00:00
Add SNOOPIE module
This commit is contained in:
@@ -61,6 +61,8 @@ public:
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void handleInterrupt();
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int snoopie(uint16_t *buffer, size_t bufferSize, uint8_t *writeIndex);
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private:
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SPICoaxTransceiver &_spiCoaxTransceiver;
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CoaxProtocol _txProtocol;
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@@ -129,6 +131,8 @@ public:
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return readRegister(COAX_REGISTER_STATUS) & COAX_REGISTER_STATUS_RX_ACTIVE;
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};
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int snoopie(uint16_t *buffer, size_t bufferSize, uint8_t *writeIndex);
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private:
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void spiTransfer(const uint8_t *transmitBuffer, uint8_t *receiveBuffer, size_t count);
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};
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@@ -25,6 +25,7 @@
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#define COMMAND_INFO 0xf0
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#define COMMAND_TEST 0xf1
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#define COMMAND_DFU 0xf2
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#define COMMAND_SNOOPIE_REPORT 0xf3
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#define INFO_SUPPORTED_QUERIES 0x01
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#define INFO_HARDWARE_TYPE 0x02
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@@ -59,4 +60,7 @@ private:
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void handleInfo(uint8_t *buffer, size_t bufferCount);
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void handleTest(uint8_t *buffer, size_t bufferCount);
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void handleDFU(uint8_t *buffer, size_t bufferCount);
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void snoopieTeamAway();
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void handleSnoopieReport(uint8_t *buffer, size_t bufferCount);
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};
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@@ -246,10 +246,16 @@ void Coax::handleInterrupt()
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}
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}
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int Coax::snoopie(uint16_t *buffer, size_t bufferSize, uint8_t *writeIndex)
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{
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return _spiCoaxTransceiver.snoopie(buffer, bufferSize, writeIndex);
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}
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#define COAX_COMMAND_READ_REGISTER 0x2
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#define COAX_COMMAND_WRITE_REGISTER 0x3
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#define COAX_COMMAND_TX 0x4
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#define COAX_COMMAND_RX 0x5
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#define COAX_COMMAND_SNOOPIE 0x6
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#define COAX_COMMAND_RESET 0xff
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#define NOP asm volatile("nop\n\t")
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@@ -511,6 +517,37 @@ void SPICoaxTransceiver::setRXParity(CoaxParity parity)
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writeRegister(COAX_REGISTER_CONTROL, parity == CoaxParity::Even ? COAX_REGISTER_CONTROL_RX_PARITY : 0, COAX_REGISTER_CONTROL_RX_PARITY);
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}
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int SPICoaxTransceiver::snoopie(uint16_t *buffer, size_t bufferSize, uint8_t *writeIndex)
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{
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uint8_t transmitBuffer[2] = { COAX_COMMAND_SNOOPIE };
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uint8_t receiveBuffer[2];
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ATOMIC_BLOCK_START;
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LL_GPIO_ResetOutputPin(ICE40_CS_GPIO_Port, ICE40_CS_Pin);
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spiTransfer(transmitBuffer, NULL, 1);
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transmitBuffer[0] = 0x00;
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transmitBuffer[1] = 0x00;
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spiTransfer(transmitBuffer, receiveBuffer, 1);
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*writeIndex = receiveBuffer[0];
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for (size_t index = 0; index < bufferSize; index++) {
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spiTransfer(transmitBuffer, receiveBuffer, 2);
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uint16_t value = (receiveBuffer[0] << 8) | receiveBuffer[1];
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buffer[index] = value;
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}
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LL_GPIO_SetOutputPin(ICE40_CS_GPIO_Port, ICE40_CS_Pin);
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ATOMIC_BLOCK_END;
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return 0;
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}
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void SPICoaxTransceiver::spiTransfer(const uint8_t *transmitBuffer,
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uint8_t *receiveBuffer, size_t count)
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{
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@@ -84,6 +84,8 @@ void Interface::handleMessage(uint8_t *buffer, size_t bufferCount)
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handleTest(buffer + 3, count - 1);
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} else if (command == COMMAND_DFU) {
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handleDFU(buffer + 3, count - 1);
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} else if (command == COMMAND_SNOOPIE_REPORT) {
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handleSnoopieReport(buffer + 3, count - 1);
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} else {
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sendErrorMessage(ERROR_UNKNOWN_COMMAND, NULL);
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}
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@@ -178,6 +180,10 @@ void Interface::handleTransmitReceive(uint8_t *buffer, size_t bufferCount)
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if (receiveCount < 0) {
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Debug::trap(403, "error = %d", receiveCount);
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// vvv
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snoopieTeamAway();
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// ^^^
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_indicators.error();
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// Convert the error to legacy interface error for compatability.
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@@ -292,3 +298,34 @@ void Interface::handleDFU(uint8_t *buffer, size_t bufferCount)
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resetToBootloader();
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}
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uint16_t snoopieBuffer[256];
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uint8_t snoopieWriteIndex;
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void Interface::snoopieTeamAway()
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{
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printf("\r\n\r\nSNOOPIE +++\r\n");
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_coax.snoopie((uint16_t *) &snoopieBuffer, 256, &snoopieWriteIndex);
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printf("writeIndex = %d\r\n", snoopieWriteIndex);
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for (size_t index = 0; index < 256; index++) {
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uint16_t counter = (snoopieBuffer[index] & 0xfff0) >> 4;
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uint8_t probes = snoopieBuffer[index] & 0x0f;
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printf("%d %d\r\n", counter, probes);
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}
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printf("SNOOPIE ---\r\n");
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}
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void Interface::handleSnoopieReport(uint8_t *buffer, size_t bufferCount)
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{
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buffer[0] = 0x01;
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buffer[1] = snoopieWriteIndex;
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memcpy(buffer + 2, &snoopieBuffer, 256 * sizeof(uint16_t));
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MessageSender::send(buffer, 2 + (256 * sizeof(uint16_t)));
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}
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@@ -19,6 +19,7 @@ add_file -verilog -lib work "third_party/ram_sdp.v"
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add_file -verilog -lib work "strobe_cdc.v"
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add_file -verilog -lib work "top.v"
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add_file -verilog -lib work "dual_clock_spi_device.v"
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add_file -verilog -lib work "snoopie.v"
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add_file -constraint -lib work "clocks.sdc"
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#implementation: "coax_Implmnt"
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impl -add coax_Implmnt -type fpga
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@@ -47,7 +47,12 @@ module control (
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output reg rx_read_strobe,
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input rx_empty,
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output rx_protocol,
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output rx_parity
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output rx_parity,
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output reg snoopie_enable,
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input [15:0] snoopie_read_data,
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output reg snoopie_read_strobe,
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input [7:0] snoopie_write_address
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);
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parameter DEFAULT_CONTROL_REGISTER = 8'b01001000;
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@@ -64,6 +69,11 @@ module control (
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localparam STATE_RX_3 = 10;
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localparam STATE_RX_4 = 11;
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localparam STATE_RESET = 12;
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localparam STATE_SNOOPIE_1 = 13;
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localparam STATE_SNOOPIE_2 = 14;
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localparam STATE_SNOOPIE_3 = 15;
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localparam STATE_SNOOPIE_4 = 16;
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localparam STATE_SNOOPIE_5 = 17;
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reg [7:0] state = STATE_IDLE;
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reg [7:0] next_state;
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@@ -94,6 +104,9 @@ module control (
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reg [15:0] rx_buffer;
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reg [15:0] next_rx_buffer;
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reg next_snoopie_enable;
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reg next_snoopie_read_strobe;
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reg [1:0] spi_cs_n_d;
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always @(posedge clk)
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@@ -124,6 +137,9 @@ module control (
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next_rx_read_strobe = 0;
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next_rx_buffer = rx_buffer;
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next_snoopie_enable = 1;
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next_snoopie_read_strobe = 0;
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case (state)
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STATE_IDLE:
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begin
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@@ -136,6 +152,7 @@ module control (
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4'h3: next_state = STATE_WRITE_REGISTER_1;
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4'h4: next_state = STATE_TX_1;
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4'h5: next_state = STATE_RX_1;
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4'h6: next_state = STATE_SNOOPIE_1;
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4'hf: next_state = STATE_RESET;
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endcase
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end
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@@ -280,6 +297,57 @@ module control (
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next_state = STATE_IDLE;
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end
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STATE_SNOOPIE_1:
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begin
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next_snoopie_enable = 0;
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next_spi_tx_data = snoopie_write_address;
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next_spi_tx_strobe = 1;
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next_state = STATE_SNOOPIE_2;
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end
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STATE_SNOOPIE_2:
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begin
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next_snoopie_enable = 0;
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if (spi_rx_strobe)
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next_state = STATE_SNOOPIE_3;
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end
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STATE_SNOOPIE_3:
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begin
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next_snoopie_enable = 0;
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next_spi_tx_data = snoopie_read_data[15:8];
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next_spi_tx_strobe = 1;
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next_state = STATE_SNOOPIE_4;
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end
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STATE_SNOOPIE_4:
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begin
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next_snoopie_enable = 0;
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if (spi_rx_strobe)
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begin
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next_snoopie_read_strobe = 1;
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next_spi_tx_data = snoopie_read_data[7:0];
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next_spi_tx_strobe = 1;
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next_state = STATE_SNOOPIE_5;
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end
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end
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STATE_SNOOPIE_5:
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begin
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next_snoopie_enable = 0;
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if (spi_rx_strobe)
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next_state = STATE_SNOOPIE_3;
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end
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endcase
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if (spi_cs_n_d[1])
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@@ -317,6 +385,9 @@ module control (
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rx_read_strobe <= next_rx_read_strobe;
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rx_buffer <= next_rx_buffer;
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snoopie_enable <= next_snoopie_enable;
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snoopie_read_strobe <= next_snoopie_read_strobe;
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if (reset)
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begin
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state <= STATE_IDLE;
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@@ -337,6 +408,9 @@ module control (
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rx_reset <= 0;
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rx_read_strobe <= 0;
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rx_buffer <= 0;
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snoopie_enable <= 1;
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snoopie_read_strobe <= 0;
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end
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previous_tx_active <= tx_active;
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68
interface2/fpga/rtl/snoopie.v
Normal file
68
interface2/fpga/rtl/snoopie.v
Normal file
@@ -0,0 +1,68 @@
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`default_nettype none
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module snoopie (
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input clk,
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input enable,
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input [3:0] probes,
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output [7:0] xxx_write_address,
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output [15:0] read_data,
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input read_strobe
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);
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reg previous_enable = 0;
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reg [11:0] counter;
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reg [3:0] previous_probes;
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reg [7:0] write_address;
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reg [15:0] write_data;
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reg write_enable;
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reg [7:0] read_address;
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ram_sdp #(
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.AWIDTH(8),
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.DWIDTH(16)
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) ram (
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.clk(clk),
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.wr_addr(write_address),
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.wr_data(write_data),
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.wr_ena(write_enable),
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.rd_addr(read_address),
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.rd_data(read_data),
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.rd_ena(1'b1)
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);
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always @(posedge clk)
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begin
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counter <= counter + 1;
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// Writer...
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if (enable && !previous_enable)
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write_address <= 0;
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else if (write_enable)
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write_address <= write_address + 1;
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write_enable <= 0;
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if (enable && probes != previous_probes)
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begin
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write_data <= { counter[11:0], probes[3:0] };
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write_enable <= 1;
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end
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// Reader...
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if (enable && !previous_enable)
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read_address <= 0;
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else if (read_strobe)
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read_address <= read_address + 1;
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previous_probes <= probes;
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previous_enable <= enable;
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end
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assign xxx_write_address = write_address;
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endmodule
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@@ -168,6 +168,23 @@ module top (
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.rx_debug(rx_debug)
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);
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wire snoopie_enable;
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wire [15:0] snoopie_read_data;
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wire snoopie_read_strobe;
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wire [7:0] snoopie_write_address;
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snoopie snoopie (
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.clk(clk),
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.enable(snoopie_enable),
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.probes({ internal_rx, rx_error, 2'b00 }),
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.read_data(snoopie_read_data),
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.read_strobe(snoopie_read_strobe),
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.xxx_write_address(snoopie_write_address)
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);
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control control (
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.clk(clk),
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.reset(reset),
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@@ -198,7 +215,12 @@ module top (
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.rx_read_strobe(rx_read_strobe),
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.rx_empty(rx_empty),
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.rx_protocol(rx_protocol),
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.rx_parity(rx_parity)
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.rx_parity(rx_parity),
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.snoopie_enable(snoopie_enable),
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.snoopie_read_data(snoopie_read_data),
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.snoopie_read_strobe(snoopie_read_strobe),
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.snoopie_write_address(snoopie_write_address)
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);
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assign irq = rx_active || rx_error;
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@@ -17,6 +17,7 @@ coax_tx_rx_frontend_tb: coax_tx_rx_frontend_tb.v $(RTL)/coax_tx_rx_frontend.v $(
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control_tb: control_tb.v $(RTL)/control.v $(RTL)/coax_buffered_tx.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v $(RTL)/coax_buffer.v $(RTL)/third_party/*.v
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tx_rx_loopback_tb: tx_rx_loopback_tb.v $(RTL)/coax_tx.v $(RTL)/coax_tx_bit_timer.v $(RTL)/coax_rx.v $(RTL)/coax_rx_ss_detector.v
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regression_memorex_tb: regression_memorex_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_ss_detector.v
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regression_johann_tb: regression_johann_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_ss_detector.v
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test: $(TESTS)
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./run_tests.sh
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169
interface2/fpga/tests/regression_johann_tb.v
Normal file
169
interface2/fpga/tests/regression_johann_tb.v
Normal file
@@ -0,0 +1,169 @@
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`default_nettype none
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`include "assert.v"
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module regression_johann_tb;
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reg clk = 0;
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initial
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begin
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forever
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begin
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#1 clk <= ~clk;
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end
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end
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reg probe_rx = 0;
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reg probe_error = 0;
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reg reset = 0;
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coax_rx #(
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.CLOCKS_PER_BIT(16)
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) dut (
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.clk(clk),
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.reset(reset),
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.rx(probe_rx),
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.protocol(1'b0),
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.parity(1'b1)
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);
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initial
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begin
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$dumpfile("regression_johann_tb.vcd");
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$dumpvars(0, regression_johann_tb);
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test_1;
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$finish;
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end
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task test_1;
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begin
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$display("START: test_1");
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`assert_equal(dut.state, dut.STATE_IDLE, "state should be STATE_IDLE");
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// ... | vcd2v -s 2 -t nnnn probe_rx=top.internal_rx probe_error=top.rx_error
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//
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// vvv
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#200;
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probe_rx = 1;
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probe_error = 0;
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#18;
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probe_rx = 0;
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probe_error = 0;
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#16;
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probe_rx = 1;
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probe_error = 0;
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#16;
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probe_rx = 0;
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probe_error = 0;
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#16;
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probe_rx = 1;
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probe_error = 0;
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#16;
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probe_rx = 0;
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probe_error = 0;
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#16;
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probe_rx = 1;
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probe_error = 0;
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#16;
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probe_rx = 0;
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probe_error = 0;
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#16;
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probe_rx = 1;
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probe_error = 0;
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#16;
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probe_rx = 0;
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probe_error = 0;
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#16;
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probe_rx = 1;
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probe_error = 0;
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#16;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#48;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#48;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#32;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#16;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#32;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#32;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#32;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#32;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
#32;
|
||||
probe_rx = 1;
|
||||
probe_error = 0;
|
||||
#4;
|
||||
probe_rx = 1;
|
||||
probe_error = 1;
|
||||
#28;
|
||||
probe_rx = 0;
|
||||
probe_error = 1;
|
||||
#16;
|
||||
probe_rx = 1;
|
||||
probe_error = 1;
|
||||
#82;
|
||||
probe_rx = 0;
|
||||
probe_error = 1;
|
||||
#258;
|
||||
probe_rx = 0;
|
||||
probe_error = 0;
|
||||
// ^^^
|
||||
|
||||
#64;
|
||||
|
||||
`assert_equal(dut.state, dut.STATE_IDLE, "state should be STATE_IDLE");
|
||||
|
||||
`assert_equal(dut.data, 10'b0000001010, "data not correct")
|
||||
|
||||
$display("END: test_1");
|
||||
end
|
||||
endtask
|
||||
endmodule
|
||||
@@ -80,6 +80,42 @@ class SerialInterface(Interface):
|
||||
if message[0] != 0x01:
|
||||
raise _convert_error(message)
|
||||
|
||||
def snoopie_report(self):
|
||||
message = bytes([0xf3])
|
||||
|
||||
self._write_message(message)
|
||||
|
||||
message = self._read_message()
|
||||
|
||||
if message[0] != 0x01:
|
||||
raise Exception('Uh, some sort of problem with the SNOOPIE report')
|
||||
|
||||
if len(message) != 1 + 1 + (2 * 256):
|
||||
raise Exception('Uh, length of SNOOPIE report is not correct')
|
||||
|
||||
write_index = message[1]
|
||||
buffer = message[2:]
|
||||
|
||||
print()
|
||||
print()
|
||||
|
||||
print('* ' * 40)
|
||||
|
||||
print(f'write_index = {write_index}')
|
||||
|
||||
for i in range(256):
|
||||
x = buffer[i * 2] | (buffer[(i * 2) + 1] << 8)
|
||||
|
||||
counter = (x & 0xfff0) >> 4
|
||||
probes = x & 0x0f
|
||||
|
||||
print(f'{counter} {probes}')
|
||||
|
||||
print('* ' * 40)
|
||||
|
||||
print()
|
||||
print()
|
||||
|
||||
def _get_features(self):
|
||||
"""Get interface features."""
|
||||
message = bytes([0xf0, 0x07])
|
||||
@@ -125,6 +161,10 @@ class SerialInterface(Interface):
|
||||
if not isinstance(error, (ReceiveError, ReceiveTimeout)):
|
||||
raise error
|
||||
|
||||
# vvv
|
||||
self.snoopie_report()
|
||||
# ^^^
|
||||
|
||||
response = error
|
||||
|
||||
responses.append(response)
|
||||
|
||||
@@ -91,6 +91,8 @@ class SerialInterfaceTransmitReceiveTestCase(unittest.TestCase):
|
||||
self.interface._write_message = Mock(wraps=self.interface._write_message)
|
||||
self.interface._read_message = Mock()
|
||||
|
||||
self.interface.snoopie_report = Mock()
|
||||
|
||||
def test_words_frame(self):
|
||||
# Arrange
|
||||
self.interface._read_message.return_value=bytes.fromhex('01 00 00')
|
||||
|
||||
Reference in New Issue
Block a user