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https://github.com/lowobservable/coax.git
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Add receiver enable
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@@ -3,6 +3,7 @@
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module coax_rx (
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input clk,
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input rx,
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input enable,
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input data_read,
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output active,
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output reg [9:0] data = 10'b0,
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@@ -37,7 +38,7 @@ module coax_rx (
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wire bit_timer_enable;
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wire bit_timer_sample;
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assign bit_timer_enable = (state != CODE_VIOLATION_1A && state != CODE_VIOLATION_3B);
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assign bit_timer_enable = (enable && state != CODE_VIOLATION_1A && state != CODE_VIOLATION_3B);
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coax_rx_bit_timer #(
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.CLOCKS_PER_BIT(CLOCKS_PER_BIT)
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@@ -104,35 +105,46 @@ module coax_rx (
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rx_0 <= rx;
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rx_1 <= rx_0;
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if (data_read && data_available)
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if (enable)
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begin
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if (data_read && data_available)
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data_available <= 0;
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if (state == DATA)
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begin
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if (state != previous_state)
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begin
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input_data <= 10'b0;
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input_data_counter <= 0;
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parity_bit <= 1; // Even parity includes sync bit
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end
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else if (bit_timer_sample)
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begin
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input_data <= { input_data[8:0], rx_1 };
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input_data_counter <= input_data_counter + 1;
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if (rx_1)
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parity_bit <= ~parity_bit;
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end
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end
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else if (state == END_1 && state != previous_state)
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begin
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data <= input_data;
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data_available <= 1;
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end
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state <= next_state;
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previous_state <= state;
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end
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else
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begin
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state <= IDLE;
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previous_state <= IDLE;
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data <= 10'b0;
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data_available <= 0;
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if (state == DATA)
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begin
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if (state != previous_state)
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begin
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input_data <= 10'b0;
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input_data_counter <= 0;
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parity_bit <= 1; // Even parity includes sync bit
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end
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else if (bit_timer_sample)
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begin
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input_data <= { input_data[8:0], rx_1 };
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input_data_counter <= input_data_counter + 1;
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if (rx_1)
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parity_bit <= ~parity_bit;
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end
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end
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else if (state == END_1 && state != previous_state)
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begin
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data <= input_data;
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data_available <= 1;
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end
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state <= next_state;
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previous_state <= state;
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end
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assign active = (state >= SYNC_BIT && state <= END_1);
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@@ -65,6 +65,7 @@ module top (
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) coax_rx (
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.clk(clk_19mhz),
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.rx(rx),
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.enable(rx_enable && !tx_active),
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.active(rx_active),
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.data(rx_data),
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.data_available(rx_data_available),
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