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Consistency

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This commit is contained in:
Andrew Kay
2020-07-08 21:42:05 -05:00
parent 411cd847dc
commit 7fd767a8cd
1 changed files with 8 additions and 8 deletions
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16
interface2/rtl/coax_rx.v
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@@ -47,8 +47,8 @@ module coax_rx (
reg [9:0] next_data;
reg next_data_available;
reg [9:0] internal_data;
reg [9:0] next_internal_data;
reg [9:0] input_data;
reg [9:0] next_input_data;
reg [3:0] bit_counter = 0;
reg [3:0] next_bit_counter;
@@ -79,7 +79,7 @@ module coax_rx (
next_data = data;
next_data_available = data_available;
next_internal_data = internal_data;
next_input_data = input_data;
next_bit_counter = bit_counter;
case (state)
@@ -236,7 +236,7 @@ module coax_rx (
begin
if (synchronized)
begin
next_internal_data = { internal_data[8:0], rx };
next_input_data = { input_data[8:0], rx };
if (bit_counter < 9)
begin
@@ -262,12 +262,12 @@ module coax_rx (
if (synchronized)
begin
// Even parity includes the sync bit.
if (rx == ^{ 1'b1, internal_data })
if (rx == ^{ 1'b1, input_data })
begin
if (!data_available)
begin
next_data_available = 1;
next_data = internal_data;
next_data = input_data;
next_state = SYNC_BIT;
end
else
@@ -327,7 +327,7 @@ module coax_rx (
data <= next_data;
data_available <= next_data_available;
internal_data <= next_internal_data;
input_data <= next_input_data;
bit_counter <= next_bit_counter;
active <= next_active;
@@ -343,7 +343,7 @@ module coax_rx (
data <= 10'b0000000000;
data_available <= 0;
internal_data <= 10'b0000000000;
input_data <= 10'b0000000000;
bit_counter <= 0;
active <= 0;