Attempt DP8340 and DP8341 shims

interface2/rtl/Makefile

@@ -5,7 +5,7 @@ TINYPROG ?= tinyprog
 
 all: top.bin
 
-top.json: top.v hello_world.v coax_tx_bit_timer.v coax_tx.v coax_rx_bit_timer.v coax_rx.v
+top.json: top.v hello_world.v coax_tx_bit_timer.v coax_tx.v coax_rx_bit_timer.v coax_rx.v dp8340_shim.v dp8341_shim.v
 
 prog: top.bin
 	$(TINYPROG) -p top.bin

interface2/rtl/dp8340_shim.v

@@ -0,0 +1,42 @@
+`default_nettype none
+
+module dp8340_shim (
+    input clk,
+    input [9:0] data_in,
+    input reg_load_n,
+    output reg_full,
+    input auto_response_n,
+    output tx_active,
+    input parity_control,
+    // TODO: even_odd_parity not supported by coax_tx
+    output data_out_n,
+    output data_out,
+    output data_delay
+);
+    parameter CLOCKS_PER_BIT = 8;
+
+    wire [9:0] data;
+
+    always @(*)
+    begin
+        data <= data_in;
+
+        if (~auto_response_n)
+            data <= 10'b0;
+        else if (~parity_control)
+            data <= { data_in[9:2], ^data_in[9:2], data_in[0] };
+    end
+
+    coax_tx #(
+        .CLOCKS_PER_BIT(CLOCKS_PER_BIT)
+    ) coax_tx (
+        .clk(clk),
+        .load(~reg_load_n),
+        .data(data),
+        .full(reg_full),
+        .active(tx_active),
+        .tx(data_out),
+        .tx_delay(data_delay),
+        .tx_inverted(data_out_n)
+    );
+endmodule

interface2/rtl/dp8341_shim.v

@@ -0,0 +1,53 @@
+`default_nettype none
+
+module dp8341_shim (
+    input clk,
+    input rx_disable,
+    input data_in,
+    output rx_active,
+    // TODO: error
+    input register_read_n,
+    output data_available,
+    // TODO: output_control
+    input output_enable,
+    inout [9:0] data_out
+);
+    parameter CLOCKS_PER_BIT = 8;
+
+    wire rx;
+
+    // TODO: Move receiver enable to coax_rx and correctly handle case where
+    // receiver is disabled while active.
+    assign rx = (~rx_disable | rx_active) & data_in;
+
+    wire [9:0] data;
+
+    assign data_out = (output_enable ? data : 10'bzzzzzzzzzz);
+
+    reg register_read_n_0 = 1'b1;
+    reg register_read_n_1 = 1'b1;
+    reg previous_register_read_n = 1'b1;
+
+    always @(posedge clk)
+    begin
+        register_read_n_0 <= register_read_n;
+        register_read_n_1 <= register_read_n_0;
+
+        previous_register_read_n <= register_read_n_1;
+    end
+
+    wire data_read;
+
+    assign data_read = register_read_n_1 && ~previous_register_read_n;
+
+    coax_rx #(
+        .CLOCKS_PER_BIT(CLOCKS_PER_BIT)
+    ) coax_rx (
+        .clk(clk),
+        .rx(rx),
+        .data_read(data_read),
+        .active(rx_active),
+        .data(data),
+        .data_available(data_available)
+    );
+endmodule

interface2/rtl/pins.pcf

@@ -1,16 +1,23 @@
-set_io --warn-no-port tx_active B1
-set_io --warn-no-port tx C2
-set_io --warn-no-port tx_delay C1
-set_io --warn-no-port tx_inverted D2
-
-set_io --warn-no-port rx D1
-set_io --warn-no-port rx_active E2
-set_io --warn-no-port rx_data_available E1
-
-set_io --warn-no-port xxx_debug_1 G2
-set_io --warn-no-port xxx_debug_2 H1
-
 # 16MHz clock
 set_io --warn-no-port clk_16mhz B2
 
+# DP8341 receiver
+set_io --warn-no-port dp8341_data_in A2
+set_io --warn-no-port dp8341_rx_active D2
+set_io --warn-no-port dp8341_register_read_n D1
+set_io --warn-no-port dp8341_data_available E2
+set_io --warn-no-port dp8341_output_enable E1
+
+# Shared data bus
+set_io --warn-no-port data[9] B6
+set_io --warn-no-port data[8] A7
+set_io --warn-no-port data[7] B7
+set_io --warn-no-port data[6] A8
+set_io --warn-no-port data[5] B8
+set_io --warn-no-port data[4] A9
+set_io --warn-no-port data[3] C9
+set_io --warn-no-port data[2] D8
+set_io --warn-no-port data[1] D9
+set_io --warn-no-port data[0] H9
+
 set_io --warn-no-port usb_pu A3

interface2/rtl/top.v

@@ -2,14 +2,17 @@
 
 module top (
     input clk_16mhz,
-    output tx_active,
-    output tx,
-    output tx_delay,
-    output tx_inverted,
-    input rx,
-    output rx_active,
-    output xxx_debug_1,
-    output xxx_debug_2,
+
+    // DP8341 receiver
+    input dp8341_data_in,
+    output dp8341_rx_active,
+    input dp8341_register_read_n,
+    output dp8341_data_available,
+    input dp8341_output_enable,
+
+    // Shared data bus
+    inout [9:0] data,
+
     output usb_pu
 );
     // 19 MHz
@@ -30,10 +33,21 @@ module top (
         .PLLOUTCORE(clk_19mhz)
     );
 
-    coax_rx coax_rx (
+    wire dp8341_rx_disable;
+
+    assign dp8341_rx_disable = 0;
+
+    dp8341_shim #(
+        .CLOCKS_PER_BIT(8)
+    ) dp8341 (
         .clk(clk_19mhz),
-        .rx(rx),
-        .active(rx_active)
+        .rx_disable(dp8341_rx_disable),
+        .data_in(dp8341_data_in),
+        .rx_active(dp8341_rx_active),
+        .register_read_n(dp8341_register_read_n),
+        .data_available(dp8341_data_available),
+        .output_enable(dp8341_output_enable),
+        .data_out(data)
     );
 
     assign usb_pu = 0;