Quiesce pattern

interface2/rtl/coax_tx.v

@@ -2,13 +2,56 @@
 
 module coax_tx (
     input clk,
-    output tx
+    input xxx,
+    output tx,
+    output active
 );
     parameter CLOCKS_PER_BIT = 8;
 
+    localparam IDLE = 0;
+    localparam BIT_ALIGN = 1;
+    localparam LINE_QUIESCE_1 = 2;
+    localparam LINE_QUIESCE_2 = 3;
+    localparam LINE_QUIESCE_3 = 4;
+    localparam LINE_QUIESCE_4 = 5;
+    localparam LINE_QUIESCE_5 = 6;
+    localparam LINE_QUIESCE_6 = 7;
+
     reg [$clog2(CLOCKS_PER_BIT):0] bit_counter = 0;
 
-    reg bit = 1'b1;
+    wire bit_strobe;
+    wire bit_first_half;
+
+    reg [3:0] state;
+    reg [3:0] next_state;
+
+    reg bit = 0;
+
+    always @(*)
+    begin
+        next_state <= state;
+
+        if (bit_strobe)
+        begin
+            case (state)
+                BIT_ALIGN: next_state <= LINE_QUIESCE_1;
+                LINE_QUIESCE_1: next_state <= LINE_QUIESCE_2;
+                LINE_QUIESCE_2: next_state <= LINE_QUIESCE_3;
+                LINE_QUIESCE_3: next_state <= LINE_QUIESCE_4;
+                LINE_QUIESCE_4: next_state <= LINE_QUIESCE_5;
+                LINE_QUIESCE_5: next_state <= LINE_QUIESCE_6;
+                LINE_QUIESCE_6: next_state <= IDLE;
+            endcase
+        end
+    end
+
+    always @(posedge clk)
+    begin
+        if (xxx)
+            state <= BIT_ALIGN;
+        else 
+            state <= next_state;
+    end
 
     always @(posedge clk)
     begin
@@ -18,5 +61,16 @@ module coax_tx (
             bit_counter <= bit_counter + 1;
     end
 
-    assign tx = bit_counter < (CLOCKS_PER_BIT / 2) ? ~bit : bit;
+    assign bit_strobe = (bit_counter == 7);
+    assign bit_first_half = (bit_counter < CLOCKS_PER_BIT / 2);
+
+    always @(*)
+    begin
+        tx <= 0;
+
+        if (state >= LINE_QUIESCE_1 && state <= LINE_QUIESCE_6)
+            tx <= bit_first_half ? 0 : 1;
+    end
+
+    assign active = (state != IDLE);
 endmodule

interface2/rtl/pins.pcf

@@ -1,4 +1,5 @@
 set_io --warn-no-port tx B8
+set_io --warn-no-port tx_active A9
 
 # 16MHz clock
 set_io --warn-no-port clk B2

interface2/rtl/top.v

@@ -3,6 +3,7 @@
 module top (
     input clk,
     output tx,
+    output tx_active,
     output usb_pu
 );
     wire coax_clk;
@@ -25,8 +26,21 @@ module top (
 
     coax_tx coax_tx (
         .clk(coax_clk),
-        .tx(tx)
+        .xxx(do_it),
+        .tx(tx),
+        .active(tx_active)
     );
 
+    wire do_it;
+
+    assign do_it = (counter == 16'b1111_1111_1111_1111);
+
+    reg [15:0] counter = 0;
+
+    always @(posedge coax_clk)
+    begin
+        counter <= counter + 1;
+    end
+
     assign usb_pu = 0;
 endmodule