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Update pin assignments for new development board
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@@ -16,17 +16,17 @@
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#include "NewCoax.h"
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#define RESET_PIN 4
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#define RESET_PIN 5 // -> FPGA 6
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#define TX_ACTIVE_PIN 5
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#define TX_LOAD_PIN 6
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#define TX_FULL_PIN 7
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#define TX_ACTIVE_PIN 3 // -> FPGA 3
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#define TX_LOAD_PIN 6 // -> FPGA 7
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#define TX_FULL_PIN 7 // -> FPGA 8
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#define RX_ENABLE_PIN 8
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#define RX_ACTIVE_PIN 9
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#define RX_ERROR_PIN 10
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#define RX_DATA_AVAILABLE_PIN 11
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#define RX_READ_PIN 12
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#define RX_ENABLE_PIN 8 // -> FPGA 9
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#define RX_ACTIVE_PIN 9 // -> FPGA 10
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#define RX_ERROR_PIN 10 // -> FPGA 11
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#define RX_DATA_AVAILABLE_PIN 11 // -> FPGA 12
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#define RX_READ_PIN 12 // -> FPGA 13
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#define DATA_BUS_START_PIN 14
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#define DATA_BUS_END_PIN 23
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@@ -4,14 +4,14 @@ set_io --warn-no-port clk_16mhz B2
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set_io --warn-no-port reset D2 # 6
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# Transmitter
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set_io --warn-no-port tx_active A2 # 1
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set_io --warn-no-port tx_inverted A1 # 2
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set_io --warn-no-port tx_delay B1 # 3
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set_io --warn-no-port tx_active B1 # 3!
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set_io --warn-no-port tx_inverted C2 # 4!
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set_io --warn-no-port tx_delay A1 # 2!
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set_io --warn-no-port tx_load D1 # 7
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set_io --warn-no-port tx_full E2 # 8
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# Receiver
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set_io --warn-no-port rx C2 # 4
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set_io --warn-no-port rx A2 # 1!
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set_io --warn-no-port rx_enable E1 # 9
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set_io --warn-no-port rx_active G2 # 10
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set_io --warn-no-port rx_error H1 # 11
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