Verilog templating

interface2/Makefile

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+SUBDIRS = tests rtl
+
+all: $(SUBDIRS)
+
+$(SUBDIRS):
+	$(MAKE) -C $@
+
+clean:
+	for dir in $(SUBDIRS); do \
+		$(MAKE) -C $$dir clean; \
+	done
+
+.PHONY: all $(SUBDIRS) clean

interface2/rtl/.gitignore

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+*.json
+*.asc
+*.bin

interface2/rtl/Makefile

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+YOSYS ?= yosys
+NEXTPNR ?= nextpnr-ice40
+ICEPACK ?= icepack
+TINYPROG ?= tinyprog
+
+all: top.bin
+
+top.json: top.v coax_tx.v
+
+prog: top.bin
+	$(TINYPROG) -p top.bin
+
+clean:
+	rm -f *.json *.asc *.bin
+
+%.json:
+	$(YOSYS) -p 'synth_ice40 -top top -json $@' $^
+
+%.asc: %.json pins.pcf
+	$(NEXTPNR) --lp8k --package cm81 --json $< --pcf pins.pcf --asc $@
+
+%.bin: %.asc
+	$(ICEPACK) $< $@
+
+.PHONY: all prog clean

interface2/rtl/coax_tx.v

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+`default_nettype none
+
+module coax_tx (
+    input clk,
+    output tx
+);
+    reg state = 0;
+
+    always @(posedge clk)
+    begin
+        state <= ~state;
+    end
+
+    assign tx = state;
+endmodule

interface2/rtl/pins.pcf

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+set_io --warn-no-port tx B8
+
+# 16MHz clock
+set_io --warn-no-port clk B2
+
+set_io --warn-no-port usb_pu A3

interface2/rtl/top.v

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+`default_nettype none
+
+module top (
+    input clk,
+    output tx,
+    output usb_pu
+);
+    coax_tx coax_tx (
+        .clk(clk),
+        .tx(tx)
+    );
+
+    assign usb_pu = 0;
+endmodule

interface2/tests/.gitignore

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+*_tb
+*.vcd

interface2/tests/Makefile

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+IVERILOG ?= iverilog
+VVP ?= vvp
+
+RTL = ../rtl
+
+all: coax_tx_tb.vcd
+
+coax_tx_tb: coax_tx_tb.v $(RTL)/coax_tx.v
+
+clean:
+	rm -f *_tb *.vcd
+
+%_tb:
+	$(IVERILOG) -o $@ $^
+
+%_tb.vcd: %_tb
+	$(VVP) -N $< -lxt2
+
+.PHONY: all, clean

interface2/tests/coax_tx_tb.v

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+`default_nettype none
+
+module coax_tx_tb();
+    reg clk = 0;
+
+    initial
+    begin
+        clk <= 1'h0;
+
+        forever
+        begin
+            #1 clk <= ~clk;
+        end
+    end
+
+    wire tx;
+
+    coax_tx dut (
+        .clk(clk),
+        .tx(tx)
+    );
+
+    initial
+    begin
+        $dumpfile("coax_tx_tb.vcd");
+        $dumpvars(0, coax_tx_tb);
+
+        repeat(100) @(posedge clk);
+
+        $finish;
+    end
+endmodule