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Code Issues Projects Releases Wiki Activity

Drop shims, for now

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This commit is contained in:
Andrew Kay
2020-03-03 19:52:56 -06:00
parent 61e56a2dc3
commit b750c9e756
5 changed files with 18 additions and 121 deletions
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2
interface2/rtl/Makefile
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@@ -5,7 +5,7 @@ TINYPROG ?= tinyprog
all: top.bin
top.json: top.v hello_world.v coax_tx_bit_timer.v coax_tx.v coax_rx_bit_timer.v coax_rx.v dp8340_shim.v dp8341_shim.v
top.json: top.v hello_world.v coax_tx_bit_timer.v coax_tx.v coax_rx_bit_timer.v coax_rx.v
prog: top.bin
$(TINYPROG) -p top.bin

42
interface2/rtl/dp8340_shim.v
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@@ -1,42 +0,0 @@
`default_nettype none
module dp8340_shim (
input clk,
input [9:0] data_in,
input reg_load_n,
output reg_full,
input auto_response_n,
output tx_active,
input parity_control,
// TODO: even_odd_parity not supported by coax_tx
output data_out_n,
output data_out,
output data_delay
);
parameter CLOCKS_PER_BIT = 8;
wire [9:0] data;
always @(*)
begin
data <= data_in;
if (~auto_response_n)
data <= 10'b0;
else if (~parity_control)
data <= { data_in[9:2], ^data_in[9:2], data_in[0] };
end
coax_tx #(
.CLOCKS_PER_BIT(CLOCKS_PER_BIT)
) coax_tx (
.clk(clk),
.load(~reg_load_n),
.data(data),
.full(reg_full),
.active(tx_active),
.tx(data_out),
.tx_delay(data_delay),
.tx_inverted(data_out_n)
);
endmodule

53
interface2/rtl/dp8341_shim.v
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@@ -1,53 +0,0 @@
`default_nettype none
module dp8341_shim (
input clk,
input rx_disable,
input data_in,
output rx_active,
// TODO: error
input register_read_n,
output data_available,
// TODO: output_control
input output_enable,
inout [9:0] data_out
);
parameter CLOCKS_PER_BIT = 8;
wire rx;
// TODO: Move receiver enable to coax_rx and correctly handle case where
// receiver is disabled while active.
assign rx = (~rx_disable | rx_active) & data_in;
wire [9:0] data;
assign data_out = (output_enable ? data : 10'bzzzzzzzzzz);
reg register_read_n_0 = 1'b1;
reg register_read_n_1 = 1'b1;
reg previous_register_read_n = 1'b1;
always @(posedge clk)
begin
register_read_n_0 <= register_read_n;
register_read_n_1 <= register_read_n_0;
previous_register_read_n <= register_read_n_1;
end
wire data_read;
assign data_read = register_read_n_1 && ~previous_register_read_n;
coax_rx #(
.CLOCKS_PER_BIT(CLOCKS_PER_BIT)
) coax_rx (
.clk(clk),
.rx(rx),
.data_read(data_read),
.active(rx_active),
.data(data),
.data_available(data_available)
);
endmodule

11
interface2/rtl/pins.pcf
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@@ -1,12 +1,11 @@
# 16MHz clock
set_io --warn-no-port clk_16mhz B2
# DP8341 receiver
set_io --warn-no-port dp8341_data_in A2
set_io --warn-no-port dp8341_rx_active D2
set_io --warn-no-port dp8341_register_read_n D1
set_io --warn-no-port dp8341_data_available E2
set_io --warn-no-port dp8341_output_enable E1
# Receiver
set_io --warn-no-port rx A2
set_io --warn-no-port rx_active D2
set_io --warn-no-port rx_data_available D1
set_io --warn-no-port rx_data_read E2
# Shared data bus
set_io --warn-no-port data[9] B6

31
interface2/rtl/top.v
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@@ -3,12 +3,11 @@
module top (
input clk_16mhz,
// DP8341 receiver
input dp8341_data_in,
output dp8341_rx_active,
input dp8341_register_read_n,
output dp8341_data_available,
input dp8341_output_enable,
// Receiver
input rx,
output rx_active,
output rx_data_available,
input rx_data_read,
// Shared data bus
inout [9:0] data,
@@ -33,21 +32,15 @@ module top (
.PLLOUTCORE(clk_19mhz)
);
wire dp8341_rx_disable;
assign dp8341_rx_disable = 0;
dp8341_shim #(
coax_rx #(
.CLOCKS_PER_BIT(8)
) dp8341 (
) coax_rx (
.clk(clk_19mhz),
.rx_disable(dp8341_rx_disable),
.data_in(dp8341_data_in),
.rx_active(dp8341_rx_active),
.register_read_n(dp8341_register_read_n),
.data_available(dp8341_data_available),
.output_enable(dp8341_output_enable),
.data_out(data)
.rx(rx),
.active(rx_active),
.data(data),
.data_available(rx_data_available),
.data_read(rx_data_read)
);
assign usb_pu = 0;