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https://github.com/lowobservable/coax.git
synced 2026-02-27 09:28:56 +00:00
First hardware test of coax_rx, increase clk frequency
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@@ -5,7 +5,7 @@ TINYPROG ?= tinyprog
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all: top.bin
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top.json: top.v coax_rx_bit_timer.v
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top.json: top.v coax_rx_bit_timer.v coax_rx.v
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prog: top.bin
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$(TINYPROG) -p top.bin
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@@ -311,7 +311,7 @@ module coax_rx (
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if (reset)
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begin
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bit_timer_reset = 1;
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bit_timer_reset <= 1;
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state_counter <= 0;
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state <= IDLE;
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@@ -13,12 +13,11 @@ set_io --warn-no-port clk_16mhz B2
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set_io --warn-no-port rx C2 # 4
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set_io --warn-no-port reset E1 # 9
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set_io --warn-no-port sample G2 # 10
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set_io --warn-no-port synchronized H1 # 11
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#set_io --warn-no-port rx_enable E1 # 9
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#set_io --warn-no-port rx_active G2 # 10
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#set_io --warn-no-port rx_data_available H1 # 11
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set_io --warn-no-port rx_active G2 # 10
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set_io --warn-no-port rx_error H1 # 11
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#set_io --warn-no-port rx_data_available xx # xx
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#set_io --warn-no-port rx_data_read J1 # 12
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# Shared data bus
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@@ -5,49 +5,49 @@ module top (
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// Receiver
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input rx,
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output rx_active,
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output rx_error,
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input reset,
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output sample,
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output synchronized,
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output debug,
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output usb_pu
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);
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// 19 MHz
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// 38 MHz
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//
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// icepll -i 16 -o 18.869
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wire clk_19mhz;
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// icepll -i 16 -o 37.738
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wire clk_38mhz;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000),
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.DIVF(7'b0100101),
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.DIVQ(3'b101),
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.DIVQ(3'b100),
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.FILTER_RANGE(3'b001)
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) clk_19mhz_pll (
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) clk_38mhz_pll (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk_16mhz),
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.PLLOUTCORE(clk_19mhz)
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.PLLOUTCORE(clk_38mhz)
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);
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reg rx_0 = 0;
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reg rx_1 = 1;
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always @(posedge clk_19mhz)
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always @(posedge clk_38mhz)
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begin
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rx_0 <= rx;
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rx_1 <= rx_0;
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end
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coax_rx_bit_timer #(
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.CLOCKS_PER_BIT(8)
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) rx_bit_timer (
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.clk(clk_19mhz),
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coax_rx #(
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.CLOCKS_PER_BIT(16)
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) coax_rx (
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.clk(clk_38mhz),
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.rx(rx_1),
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.reset(reset),
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.sample(sample),
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.synchronized(synchronized)
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.active(rx_active),
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.error(rx_error)
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);
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assign debug = rx_1;
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