First hardware test of coax_rx, increase clk frequency

This commit is contained in:
Andrew Kay
2020-07-05 16:13:32 -05:00
parent eacb8f0eea
commit c49a82f588
4 changed files with 20 additions and 21 deletions

View File

@@ -5,7 +5,7 @@ TINYPROG ?= tinyprog
all: top.bin
top.json: top.v coax_rx_bit_timer.v
top.json: top.v coax_rx_bit_timer.v coax_rx.v
prog: top.bin
$(TINYPROG) -p top.bin

View File

@@ -311,7 +311,7 @@ module coax_rx (
if (reset)
begin
bit_timer_reset = 1;
bit_timer_reset <= 1;
state_counter <= 0;
state <= IDLE;

View File

@@ -13,12 +13,11 @@ set_io --warn-no-port clk_16mhz B2
set_io --warn-no-port rx C2 # 4
set_io --warn-no-port reset E1 # 9
set_io --warn-no-port sample G2 # 10
set_io --warn-no-port synchronized H1 # 11
#set_io --warn-no-port rx_enable E1 # 9
#set_io --warn-no-port rx_active G2 # 10
#set_io --warn-no-port rx_data_available H1 # 11
set_io --warn-no-port rx_active G2 # 10
set_io --warn-no-port rx_error H1 # 11
#set_io --warn-no-port rx_data_available xx # xx
#set_io --warn-no-port rx_data_read J1 # 12
# Shared data bus

View File

@@ -5,49 +5,49 @@ module top (
// Receiver
input rx,
output rx_active,
output rx_error,
input reset,
output sample,
output synchronized,
output debug,
output usb_pu
);
// 19 MHz
// 38 MHz
//
// icepll -i 16 -o 18.869
wire clk_19mhz;
// icepll -i 16 -o 37.738
wire clk_38mhz;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000),
.DIVF(7'b0100101),
.DIVQ(3'b101),
.DIVQ(3'b100),
.FILTER_RANGE(3'b001)
) clk_19mhz_pll (
) clk_38mhz_pll (
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clk_16mhz),
.PLLOUTCORE(clk_19mhz)
.PLLOUTCORE(clk_38mhz)
);
reg rx_0 = 0;
reg rx_1 = 1;
always @(posedge clk_19mhz)
always @(posedge clk_38mhz)
begin
rx_0 <= rx;
rx_1 <= rx_0;
end
coax_rx_bit_timer #(
.CLOCKS_PER_BIT(8)
) rx_bit_timer (
.clk(clk_19mhz),
coax_rx #(
.CLOCKS_PER_BIT(16)
) coax_rx (
.clk(clk_38mhz),
.rx(rx_1),
.reset(reset),
.sample(sample),
.synchronized(synchronized)
.active(rx_active),
.error(rx_error)
);
assign debug = rx_1;