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Initial attempts at multiple word transmission

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This commit is contained in:
Andrew Kay
2020-02-12 19:44:43 -06:00
parent cc7023d35f
commit c859688931
2 changed files with 41 additions and 11 deletions
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46
interface2/rtl/coax_tx.v
View File

@@ -4,6 +4,7 @@ module coax_tx (
input clk,
input load,
input [9:0] data,
output full,
output active,
output reg tx, // ??? why does thie have to be reg?
output tx_delay,
@@ -35,7 +36,10 @@ module coax_tx (
reg [4:0] state = IDLE;
reg [4:0] next_state;
reg [4:0] previous_state;
reg [1:0] xxx = 2'b00;
reg [9:0] holding_data;
reg [9:0] output_data;
reg [3:0] output_data_counter;
reg parity_bit;
@@ -60,7 +64,7 @@ module coax_tx (
CODE_VIOLATION_3: next_state <= SYNC_BIT;
SYNC_BIT: next_state <= DATA;
DATA: next_state <= output_data_counter == 9 ? PARITY_BIT : DATA;
PARITY_BIT: next_state <= END_1;
PARITY_BIT: next_state <= xxx[1] ? SYNC_BIT : END_1;
END_1: next_state <= END_2;
END_2: next_state <= END_3;
END_3: next_state <= IDLE;
@@ -72,6 +76,7 @@ module coax_tx (
always @(posedge clk)
begin
previous_state <= state;
state <= next_state;
if (bit_counter == CLOCKS_PER_BIT - 1)
@@ -81,9 +86,22 @@ module coax_tx (
if (load && !previous_load)
begin
if (xxx[1])
begin
// TODO: error...
end
else
begin
// TODO: make this more intelligent in the case of both
// data registers being empty!
xxx <= { 1'b1, xxx[0] };
holding_data <= data;
end
if (state == IDLE)
begin
output_data <= data;
bit_counter <= 0;
// Let's go!
@@ -93,24 +111,30 @@ module coax_tx (
previous_load <= load;
if (state == SYNC_BIT)
if (state == SYNC_BIT && state != previous_state)
begin
xxx <= { 1'b0, xxx[1] };
output_data <= holding_data;
output_data_counter <= 0;
parity_bit <= 1; // Even parity includes sync bit
end
else if (state == DATA)
else if (state == DATA && bit_strobe)
begin
if (bit_strobe)
begin
output_data <= { output_data[8:0], 1'b0 };
output_data_counter <= output_data_counter + 1;
output_data <= { output_data[8:0], 1'b0 };
output_data_counter <= output_data_counter + 1;
if (output_data[9])
parity_bit <= ~parity_bit;
end
if (output_data[9])
parity_bit <= ~parity_bit;
end
else if (state == PARITY_BIT && state != previous_state)
begin
xxx <= { xxx[1], 1'b0 };
end
end
assign full = xxx[1];
assign bit_strobe = (bit_counter == CLOCKS_PER_BIT - 1);
assign bit_first_half = (bit_counter < CLOCKS_PER_BIT / 2);

6
interface2/tests/coax_tx_tb.v
View File

@@ -37,6 +37,12 @@ module coax_tx_tb();
load = 1;
#8 load = 0;
#200
data = 10'b1111111111;
load = 1;
# 8 load = 0;
repeat(1000) @(posedge clk);
$finish;