Andrew Kay 6e9a981064 Fix bug in TX start sequence generation

2020-07-31 17:48:15 -05:00

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firmware

Make data bus setMode a little more efficient

2020-07-20 07:40:44 -05:00

pcb

PCB fabrication

2020-02-29 10:16:18 -06:00

rtl

Fix bug in TX start sequence generation

2020-07-31 17:48:15 -05:00

tests

Fix receiver start and end sequence detection

2020-07-10 22:15:53 -05:00

Makefile

Verilog templating

2020-02-04 22:11:14 -06:00