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55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
`default_nettype none
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module top (
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input clk_16mhz,
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// DP8341 receiver
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input dp8341_data_in,
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output dp8341_rx_active,
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input dp8341_register_read_n,
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output dp8341_data_available,
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input dp8341_output_enable,
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// Shared data bus
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inout [9:0] data,
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output usb_pu
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);
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// 19 MHz
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//
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// icepll -i 16 -o 18.869
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wire clk_19mhz;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000),
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.DIVF(7'b0100101),
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.DIVQ(3'b101),
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.FILTER_RANGE(3'b001)
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) clk_19mhz_pll (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk_16mhz),
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.PLLOUTCORE(clk_19mhz)
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);
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wire dp8341_rx_disable;
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assign dp8341_rx_disable = 0;
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dp8341_shim #(
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.CLOCKS_PER_BIT(8)
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) dp8341 (
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.clk(clk_19mhz),
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.rx_disable(dp8341_rx_disable),
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.data_in(dp8341_data_in),
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.rx_active(dp8341_rx_active),
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.register_read_n(dp8341_register_read_n),
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.data_available(dp8341_data_available),
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.output_enable(dp8341_output_enable),
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.data_out(data)
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);
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assign usb_pu = 0;
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endmodule
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