Andrew Kay 49abcf7e2b Add data, data_available and data_read

2020-02-18 07:55:13 -06:00

..

.gitignore

Verilog templating

2020-02-04 22:11:14 -06:00

coax_rx_tb.v

Add data, data_available and data_read

2020-02-18 07:55:13 -06:00

coax_tx_bit_timer_tb.v

Initial attempt at receiver

2020-02-17 20:47:46 -06:00

coax_tx_tb.v

Bit timer module

2020-02-14 20:13:01 -06:00

hello_world_tb.v

Hello world

2020-02-12 23:13:21 -06:00

Makefile

Initial attempt at receiver

2020-02-17 20:47:46 -06:00