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51 lines
756 B
Verilog
51 lines
756 B
Verilog
`default_nettype none
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module coax_tx_tb();
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reg clk = 0;
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initial
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begin
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forever
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begin
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#1 clk <= ~clk;
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end
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end
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reg load = 0;
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reg [9:0] data;
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wire tx;
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wire active;
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coax_tx #(
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.CLOCKS_PER_BIT(8)
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) dut (
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.clk(clk),
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.load(load),
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.data(data),
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.tx(tx),
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.active(active)
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);
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initial
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begin
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$dumpfile("coax_tx_tb.vcd");
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$dumpvars(0, coax_tx_tb);
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repeat(10) @(posedge clk);
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data = 10'b0000000101;
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load = 1;
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#8 load = 0;
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#200
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data = 10'b1111111111;
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load = 1;
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# 8 load = 0;
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repeat(1000) @(posedge clk);
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$finish;
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end
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endmodule
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