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sim: sim_core.hrl: describe user-mode execution context
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Mikael Pettersson
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erlang/apps/sim/src/sim_core.hrl
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113
erlang/apps/sim/src/sim_core.hrl
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%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% simulator for pdp10-elf
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%%% Copyright (C) 2020 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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%%%
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%%%=============================================================================
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%%%
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%%% PDP10 Core Definitions
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%%%
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%%% Words are 36 bits wide. The bits are numbered 0-35, left to right (most
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%%% significant to least significant). The left (more significant) half word
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%%% is bits 0-17, and the right (less significant) half word is bits 18-36.
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%%% Numbers use twos-complement representation, with bit 0 as the sign.
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%%%
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%%% A double word is two adjacent words treated as a single 72-bit entity,
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%%% where the word with the lower address is the more significant.
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%%%
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%%% Bits are numbered in decimal, most other numbers are in octal, in particular
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%%% accumulator numbers, addresses, and instruction codes are in octal.
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%%%
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%%% A virtual address on a fully extended processor is 30 bits, composed of a 12
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%%% bit section number (upper 12 bits) and an 18-bit section offset (lower 18
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%%% bits). Paging hardware divides each section into 512 pages of 512 words.
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%%% The address bits are numbered according to the right-justified position of
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%%% an address in a word. Thus bits 6-17 contain the section number, and bits
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%%% 18-35 the section offset.
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%%%
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%%% Single-section processors (PDP6, KA10, KI10, non-extended KL10, KS10) have
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%%% no section number in their virtual addresses, while the extended KL10 (aka
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%%% KL10B) only has 5 bit section numbers (bits 13-17).
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%%%
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%%% The program counter register, PC, contains a virtual address. Incrementing
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%%% PC increments its segment offset without propagating any carry into the
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%%% section number.
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%%%
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%%% Instructions are words. In the basic instruction format, bits 0-8 specify
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%%% the operation, and bits 9-12 (A) address an accumulator. The rest of the
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%%% word specifies how to calculate the effective address (E). Bit 13 (I)
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%%% specifies the type of addressing (indirect or not), bits 14-17 (X) specify
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%%% an index register, and bits 18-35 (Y) specify a memory location. Some
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%%% instructions use bits 9-12 to address flags or as an extension to the
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%%% instruction code.
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%%%
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%%% If an instruction does not use some part of the instruction word, that part
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%%% is reserved and MUST BE ZERO, unless otherwise specified.
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-ifndef(_SIM_CORE_HRL_).
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-define(_SIM_CORE_HRL_, true).
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-define(UINT_T(N), 0..((1 bsl (N)) - 1)).
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-type uint12_t() :: ?UINT_T(12).
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-type uint13_t() :: ?UINT_T(13).
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-type uint18_t() :: ?UINT_T(18).
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-type uint36_t() :: ?UINT_T(36).
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-type word() :: uint36_t().
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%%% Program Flags
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%%% Note: architecturally these occupy bits 0-12 (PDP10 bit numbering) of a
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%%% 36-bit word, but here we express them as occupying bits 12-0 (normal bit
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%%% numbering) of a 13-bit word. The bit numbers in the definitions are from
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%%% the XKL-1 specification.
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-define(PDP10_PF_NO_DIVIDE, (12-12)).
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-define(PDP10_PF_FLOATING_UNDERFLOW, (12-11)).
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-define(PDP10_PF_TRAP_1, (12-10)). % n/a on KA10 exec
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-define(PDP10_PF_TRAP_2, (12-9)). % n/a on KA10 exec
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-define(PDP10_PF_ADDRESS_FAILURE_INHIBIT, (12-8)). % n/a on KS10 and KA10 exec
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-define(PDP10_PF_PUBLIC, (12-7)). % n/a on XKL-1, KS10, and KA10 exec
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-define(PDP10_PF_USER_IN_OUT, (12-6)). % user mode; n/a on XKL-1 and KS10
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-define(PDP10_PF_PREVIOUS_CONTEXT_USER, (12-6)). % exec mode on KL10, KI10, KS10, and XKL-1
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-define(PDP10_PF_USER, (12-5)).
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-define(PDP10_PF_FIRST_PART_DONE, (12-4)).
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-define( PDP6_PF_BIS, (12-4)). % PDP6 only
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-define(PDP10_PF_FLOATING_OVERFLOW, (12-3)).
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-define( PDP6_PF_PC_CHANGE, (12-3)). % PDP6 only
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-define(PDP10_PF_CARRY_1, (12-2)).
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-define(PDP10_PF_CARRY_0, (12-1)).
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-define(PDP10_PF_OVERFLOW, (12-0)). % user mode
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-define(PDP10_PF_PREVIOUS_CONTEXT_PUBLIC, (12-0)). % exec mode on KL10, KI10
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-record(cpu,
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{ %% user-mode visible context
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pc_segment :: uint12_t() % PC register, high 12 bits
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, pc_offset :: uint18_t() % PC register, low 18 bits
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, ac :: tuple(uint36_t()) % array of 16 36-bit words
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, flags :: uint13_t() % status and condition bits
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%% TODO: add supervisor-mode handling:
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%% - correctly handle being in not-USER mode
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%% - ACS: array of 8 AC blocks, user AC is ACS[CAB]
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%% - CAB: Current AC Block index, 3 bits
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%% - PCS: Previous Context Section, 12 bits
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%% - PCU: Previous Context User, 1 bit
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%% - PAB: Previous AC Block, 3 bit
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}).
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-endif. % _SIM_CORE_HRL_
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