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sim: sim_boolean: handle ANDCB, add unit test

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This commit is contained in:
Mikael Pettersson
2020-07-24 19:57:59 +02:00
parent 6e6b176e78
commit 60bda89259
3 changed files with 32 additions and 0 deletions
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17
erlang/apps/sim/src/sim_boolean.erl
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@@ -30,6 +30,7 @@
, handle_ANDCAB/4
, handle_ANDCAI/4
, handle_ANDCAM/4
, handle_ANDCB/4
, handle_ANDCM/4
, handle_ANDCMB/4
, handle_ANDCMI/4
@@ -401,6 +402,22 @@ handle_IORB(Core, Mem, IR, EA) ->
fun(Core1, Mem1) -> handle_IORB(Core1, Mem1, IR, EA) end)
end.
%% ANDCB - And Complements of Both
-spec handle_ANDCB(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_ANDCB(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
CA = sim_core:get_ac(Core, AC),
Word = ((bnot CE) band (bnot CA)) band ((1 bsl 36) - 1),
sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> handle_ANDCA(Core1, Mem1, IR, EA) end)
end.
%% Miscellaneous ===============================================================
ea_address(#ea{section = Section, offset = Offset}) ->

1
erlang/apps/sim/src/sim_core.erl
View File

@@ -285,6 +285,7 @@ dispatch(Core, Mem, IR, EA) ->
8#435 -> sim_boolean:handle_IORI(Core, Mem, IR, EA);
8#436 -> sim_boolean:handle_IORM(Core, Mem, IR, EA);
8#437 -> sim_boolean:handle_IORB(Core, Mem, IR, EA);
8#440 -> sim_boolean:handle_ANDCB(Core, Mem, IR, EA);
_ ->
PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}