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https://github.com/mikpe/pdp10-tools.git
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sim: sim_shifts: new, handle LSH/LSHC, add unit tests
This commit is contained in:
Mikael Pettersson
@@ -280,6 +280,8 @@ dispatch(Core, Mem, IR, EA) ->
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8#215 -> sim_moves:handle_MOVEI(Core, Mem, IR, EA); % MOVMI = MOVEI
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8#216 -> sim_moves:handle_MOVMM(Core, Mem, IR, EA);
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8#217 -> sim_moves:handle_MOVMS(Core, Mem, IR, EA);
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8#242 -> sim_shifts:handle_LSH(Core, Mem, IR, EA);
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8#246 -> sim_shifts:handle_LSHC(Core, Mem, IR, EA);
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8#250 -> sim_moves:handle_EXCH(Core, Mem, IR, EA);
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8#251 -> sim_moves:handle_BLT(Core, Mem, IR, EA);
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8#252 -> sim_arithmetic:handle_AOBJP(Core, Mem, IR, EA);
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105
erlang/apps/sim/src/sim_shifts.erl
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105
erlang/apps/sim/src/sim_shifts.erl
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@@ -0,0 +1,105 @@
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%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% simulator for pdp10-elf
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%%% Copyright (C) 2020 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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%%%
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%%%=============================================================================
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%%%
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%%% 2.5 Shift and Rotate
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-module(sim_shifts).
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-export([ handle_LSH/4
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, handle_LSHC/4
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]).
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-include("sim_core.hrl").
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%% 2.5 Shift and Rotate ========================================================
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%% LSH - Logical Shift
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-spec handle_LSH(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_LSH(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = lsh(CA, EA#ea.offset),
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set_ac_next_pc(Core, Mem, AC, Word).
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%% LSHC - Logical Shift Combined
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-spec handle_LSHC(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_LSHC(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA0 = sim_core:get_ac(Core, AC),
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CA1 = sim_core:get_ac(Core, (AC + 1) band 8#17),
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{Word0, Word1} = lshc(CA0, CA1, EA#ea.offset),
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set_acs_next_pc(Core, Mem, AC, Word0, Word1).
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%% Miscellaneous ===============================================================
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lsh(CA, Offset) ->
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case Offset band (1 bsl 17) of
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0 -> % left shift
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Count = Offset band ((1 bsl 8) - 1),
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if Count >= 36 -> 0;
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true -> (CA band ((1 bsl (36 - Count)) - 1)) bsl Count
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end;
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_ -> % right shift
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Count = (-Offset) band ((1 bsl 8) - 1),
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if Count >= 36 -> 0;
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true -> CA bsr Count
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end
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end.
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lshc(CA0, CA1, Offset) ->
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case Offset band (1 bsl 17) of
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0 -> % left shift
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Count = Offset band ((1 bsl 8) - 1),
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if Count >= 72 ->
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{_Word0 = 0, _Word1 = 0};
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Count >= 36 ->
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Count1 = Count - 36,
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Word0 = (CA1 band ((1 bsl (36 - Count1)) - 1)) bsl Count1,
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{Word0, _Word1 = 0};
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true ->
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Word0 = ((CA0 band ((1 bsl (36 - Count)) - 1)) bsl Count) bor (CA1 bsr (36 - Count)),
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Word1 = ((CA1 band ((1 bsl (36 - Count)) - 1)) bsl Count),
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{Word0, Word1}
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end;
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_ -> % right shift
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Count = (-Offset) band ((1 bsl 8) - 1),
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if Count >= 72 ->
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{_Word0 = 0, _Word1 = 0};
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Count >= 36 ->
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Word1 = CA0 bsr (Count - 36),
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{_Word0 = 0, Word1};
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true ->
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Word0 = CA0 bsr Count,
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Word1 = ((CA0 band ((1 bsl Count) - 1)) bsl (36 - Count)) bor (CA1 bsr Count),
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{Word0, Word1}
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end
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end.
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set_acs_next_pc(Core, Mem, AC, Word0, Word1) ->
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set_ac_next_pc(sim_core:set_ac(Core, AC, Word0), Mem, (AC + 1) band 8#17, Word1).
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set_ac_next_pc(Core, Mem, AC, Word) ->
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
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161
erlang/apps/sim/test/sim_shifts_tests.erl
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161
erlang/apps/sim/test/sim_shifts_tests.erl
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@@ -0,0 +1,161 @@
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%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% simulator for pdp10-elf
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%%% Copyright (C) 2020 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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%%%
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%%%=============================================================================
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%%%
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%%% Test cases for 2.5 Shift and Rotate
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-module(sim_shifts_tests).
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-include("../src/sim_core.hrl").
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-include_lib("eunit/include/eunit.hrl").
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-define(DEFAULT_FLAGS, (1 bsl ?PDP10_PF_USER)).
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-define(LOW18(X), ((X) band ((1 bsl 18) - 1))).
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-define(LOW36(X), ((X) band ((1 bsl 36) - 1))).
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-define(INSN(OP, AC, I, X, Y),
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(((OP) bsl (35 - 8)) bor
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((AC) bsl (35 - 12)) bor
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((I) bsl (35 - 13)) bor
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((X) bsl (35 - 17)) bor
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?LOW18(Y))).
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-define(COMMA2(LEFT, RIGHT), ((?LOW18(LEFT) bsl 18) bor ?LOW18(RIGHT))). % LEFT,,RIGHT in MACRO-10
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-define(EA(S, O), #ea{section = S, offset = O, islocal = false}).
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-define(AC(A), ?EA(1, A)).
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-define(INSN_INVALID, ?INSN(0, 0, 0, 0, 0)).
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-define(OP_LSH, 8#242).
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-define(OP_LSHC, 8#246).
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%% 2.5 Shift and Rotate ========================================================
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%% LSH - Logical Shift
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lsh_test() ->
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ACS =
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[ {1, ?COMMA2(8#000111, 8#222333)} % AC1 = 000111222333
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],
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Prog1 =
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[ {1, 8#100, ?INSN(?OP_LSH, 1, 0, 0, 9)} % 1,,100/ LSH 1,9
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog1, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#111222, 8#333000)} % AC1 = 111222333000
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]),
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Prog2 =
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[ {1, 8#100, ?INSN(?OP_LSH, 1, 0, 0, -9)} % 1,,100/ LSH 1,-9
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog2, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#000000, 8#111222)} % AC1 = 000000111222
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]).
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%% LSHC - Logical Shift Combined
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lshc_test() ->
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ACS =
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[ {1, ?COMMA2(8#000111, 8#222333)} % AC1 = 000111222333
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, {2, ?COMMA2(8#444555, 8#666777)} % AC2 = 444555666777
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],
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Prog1 =
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[ {1, 8#100, ?INSN(?OP_LSHC, 1, 0, 0, 9)} % 1,,100/ LSHC 1,9
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog1, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#111222, 8#333444)} % AC1 = 111222333444
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, {?AC(2), ?COMMA2(8#555666, 8#777000)} % AC2 = 555666777000
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]),
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Prog2 =
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[ {1, 8#100, ?INSN(?OP_LSHC, 1, 0, 0, 45)} % 1,,100/ LSHC 1,55
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog2, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#555666, 8#777000)} % AC1 = 555666777000
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, {?AC(2), ?COMMA2(8#000000, 8#000000)} % AC2 = 000000000000
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]),
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Prog3 =
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[ {1, 8#100, ?INSN(?OP_LSHC, 1, 0, 0, -9)} % 1,,100/ LSHC 1,-9
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog3, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#000000, 8#111222)} % AC1 = 000000111222
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, {?AC(2), ?COMMA2(8#333444, 8#555666)} % AC2 = 333444555666
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]),
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Prog4 =
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[ {1, 8#100, ?INSN(?OP_LSHC, 1, 0, 0, -45)} % 1,,100/ LSHC 1,-55
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, {1, 8#101, ?INSN_INVALID} % 1,,101/ <invalid>
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],
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expect(Prog4, ACS, {1, 8#101}, ?DEFAULT_FLAGS,
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[ {?AC(1), ?COMMA2(8#000000, 8#000000)} % AC1 = 000000000000
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, {?AC(2), ?COMMA2(8#000000, 8#111222)} % AC2 = 000000111222
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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{Core, Mem} = init(Prog, ACs),
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{Core1, Mem1, {error, {sim_core, {dispatch, PC, _IR, _EA}}}} = sim_core:run(Core, Mem),
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ActualPC = {PC bsr 18, PC band ((1 bsl 18) - 1)},
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?assertEqual(ExpectedPC, ActualPC),
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?assertEqual(ExpectedFlags, Core1#core.flags),
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lists:foreach(fun({EA, ExpectedE}) ->
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{ok, ActualE} = sim_core:c(Core1, Mem1, EA),
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?assertEqual(ExpectedE, ActualE)
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end, ExpectedEs),
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sim_mem:delete(Mem).
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init(Prog, ACs) ->
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{PCSection, PCOffset} = prog_pc(Prog),
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Mem = init_mem(Prog),
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Core = init_core(PCSection, PCOffset, ACs),
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{Core, Mem}.
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prog_pc([{Section, Offset, _Word} | _Rest]) -> {Section, Offset}.
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init_mem(Prog) -> init_mem(Prog, sim_mem:new()).
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init_mem([], Mem) -> Mem;
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init_mem([{Section, Offset, Word} | Rest], Mem) ->
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init_word(Section, Offset, Word, Mem),
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init_mem(Rest, Mem).
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init_word(Section, Offset, Word, Mem) ->
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Address = (Section bsl 18) bor Offset,
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PFN = Address bsr 9,
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case sim_mem:mquery(Mem, PFN) of
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false -> sim_mem:mmap(Mem, PFN, 4+2, core);
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{_Prot, _What} -> ok
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end,
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ok = sim_mem:write_word(Mem, Address, Word).
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init_core(PCSection, PCOffset, ACs) ->
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#core{ pc_section = PCSection
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, pc_offset = PCOffset
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, acs = init_acs(ACs, list_to_tuple(lists:duplicate(16, 0)))
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, flags = ?DEFAULT_FLAGS
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}.
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init_acs([], ACS) -> ACS;
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init_acs([{AC, Val} | Rest], ACS) -> init_acs(Rest, setelement(AC + 1, ACS, Val)).
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