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sim: sim_halfword: new, handle HLL/HLLI/XHLLI/HLLM/HLLS, add unit tests
This commit is contained in:
Mikael Pettersson
@@ -317,6 +317,10 @@ dispatch(Core, Mem, IR, EA) ->
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8#475 -> sim_boolean:handle_SETO(Core, Mem, IR, EA); % SETOI = SETO
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8#476 -> sim_boolean:handle_SETOM(Core, Mem, IR, EA);
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8#477 -> sim_boolean:handle_SETOB(Core, Mem, IR, EA);
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8#500 -> sim_halfword:handle_HLL(Core, Mem, IR, EA);
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8#501 -> sim_halfword:handle_HLLI(Core, Mem, IR, EA); % XHLLI in non-zero sections
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8#502 -> sim_halfword:handle_HLLM(Core, Mem, IR, EA);
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8#503 -> sim_halfword:handle_HLLS(Core, Mem, IR, EA);
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_ ->
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PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
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{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
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115
erlang/apps/sim/src/sim_halfword.erl
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115
erlang/apps/sim/src/sim_halfword.erl
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@@ -0,0 +1,115 @@
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%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% simulator for pdp10-elf
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%%% Copyright (C) 2020 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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%%%
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%%%=============================================================================
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%%%
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%%% 2.8 Half-Word Data Transmission
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-module(sim_halfword).
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-export([ handle_HLL/4
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, handle_HLLI/4
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, handle_HLLM/4
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, handle_HLLS/4
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]).
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-include("sim_core.hrl").
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%% 2.8 Half-Word Data Transmission =============================================
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%% HLL - Half Word Left to Left
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-spec handle_HLL(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLL(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_left(CA, get_left(CE)),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HLLI(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLLI(Core, Mem, IR, #ea{section = Section0, offset = Offset, islocal = IsLocal}) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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%% Behave as XHLLI (2.8.1) in non-zero sections.
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Section1 =
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if IsLocal, Offset =< 8#17, Section0 > 1 -> 1; % change local AC address to global one
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true -> Section0
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end,
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Word = set_left(CA, Section1),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
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-spec handle_HLLM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLLM(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_left(CE, get_left(CA)),
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handle_writeback(Core, Mem, EA, Word);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HLLS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLLS(Core, Mem, IR, EA) ->
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%% "If A is zero, HLLS is a no-op; otherwise, it is equivalent to MOVE."
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%% This implies that redundant memory accesses should not be performed.
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AC = IR band 8#17,
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case AC of
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0 -> sim_core:next_pc(Core, Mem);
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_ ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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sim_core:next_pc(sim_core:set_ac(Core, AC, CE), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end
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end.
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%% Miscellaneous ===============================================================
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handle_writeback(Core, Mem, EA, Word) ->
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case sim_core:cset(Core, Mem, EA, Word) of
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{ok, Core1} -> sim_core:next_pc(Core1, Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), write, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, EA, Word) end)
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end.
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ea_address(#ea{section = Section, offset = Offset}) ->
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(Section bsl 18) bor Offset.
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get_left(Word) -> Word bsr 18.
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get_right(Word) -> Word band ((1 bsl 18) - 1).
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set_left(Word, Left) -> get_right(Word) bor (Left bsl 18).
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182
erlang/apps/sim/test/sim_halfword_tests.erl
Normal file
182
erlang/apps/sim/test/sim_halfword_tests.erl
Normal file
@@ -0,0 +1,182 @@
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%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% simulator for pdp10-elf
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%%% Copyright (C) 2020 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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%%%
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%%%=============================================================================
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%%%
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%%% Test cases for 2.8 Half-Word Data Transmission
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-module(sim_halfword_tests).
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-include("../src/sim_core.hrl").
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-include_lib("eunit/include/eunit.hrl").
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-define(DEFAULT_FLAGS, (1 bsl ?PDP10_PF_USER)).
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-define(LOW18(X), ((X) band ((1 bsl 18) - 1))).
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-define(INSN(OP, AC, I, X, Y),
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(((OP) bsl (35 - 8)) bor
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((AC) bsl (35 - 12)) bor
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((I) bsl (35 - 13)) bor
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((X) bsl (35 - 17)) bor
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?LOW18(Y))).
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-define(COMMA2(LEFT, RIGHT), ((?LOW18(LEFT) bsl 18) bor ?LOW18(RIGHT))). % LEFT,,RIGHT in MACRO-10
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-define(INSN_INVALID, ?INSN(0, 0, 0, 0, 0)).
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-define(OP_MOVEI, 8#201).
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-define(OP_MOVSI, 8#205).
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-define(OP_HLL, 8#500).
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-define(OP_HLLI, 8#501).
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-define(OP_XHLLI, ?OP_HLLI).
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-define(OP_HLLM, 8#502).
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-define(OP_HLLS, 8#503).
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%% 2.8 Half-Word Data Transmission =============================================
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%% HLL - Half Word Left to Left
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hll_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HLL, 1, 0, 0, 8#200)} % 1,,101/ HLL 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 1)} % AC1 = 1,,1
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]).
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hlli_test() ->
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%% In section 0, HLLI clears AC left.
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Prog =
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[ {0, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 0,,100/ MOVSI 1,1
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, {0, 8#101, ?INSN(?OP_HLLI, 1, 0, 0, 0)} % 0,,101/ HLLI 1,0
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, {0, 8#102, ?INSN_INVALID} % 0,,102/ <invalid>
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],
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expect(Prog, [], {0, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, 0} % AC1 = 0
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]).
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xhlli_ac_test() ->
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%% In non-zero sections, XHLLI loads the EA's section number into AC left.
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%% Check that a local AC address is converted to a global one.
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Prog =
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[ {2, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 0,,100/ MOVEI 1,1
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, {2, 8#101, ?INSN(?OP_XHLLI, 1, 0, 0, 0)} % 0,,101/ XHLLI 1,0
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, {2, 8#102, ?INSN_INVALID} % 0,,102/ <invalid>
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],
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expect(Prog, [], {2, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 1)} % AC1 = 1,,1
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]).
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xhlli_non_ac_test() ->
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%% In non-zero sections, XHLLI loads the EA's section number into AC left.
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%% Check that the section of a non-AC EA is loaded as-is.
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Prog =
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[ {2, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 0,,100/ MOVEI 1,1
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, {2, 8#101, ?INSN(?OP_XHLLI, 1, 0, 0, 8#20)} % 0,,101/ XHLLI 1,20
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, {2, 8#102, ?INSN_INVALID} % 0,,102/ <invalid>
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],
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expect(Prog, [], {2, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(2, 1)} % AC1 = 2,,1
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]).
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hllm_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HLLM, 1, 0, 0, 8#200)} % 1,,101/ HLLM 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(0, 1)} % 1,,200/ 0,,1
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(1, 1)} % C(1,,200) = 1,,1
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]).
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hlls_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HLLS, 1, 0, 0, 8#200)} % 1,,101/ HLLS 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(1, 0)} % AC1 = 1,,0
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]).
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hlls_no_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 0, 0, 0, 1)} % 1,,100/ MOVEI 0,1
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, {1, 8#101, ?INSN(?OP_HLLS, 0, 0, 0, 8#200)} % 1,,101/ HLLS 0,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(0, 1)} % AC0 = 0,,1
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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{Core, Mem} = init(Prog, ACs),
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{Core1, Mem1, {error, {sim_core, {dispatch, PC, _IR, _EA}}}} = sim_core:run(Core, Mem),
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ActualPC = {PC bsr 18, PC band ((1 bsl 18) - 1)},
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?assertEqual(ExpectedPC, ActualPC),
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?assertEqual(ExpectedFlags, Core1#core.flags),
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lists:foreach(fun({EA, ExpectedE}) ->
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{ok, ActualE} = sim_core:c(Core1, Mem1, EA),
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?assertEqual(ExpectedE, ActualE)
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end, ExpectedEs),
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sim_mem:delete(Mem).
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init(Prog, ACs) ->
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{PCSection, PCOffset} = prog_pc(Prog),
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Mem = init_mem(Prog),
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Core = init_core(PCSection, PCOffset, ACs),
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{Core, Mem}.
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prog_pc([{Section, Offset, _Word} | _Rest]) -> {Section, Offset}.
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init_mem(Prog) -> init_mem(Prog, sim_mem:new()).
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init_mem([], Mem) -> Mem;
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init_mem([{Section, Offset, Word} | Rest], Mem) ->
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init_word(Section, Offset, Word, Mem),
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init_mem(Rest, Mem).
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init_word(Section, Offset, Word, Mem) ->
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Address = (Section bsl 18) bor Offset,
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PFN = Address bsr 9,
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case sim_mem:mquery(Mem, PFN) of
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false -> sim_mem:mmap(Mem, PFN, 4+2, core);
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{_Prot, _What} -> ok
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end,
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ok = sim_mem:write_word(Mem, Address, Word).
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init_core(PCSection, PCOffset, ACs) ->
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#core{ pc_section = PCSection
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, pc_offset = PCOffset
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, acs = init_acs(ACs, list_to_tuple(lists:duplicate(16, 0)))
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, flags = ?DEFAULT_FLAGS
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}.
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init_acs([], ACS) -> ACS;
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init_acs([{AC, Val} | Rest], ACS) -> init_acs(Rest, setelement(AC + 1, Val, ACS)).
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